Abstract: A method for manufacturing a semiconductor device in which lower cost can be realized, a wiring with favorable coverage can be formed in a contact hole having a large aspect ratio, wiring capacitance can be reduced and a multilayer wiring can be formed, can be provided.

Abstract: A semiconductor device includes a patterned conductive layer on which an initial dielectric film is deposited by a non-etching deposition process. A second dielectric film is then deposited on the initial dielectric film by high-density plasma chemical vapor deposition (HDP CVD). The HDP CVD process etches the second dielectric film as it is being deposited, thereby smoothing the surface of the second dielectric film. The initial dielectric film insulates the patterned conductive layer from the plasma used in the HDP CVD process, so that plasma charge is not conducted to underlying oxide films, such as gate oxide films, and does not cause oxide damage.

Abstract: The present invention is directed to a method of forming a dual damascene pattern in a fabrication process of a semiconductor device, which is capable of simplifying a fabrication process of a semiconductor device by filling a via hole with a photoresist, using a reflow phenomenon of the photoresist, in an ashing process.

Abstract: A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

Abstract: A transmission type display includes a thin film transistor for driving a pixel electrode, which transistor is provided on a substrate, and a conductive shield layer provided at a position over the thin film transistor and under the pixel electrode. A first planarization film is formed to bury an irregular contour of the thin film transistor and the shield layer is disposed on the planarized surface of the first planarization film, and a second planarization film is formed to bury steps of the shield layer, and the pixel electrode is disposed on the planarized surface of the second planarization film. Since the transmission type display has the structure in which the conductive shield layer is put between the upper second planarization film and the lower first planarization film each of which is made from an insulating material, the shielding performance and the alignment characteristic of the display can be improved.

Abstract: Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.

Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-ball metallic layer is formed over the active surface of the wafer. A second under-ball metallic layer is formed over the first under-ball metallic layer. A portion of the second under-ball metallic layer is removed to expose the first under-ball metallic layer. A plurality of solder blocks is implanted over the second under-ball metallic layer. A reflux operation is conducted and then the exposed first under-ball metallic layer is removed so that only the first under-ball metallic layer underneath the second under-ball metallic layer remains.

Abstract: The present invention provides exemplary methods, apparatus and systems for planarizing an insulating layer, such as a borophosphosilicate glass (BPSG) layer, deposited over a substrate. In one embodiment, a substrate (140) is inserted into a substrate processing chamber and a BPSG layer (142) is deposited thereover. The BPSG layer has an upper surface that is generally non-planar, due in part to the underlying nonplanar substrate surface (130). The substrate is exposed to an ultraviolet (UV) light (160) at conditions sufficient to cause a reflow of the BPSG layer so that the BPSG layer upper surface (150) is generally planar. In this manner, photonic energy is used to promote BPSG reflow, thereby reducing the thermal budget requirements for such a process.

Abstract: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.

Abstract: A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.

Abstract: A dual damascene process for producing interconnects. A dielectric layer is formed over the surface of a semiconductor substrate which comprises conductive layers or MOS devices. The dielectric layer is patterned to form trench openings and a metal layer is deposited over the dielectric layer to fill the plurality of trenches. A photoresist layer is formed over the metal layer and defined to form via hole patterns above the trenches. The metal layer and the dielectric layer are etched with the patterned photoresist layer as a mask to form a plurality of via holes exposing the underlying conductive layer or MOS devices and a dual damascene opening is formed.

Abstract: A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface layer having a lower melting point than the base layer. In this way, a composite film having two layers is created. After reflow, the surface layer can be removed using conventional methods.

Abstract: A process for fabricating an interconnect for contact holes includes forming contact holes in an insulation layer leading to a first interconnect layer, cleaning the hole surface, forming a barrier layer on the hole surface, forming an AlGeCu-containing second interconnect layer on the insulation surface by a low-temperature PVD process to fill up the contact holes, forming and patterning a mask layer, and patterning the second interconnect layer by an anisotropic etching process using the mask layer. Due to the relatively small grain sizes and precipitations that are formed in the process, the layer can be patterned directly in a subsequent patterning step, resulting in an extremely reliable and inexpensive interconnect that is easy to integrate in existing process sequences.

Abstract: A manufacturable method for forming a highly reliable electrical interconnection. An electrical interconnection pattern is first formed in a dielectric layer on a semiconductor substrate as recessed regions in the dielectric layer. A conductive layer primarily comprising copper is thereafter deposited over the surface and in the recessed regions of the dielectric layer. The conductive layer is then reflowed to fill the recessed regions of the dielectric layer with substantially no void formation. This reflow process may also be used to improve the step coverage of any such copper layer deposited over the surface of a substrate to be used in conjunction with alternate techniques for forming electrical interconnections including photoresist patterning and etch.

Abstract: A manufacturable method for forming a highly reliable electrical interconnection. An electrical interconnection pattern is first formed in a dielectric layer on a semiconductor substrate as recessed regions in the dielectric layer. A conductive layer primarily comprising copper is thereafter deposited over the surface and in the recessed regions of the dielectric layer. The conductive layer is then reflowed to fill the recessed regions of the dielectric layer with substantially no void formation. This reflow process may also be used to improve the step coverage of any such copper layer deposited over the surface of a substrate to be used in conjunction with alternate techniques for forming electrical interconnections including photoresist patterning and etch.

Abstract: Micromachined extrusions on the micrometer scale is realized using compressive stresses resulting from electromigration-induced mass transport in planarized conductors. Extrusions are formed through simple die patterns etched through a passivation layer overlaying the conductors.

Abstract: A method comprising determining a polishing profile produced by a polishing tool and manufacturing a process layer with a surface profile prior to polishing operations based upon the determined polishing profile of the polishing tool.

Abstract: Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivation layer a thermally annealed planarizing passivation layer. By employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.

Abstract: A method for fabricating a semiconductor device is disclosed, which reduces defects of a device by improving the process to improve the production yield.

Abstract: A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.

Abstract: There is formed on a semiconductor substrate a lamination of a first insulating film of nondoped silicon glass or the like and, on this first insulating film, a second insulating film of boron phosphor silicate glass or the like, with a conductor layer between the two insulating films. A hole is first dry-etched in the second insulating film, leaving the substrate surface covered by the first insulating film. Then the second insulating film is heated to a reflow temperature such that the hole is thermally deformed, flaring as it extends away from the insulating film. Then a second hole is dry-etched in the first insulating film through the first recited hole in the second insulating film, with the consequent exposure of the semiconductor surface. Then a contract electrode is fabricated by filling the first and the second hole with an electroconductive material into direct contact with the substrate surface.

Abstract: A process for forming silicate glass layers on substrates is disclosed. A silicate glass layer is first deposited onto a substrate, such as a semiconductor wafer. The wafer is then placed in a thermal processing chamber and heated in the presence of a reactive gas. The object is heated to a temperature sufficient for reflow of the silicate glass. In one embodiment, the atmosphere contained within the processing chamber comprises steam in combination with a reactive gas. The reactive gas can be, for instance, hydrogen, oxygen, nitrogen, dinitrogen oxide, ozone, hydrogen peroxide, atomic and/or molecular hydrogen, or radicals or mixtures thereof.

Abstract: A workpiece is processed which includes a multiplicity of recesses formed in the exposed surface. The invention includes depositing a first barrier layer 13 of for example, titanium nitride, a second layer 11 of aluminium alloy and a third relatively thin layer 12 of titanium nitride and then exposing the sandwich of layers to elevated heat and pressure so that the second layer is deformed to fill the recesses 10.

Abstract: A layer of doped oxide glass is deposited on a semiconductor device in a chemical vapor deposition chamber by reacting gaseous sources of silicon, ozone and at least one boron or phosphorus dopant in a carrier gas, the ozone being present in a ratio of about 9-15 weight percent of the carrier gas. The deposited layer of doped oxide glass contains no greater than about 4 weight percent each of boron and phosphorus concentration and is annealed at a temperature no greater than about 700° C. for a time sufficient to soften and outgas any residual moisture in the oxide glass layer and level the upper surface to a desired degree.

Abstract: A method for manufacturing a metal interconnection includes the steps of, preparing an active matrix provided with a substrate, an insulating layer and an opening formed through the insulating layer, forming a diffusion barrier layer on surfaces of the opening and the insulating layer, forming a protection layer on the diffusion barrier layer, forming a first metal layer into the opening and upon the protection layer, forming a second metal layer on the first metal layer, and polishing back the first and the second metal layer to a top surface of the insulating layer, thereby forming a metal interconnection.

Abstract: A method for manufacturing a semiconductor device that fills contact holes with conductive material such as aluminum or an aluminum alloy. A semiconductor device is manufactured by the process of forming an opening such as a contact hole in an interlayer dielectric film formed on a semiconductor substrate having a device element formed thereon. A first film and a second film made of conductive material such as aluminum or an alloy containing aluminum are formed on the interlayer dielectric film and the opening. The second film is then gradually cooled.

Abstract: A method of anastomosing two hollow bodily organs using a bioadhesive. The method involves apposing apertures in the organs to be joined and applying the bioadhesive, thereby joining the apertures in the organs and allowing movement of fluid or semi-solid material from one of the two organs to the second organ. The invention also relates to a device for anastomosing two hollow organs. The device has two inflatable balloons, one of which is placed into the lumen each of the two organs to be joined. Inflation of the balloons holds the apertures together while the bioadhesive is applied. The device allows anastomosis of blood vessels through endoscopic means.

Abstract: A relatively high-resistance first compound film of a semiconductor and a metal is formed on a surface of a semiconductor region in self alignment by a relatively low-temperature first annealing. The relatively high-resistance first compound film is converted into a relatively low-resistance second compound film by a relatively high-temperature second annealing which is done after an insulating film is formed above the first compound film. Hence, the annealing aiming at decreasing a resistance of the compound film can serve as another annealing as well. The number of times of annealing applied to the compound film the resistance of which has been decreased is small, and a thinning effect of the compound film can be suppressed.

Abstract: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.

Abstract: A fabrication method for a dual damascene structure is provided. A barrier layer and a copper seed layer are formed on a substrate comprising a dual damascene opening, wherein the barrier layer and the copper seed layer cover the dual damascene opening. A sacrificial layer is then formed on the copper seed layer, filling the dual damascene opening. Using the copper seed layer as an etch stop layer, the sacrificial layer is etch back. The exposed copper seed layer is then removed, followed by completely removing the sacrificial layer. A metal copper layer is formed in the dual damascene opening by plating, filling the opening of the dual damascene opening.

Abstract: A dual damascene manufacturing process, which is applicable on a dual damascene structure, is described. The etching stop layer at a bottom of the trench line is removed followed by a thermal treatment to smooth out the surface at the bottom of the trench line and in the via to form a larger and smoother opening at the top part of the via. The via and the trench line are then filled with a barrier layer and a metal layer.

Abstract: A method of forming an organic low k layer, for use as an interlevel dielectric layer in semiconductor integrated circuits, has been developed. An organic low k layer, such as a poly arylene ether layer, with a dielectric constant between about 2.6 to 2.8, is applied on an underlying metal interconnect pattern. The moisture contained in the as applied, organic low k layer, or the moisture absorbed by the organic low k layer, due to exposure to the environment, is then reduced via a high density plasma treatment, performed in a nitrogen ambient. The reduction in moisture can be accomplished, even when the organic low k layer had been exposed to the environment for a period of time as great as three months. The dielectric constant, of the organic low k layer, remains unchanged, as a result of the high density plasma treatment.

Abstract: This marking method is carried out with an object to form a mark of high visibility on a surface of a metallic layer of such as a cover plate of a semiconductor device or the like without generating metallic debris or the like. According to this method, on a marking area of a metallic layer with a matte surface (Rmax: 0.5 to 5 &mgr;m), a laser beam is illuminated, thereby the metallic layer is melted, then re-solidified, thereby minute unevenness on the surface of the metallic layer is averaged and erased to be smooth. Thus formed marking portion reflects light specularly and is different in light reflectivity from an underlying portion which scatters light (diffuse reflection). Due to the difference of reflectivity, the marking portion can be visually discerned with excellency.

Abstract: An improved semiconductor device structure comprises insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low-melting point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

Abstract: The invention comprises methods of depositing silicon oxide material onto a substrate. In but one aspect of the invention, a method of depositing a silicon oxide containing layer on a substrate includes initially forming a layer comprising liquid silicon oxide precursor onto a substrate. After forming the layer, the layer is doped and transformed into a solid doped silicon oxide containing layer on the substrate. In a preferred implementation, the doping is by gas phase doping and the liquid precursor comprises Si(OH)4. In the preferred implementation, the transformation occurs by raising the temperature of the deposited liquid precursor to a first elevated temperature and polymerizing the deposited liquid precursor on the substrate. The temperature is continued to be raised to a second elevated temperature higher than the first elevated temperature and a solid doped silicon oxide containing layer is formed on the substrate.

Abstract: A contact layer is used, for example, as a liner for the fabrication of electrical contacts in contact holes. The contact layer is fabricated in two steps, in a first step a first contact layer is deposited, in which only a small proportion of the particles to be sputtered is ionized. In a second sputtering step, a second contact layer is sputtered, in the course of whose fabrication a larger proportion of the particles to be sputtered is ionized. The procedure ensures that the first contact layer is disposed as a protective layer on the substrate by gentle sputtering before the second contact layer is sputtered.

Abstract: A method of defining a mask pattern for a photoresist layer in semiconductor fabrication. The method coats a photoresist layer containing an additive on a dielectric layer. The photoresist layer has an opening formed therein. The additive is 2,2′-azo-bis-isobutyronitride (AIBN) or phenyl-azo-triphenylmethane. The photoresist layer is exposed and developed. Then, a hard baking step is performed. A UV curing or a hot curing step is performed on the photoresist layer. As a result, the additive in the photoresist layer reacts to form nitrogen (N2) gas. Nitrogen gas makes the photoresist layer expand. The opening is decreased by the expansion of the photoresist layer. The dielectric layer is etched according to the expanded photoresist layer so that a via or a trench, which is smaller than a conventional one, is formed.

Abstract: Methods of fabricating an interconnection to an underlying microelectronic layer include removing a portion of the insulation layer to form a plurality of contact holes having different contact sizes therethrough and thereby expose a portion of the microelectronic layer. A conductive material is deposited on the insulation layer and in the contact hole with a sufficient thickness such that a bridge is generated in the largest contact hole. The deposited conductive material is then reflowed to fill the contact hole and form an interconnection to the underlying microelectronic layer, by supplying a high pressure such that at least the void formed in the largest contact hole is filled. The conductive material may be planarized to thereby expose the insulation layer. The present invention may be applied to an asymmetrical contact hole, for example, a dual damascene structure.

Abstract: Disclosed is an apparatus for manufacturing a semiconductor device including a metal film which is formed on a semiconductor substrate in a film formation region containing the interior of a hole formed in the semiconductor substrate. The apparatus includes a degassing chamber, a film forming chamber, and a cooing chamber. The degassing chamber 34 is provided for carrying out a degassing process by heating the semiconductor substrate to a degassing temperature. The film forming chamber 40 is provided for forming a metal film on the film formation region in a state in which the semiconductor substrate is heated to a film formation temperature. The cooling chamber 38 is provided for cooling, after completion of the degassing process and before beginning of the formation of the metal film, the semiconductor substrate to a cold temperature being lower than the film formation temperature and in a range of −50° C. to 150° C.

Abstract: A semiconductor fabrication method is provided for forming an opening in a dielectric layer, which can help the resulting opening to be more accurately dimensioned to its specified size without being overly large. By this method, a first dielectric layer is formed from undoped silicate glass (USG) over the substrate, then a second dielectric layer is formed from an acid-resistant dielectric material over the first dielectric layer, and a third dielectric layer is subsequently formed from a thermal-flow dielectric material over the third dielectric layer. A thermal-flow process is performed to slightly planarize the third dielectric layer. Next, an isotropic etch-back process is performed to remove entirely the third dielectric layer and to remove partly the second dielectric layer partly until reaching a predefined plane in the second dielectric layer. A photolithographic and etching process is then performed to form an opening in the combined structure of the first and second dielectric layers.

Abstract: A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the oxidized portion is removed by an etch, followed by removal of the polish stop layer. The plug thus formed protrudes a controllable distance above the surrounding dielectric, providing good contact to subsequent conductive layers.

Abstract: A barrier metal that can be used in a semiconductor is to be made extremely thin. Further, the manufacturing steps of a semiconductor device are shortened to reduce its manufacturing cost. An insulating layer (e.g., a thermal nitride layer 10) with good step coverage formed on a surface of a conductor film such as lower electrodes 9 and 9a of a capacitor on a semiconductor substrate is transformed into a reformed layer 11, which serves as a conductive barrier layer. Alternatively, the insulating layer formed on the surface of the insulating layer on the semiconductor substrate is totally or partially reformed into the conductive barrier layer. This reforming process is conducted by heating the above-mentioned semiconductor substrate at a predetermined temperature and, applying a plasma-excited high melting-point metal onto the surface of the above-mentioned insulating layer. This high melting-point metal may be Ti, Ta, Ni, Mo, W or the like.

Abstract: Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.

Abstract: A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.

Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.

Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently.

Abstract: Disclosed is a method of forming a self-aligned contact to a semiconductor substrate by use of a sacrificial spacer. The sacrificial spacer has the advantage of self aligning metallization to the semiconductive substrate or to a polysilicon plug material without extra photolithography steps as are required in the prior art.

Abstract: A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A first metal layer is deposited over the insulating layer. A capacitor dielectric layer is deposited overlying the first metal layer. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top metal electrode. A flowable material layer is deposited overlying the capacitor dielectric and the top metal electrode and anisotropically etched away to leave spacers on sidewalls of the top metal electrode. A photoresist mask is formed overlying the capacitor dielectric and the top metal electrode wherein the spacers provide extra photoresist thickness at the sidewalls of the top metal layer.