Abstract: A method of planarizing a dielectric layer comprising the steps of providing a substrate having structures already formed thereon, and then forming a borophosphosilicate glass layer over the substrate. Next, a rapid thermal process is applied heating the borophosphosilicate layer to cause a thermal flow, and then the borophosphosilicate layer is etched back so that a planar surface is obtained. Finally, a passivation layer is formed over the borophosphosilicate glass layer to prevent the formation of pits in subsequent pre-metal wet etching operations.

Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.

Abstract: A device and method for planarizing a film layer device on a silicon wafer. The device has a circular track whose surface faces the track center, a carrier capable of moving along the track and carrying wafers around with their front surfaces facing the center, and a set of heating elements for heating the film layers on the wafers to make them fluid. Utilizing the centrifugal force on the film layer generated by the circular movement and the fluidity of the film layer provided by heating, planarization of the film layer is achieved.

Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining an opening in a layer of photoresist formed above a layer of dielectric material, heating the layer of photoresist to reduce the size of the opening in the layer of photoresist, and forming an opening in the layer of dielectric material that is defined by the reduced size opening in the layer of photoresist. The method further comprises removing the layer of photoresist and forming a conductive interconnection in the layer of dielectric material.

Abstract: A method of improving gap filling of dielectric layer by implantation is disclosed. When a plurality of semiconductor structures are formed on a semiconductor substrate, there are gaps between portions of the semiconductor structure. First, a dielectric layer is formed over the surface of the semiconductor structure and then an implantation process is employed to implant ions as BF2+, B3+ and F− into first dielectric layer and more particularly into part of the first dielectric layer that corresponds to sidewall of semiconductor structure. Afterwards, rapid thermal process is employed to form SiOF molecules and B2O5 molecules on the first dielectric layer, and then a second dielectric layer is formed over the first dielectric layer. Because SiOF molecules improve step coverage of the second dielectric layer formation and B2O5 molecules enhance fluidity of second dielectric layer during formation of the second dielectric layer.

Abstract: A method for monitoring bubble formation in and over a spin-on glass(SOG) layer during the CVD deposition of a superjacent insulative layer is described wherein a monitor wafer is processed either with or without a metal pattern. After a SOG layer has been deposited and cured, a layer of silicon oxide is deposited over it by CVD. If bubbles are formed during the silicon oxide deposition step as a result of out-gassing of the SOG layer, they are entrapped at or near the SOG/silicon oxide interface. The silicon oxide layer is then subjected to a buffered HF etch which exposes the bubbles either by opening them up by eroding the SOG layer underneath the oxide layer or by bringing the surface of the silicon oxide layer closer to the entrapped bubbles, thereby decorating them to make them visible to a white light scanning tool. The monitor wafer is initially scanned just prior to the SOG deposition to obtain a reference scan.

Abstract: A method of manufacturing an inter-metal dielectric layer. A substrate having a plurality of wires formed thereon is provided. A portion of the substrate is exposed to form an opening between the wires. The opening is filled with a flowable dielectric material, wherein a surface level of the flowable dielectric material is lower than that of the wires. A plurality of spacers is formed on the sidewall of the wires exposed by the flowable dielectric material. The flowable dielectric material is removed. An anisotropic deposition process with a poor-lateral-filling ability is performed to form a dielectric layer with a void under the spacer over the substrate.

Abstract: A method for fabricating a crack resistant inter-layer dielectric for a salicide process. The method includes forming an insulating layer on a provided substrate, forming a planarized inter-layer dielectric layer on the insulating layer, and performing a short-duration thermal treatment to increase the density of the inter-layer dielectric layer.

Abstract: Disclosed is a film formation method of an interlayer insulating film which is flattened to cover a wiring layer of a semiconductor integrated circuit device, in which a film-forming gas is activated by converting the film-forming gas into a plasma, the film-forming gas being composed of either a mixed gas containing a phosphorus-containing compound containing trivalent phosphorus, which takes a Si—O—P structure, and a silicon-containing compound containing at most one oxygen atom or an additional mixed gas prepared by adding an oxidative gas to said mixed gas; and a silicon-containing insulating film containing P2O5 is formed on a substrate.

Abstract: A method for annealing a contact in a doped dielectric layer without the occurrence of dopant diffusion problem by depositing a sacrificial barrier layer of oxide material in the contact opening which is capable of preventing diffusion of dopant ions into the contact opening during a high temperature reflow process for the doped dielectric layer and followed by a deposition of an electrically conductive metal into the contact opening.

Abstract: A method of forming an interlayer dielectric on a semiconductor device is disclosed. First, a phosphorous doped oxide layer is deposited on the semiconductor device to fill gaps and provide phosphorous for gettering. Then, an undoped oxide layer is deposited and planarized using chemical mechanical polishing (CMP). The undoped oxide layer is denser than the phosphorous doped oxide layer, so the undoped oxide layer can be polished more uniformly than the phosphorous doped oxide layer and can serve as a polish stop for a subsequent tungsten plug polish. Also, the denser undoped oxide layer serves as a more effective moisture barrier than the doped oxide layer. Overall fabrication process complexity can be reduced by performing both oxide depositions in a single operation with no intervening densification or CMP steps.

Abstract: A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN barrier. Furthermore, a copper-palladium gap-fill electroplating layer is electroplated over the dielectric oxide layer. Second, a copper-palladium annealing process is carried out. Then the copper-palladium electroplating surface is planarized by means of a chemical mechanical polishing (CMP) process. Third, the CoWP cap is self-aligned to the planarized copper-palladium alloy surface. Finally, a second IMD layer is deposited over the first IMD layer. Furthermore, a contact hole in the second dielectric layer over said CoWP cap layer is formed, and then the CoWP cap of the first IMD layer is connected with the copper-palladium alloy bottom surface of the second IMD layer directly.

Abstract: The present invention discloses a method for planarizing a semiconductor device used in an integrated circuit. According to the method, a semiconductor substrate on which a patterned layer having topology is formed, is loaded into a reactor chamber. Afterwards, an interlevel insulating layer is formed on the semiconductor substrate. Thereafter, a layer for the planarization containing a dopant is formed on the interlevel insulating layer. The dopant contained in the layer for the planarization, is diffused outwards from the surface of the layer. The dopant diffused outwards from the layer for the planarization is pumped out to the outside of the reactor chamber without introducing an inert gas to the reactor chamber. Finally, the layer for the planarization is flowed.

Abstract: A method of fabricating a landing pad. A gate electrode is formed on a substrate. The gate electrode has a top surface covered by a cap layer and a sidewall covered by a spacer. A polysilicon layer is formed to cover the gate. Using an oxygen based etchant to performed an isotropic chemical dry etching on the polysilicon layer, the polysilicon layer is planarized until a part of the spacer is exposed. The polysilicon layer is patterned to form a landing pad in contact with the substrate.

Abstract: A method for forming a high-quality aluminum-copper alloy pattern over a semiconductor substrate. The method first forms an aluminum-copper alloy layer over a semiconductor substrate, and then performs a rapid thermal processing operation to remelt copper extracts into the alloy bulk. Subsequently, a photoresist layer is formed over the alloy layer. Finally, the alloy layer is etched to transfer the pattern from the photoresist layer to the metallic alloy layer. Unlike a conventional method that can lead to abnormal conduction due to the presence of extracts that are difficult to etch, this invention uses a thermal operation to remove the extracts before etching is conducted. Hence, the masking effect due to etching is mostly prevented.

Abstract: An integrated circuit fabrication method for filling a high-aspect-ratio via with a metallization layer wherein there is provided a dielectric layer having a via therein. A wetting layer is deposited over the dielectric layer and within the via and the via sidewalls, the wetting layer being of a material which lowers the melting temperature of the metallization when combined with the metallization. The metallization layer is deposited over the wetting layer and the via but not completely filling the via with the metallization. The wetting agent with metallization thereon are heated to a temperature below the melting temperature of the metallization, the temperature being sufficient to cause the wetting layer to combine with the metallization, lower the melting temperature of the metallization to the temperature or below the heating temperature to cause the metallization to flow and fill the via.

Abstract: A method of forming micro solder balls for use in a C4 process is described. The solder balls are formed by laying down a peel-away photoresist layer, forming holes in the photoresist layer to expose electrical contacts, depositing a solder layer over the photoresist, forming solder areas in the holes and then, using a tape liftoff process to remove the solder layer and photoresist layer while leaving solder areas in the holes. The solder areas are then heated to allow solder balls to form.

Abstract: A method of forming an aluminum-based layer mainly including aluminum on a surface of an insulating layer and within a hole formed in the insulating layer. The method includes the steps of: carrying out a chemical vapor deposition to deposit the aluminum-based layer on the surface of the insulating layer and also to incompletely fill the hole to not less than 75% by volume of the hole by use of a source including at least one of alkyl groups and hydrogen so that a surface of the aluminum-based layer is terminated by the at least one of alkyl groups and hydrogen included in the source, and so that the surface of the aluminum-based layer is free of any natural oxide film; and carrying out a heat treatment, without formation of any natural oxide film on the surface of the aluminum-based layer, for causing a re-flow of the aluminum-based layer, whereby the at least one of alkyl groups and hydrogen promotes a migration of aluminum atoms on the surface of the aluminum-based layer.

Abstract: An improved semiconductor device structure comprises insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low-melting point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

Abstract: A method for forming an interconnection in a semiconductor element includes a process for forming a groove on an underlying substrate so as to correspond to the designed pattern of the interconnection. An underlayer for improving crystalline orientation of the interconnection is formed on the underlying substrate having the groove. A thin film of interconnection material is formed in the groove and a heattreatment process is carried out to ensure that the groove is filled with the thin film of the interconnection material. Formation of the interconnection is completed by polishing the surface of the thin film by a predetermined quantity.

Abstract: A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: Conductive structures, conductive lines, conductive SRAM lines, integrated circuitry, SRAM cells, and methods of forming the same are described. In one embodiment, a substrate is provided and a layer comprising TiN is physical vapor deposited over the substrate having greater than or equal to about 90% by volume <200> grain orientation. In another embodiment, at least two components are electrically connected by forming a layer of TiN over a substrate having the desired by-volume concentration of <200> grain orientation, and etching the layer to form a conductive line. In a preferred embodiment, conductive lines formed in accordance with the invention electrically connect at least two SRAM components and preferably form cross-coupling electrical interconnections between first and second inverters of an SRAM cell.

Abstract: Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.

Abstract: A method for creating a metal filled, high aspect ratio, contact opening, in thick insulator layers, allowing contact between a metal interconnect structure and a region of a semiconductor substrate, has been developed. The process features creating a stacked contact hole opening, comprised of a upper contact hole opening, of a specific diameter size, overlying a lower contact hole opening, having an opening larger in diameter than the opening used for the upper contact hole opening. The lower contact hole opening is created via an anisotropic RIE procedure, followed by a wet etch procedure, used to enlarge the diameter of the lower contact hole opening. The upper contact hole opening, created using an anisotropic RIE procedure, is formed using the original diameter opening, used previously for the pre-wet etched, lower contact hole opening, and is easily aligned to a metal filled, enlarged lower contact hole opening.

Abstract: A method of forming a dual damascene structure including contacts and interconnects over a substrate is disclosed. The method comprises the steps of: forming an insulating layer on said substrate; forming a nitride layer over said insulating layer; forming a cap oxide layer over said nitride layer; patterning and etching said insulating layer, nitride layer, and cap oxide layer to correspond to the location of said contacts; patterning and etching said nitride layer and said cap oxide layer to correspond to the pattern of said interconnects; and performing a reflow step.

Abstract: The present invention is a method and apparatus for filling voids in a substrate with a desired material to form conductive components and/or other features on the substrate. In one embodiment in accordance with the principles of the present invention, a substrate with voids is covered with a first layer of material and then a second layer of material is formed on top of the first layer. The first layer is deformable at a deformation temperature, while the second layer has a higher yield strength than the first layer and is substantially non-deformable at the deformation temperature. The second layer, for example, may be a rigid and/or substantially incompressible layer that distributes a driving force to the first layer. The second layer is then pressed against the first layer at a temperature equal to or greater than the deformation temperature to drive portions of the first layer into the voids in the substrate.

Abstract: A field effect transistor available for 1 giga-bit dynamic random access memory device has a two-layer gate structure consisting of a lower layer of nitrogen-containing silicon and an upper layer of refractory metal, and the nitrogen-containing silicon effectively prevents the gate oxide layer from alkaline metals diffused from the refractory metal.

Abstract: A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12.

Abstract: The present invention relates to a method for forming a VIA in an Inter Metal Dielectric (IMD) containing Spin On Glass (SOG). The IMD is formed by 1) depositing a first silicon dioxide layer through a Chemical Vapor Deposition (CVD) process; 2) depositing a Spin On Glass (SOG) layer; and 3) depositing a second silicon dioxide layer through a Chemical Vapor Deposition process. Afterward, before the VIA is formed by an Inter Metal Dielectric (IMD) etching process, a selective ion implantation process is performed to densify the Spin On Glass(SOG) layer. By this arrangement, the outgassing effect of the Spin On Glass (SOG) during a subsequent metal deposition process can be therefore prevented.

Abstract: A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal.

Abstract: The invention comprises methods of depositing silicon oxide material onto a substrate. In but one aspect of the invention, a method of depositing a silicon oxide containing layer on a substrate includes initially forming a layer comprising liquid silicon oxide precursor onto a substrate. After forming the layer, the layer is doped and transformed into a solid doped silicon oxide containing layer on the substrate. In a preferred implementation, the doping is by gas phase doping and the liquid precursor comprises Si(OH).sub.4. In the preferred implementation, the transformation occurs by raising the temperature of the deposited liquid precursor to a first elevated temperature and polymerizing the deposited liquid precursor on the substrate. The temperature is continued to be raised to a second elevated temperature higher than the first elevated temperature and a solid doped silicon oxide containing layer is formed on the substrate.

Abstract: A process for fabricating interconnection of a semiconductor device is provided which allows the physical vapor deposition and reflow treatment to be performed in different apparatuses and requires no surface treatment prior to the reflow treatment. The process comprises the steps of forming a metallic interconnection material layer on a substrate by means of physical vapor deposition using a metallic interconnection material; forming an oxidation preventive film on the metallic interconnection material layer; subjecting the metallic interconnection material layer to reflow treatment to form a complete solid solution of the components constituting the oxidation preventive film with those of the metallic interconnection material layer; and patterning the metallic interconnection material layer to form an interconnection.

Abstract: A method for forming metal lines of a semiconductor device, which is capable of eliminating a problem in the planarization caused by the chemical vapor deposition method, namely, the formation of a thin film having a rough surface, an increase in the impurity concentration and an influence on an under layer. The method includes the steps of depositing an anti-diffusion metal layer over a structure formed with a metal contact, depositing a metal layer such as a copper film or aluminum film over the anti-diffusion metal layer in accordance with a physical vapor deposition method, annealing the resulting structure in a chamber maintained at a high temperature and high vacuum without losing the vacuum, thereby planarizing the structure.

Abstract: An underlying Al alloy wiring 3 and an inter-layer insulation film 4 are formed sequentially on a semiconductor substrate 1 via an inter-layer insulation film 2. An inter-layer insulation film 5 highly hygroscopic and containing much moisture is made and etched back to flush depressions by the underlying Al alloy wiring 3. After an inter-layer insulation film 6 is made, a contact-hole C is made in the inter-layer insulation films 6 and 4. After that, prior to making a TiN/Ti film 7, gases are removed from the inter-layer insulation films 4 through 6 by annealing. The TiN/Ti film 7 is made as thick as 80 nm. In an alternative version, after the inter-layer insulation film is etched back, annealing is done to remove gases especially from the inter-layer insulation film 5.

Abstract: A method of manufacturing the semiconductor device comprises elements described below;(a) forming a wiring pattern on an insulating film on a semiconductor substrate,(b) forming a reflow SiO.sub.2 film having a reflow shape by introducing SiH.sub.4 gas and H.sub.2 O.sub.2 gas into a reaction chamber which accommodates said semiconductor substrate and mutually reacting the SiH.sub.4 and H.sub.2 O.sub.2 gases in a temperature range of about -10.degree. C. to about +10.degree. C. in a vacuum of about 665 Pa or below,(c) plasma treating a surface of said reflow SiO.sub.2 film by introducing a gas including fluorine into said reaction chamber and discharging plasma in said reaction chamber, and(d) heat treating said semiconductor substrate.

Abstract: A process for forming wiring over a migration preventing layer on a semiconductor substrate including forming a contact hole in a an insulation layer of the substrate and then filling the contact hole with an aluminum based alloy. A migration preventing layer is then formed, of a material which resists migration of atoms of the aluminum based alloy, over the surface of the aluminum based alloy. A wiring layer of aluminum is then formed over the migration preventing layer. In another embodiment, the contact hole may be provided with a first layer to prevent electron migration and a second layer which is a nitride of the first layer material.

Abstract: A method is described for overcoming the non-conformity and poor step coverage incurred when materials such as metals and barrier materials are deposited into contact or via openings by physical-vapor-deposition (PVD) techniques such as sputtering and evaporation. Conventional PVD deposition into a vertical walled opening results in the formations of cusps along the walls at the mouth of the opening. These cusps obstruct the material stream into the depth of the opening, resulting in inadequate coverage at the base of the opening particularly at the corners. This increases the chance of failure of the barrier material resulting in a reliability exposure. In addition, the cusps, if not removed, cause the formation of voids in subsequently deposited conductive plugs. The invention teaches the insulative layer, wherein the openings are formed, to be deposited to a greater thickness than required by the design. The openings are then formed and filled with a spin-on-glass.

Abstract: A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

Abstract: A method of forming a tapered via includes steps of forming a via, coating the walls and bottom of the via with a reflow material, removing the reflow material from the bottom the via and causing the reflow material to become non-solid. Surface tension and other liquid forces cause the reflow material to form a tapered shape (i.e., be thicker at the bottom than the top). Therefore, with the invention, there is more control over the reflow process.

Abstract: A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact hole includes a first insulating layer of a first thermal conductivity having a contact hole formed therein. A region of material of a second thermal conductivity formed in the first insulating layer adjacent the location of the contact hole. The second thermal conductivity is greater than the first thermal conductivity such that the thermal conductivity of the region of material is greater than the thermal conductivity of the insulating layer. A metal is formed in the hole which completely buries the contact hole.

Abstract: The present invention provides a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for one of the dielectric layers by annealing the polycide line and thereby increasing its hardness prior to the reflow process being conducted. The annealing process can be carried out either before or after the polycide line is formed at an annealing temperature in the range between about 700.degree. C. and about 1000.degree. C. in a furnace or by a rapid thermal process.

Abstract: A manufacturing method for semiconductor devices such as dynamic RAM, etc. which removes the layer part more on the high position than an arbitrary position on a step forming a gradation by just a prescribed thickness when flattening a layer with a gradation formed of a high position part and a low position part. Then the projecting part created after the etching existing more on the low position side than at the arbitrary position of the gradation is eliminated by heat treatment.

Abstract: An insulating film 16, made of BPSG, etc., is formed on a substrate 10 by CVD, covering an uneven surface, and then is subjected to thermal treatment to fluidize the film and to reduce the step. Hydrogen silsesquioxane resin solution is coated on the film 16 by spin coating, subjected to the first annealing at a relatively low temperature, and then to the second annealing at relatively high temperature, to form a glass film 18. The lamination of the films 16 and 18 is etched back under the dry etching conditions where the etch rates of the films 16 and 18 become approximately equal, until film 18 is completely removed, to planarize the film 16. A wiring is formed on the planarized surface. The surface of the insulating film serving as an underlying layer of a wiring can be planarized uniformly and with good reproducibility.

Abstract: A method of improving the planarization of inter-poly dielectric layers. On a semiconductor device on which a poly-silicon layer is formed, by using atmosphere chemical vapor deposition, an undoped inter-poly dielectric layer is formed. A doped inter-poly dielectric layer is formed on the undoped inter-poly dielectric layer. Under a high temperature, reflow and etching back operations are performed for the doped inter-poly dielectric layer. Before a second poly-silicon layer is formed, a rapid thermal process is performed.

Abstract: A method is described for filling narrow gaps in a surface that is being overcoated. This has been achieved by heating the overcoating layer to a sufficient extent so that it flows relatively easily. This, in combination with externally applied pressure, causes the overcoating layer to effectively fill any narrow gaps in the surface being coated. Temperature and pressure are applied for a time that is sufficient to allow small quantities of gas that may have become trapped in the gaps to bubble to the surface. In an alternative embodiment, the surface to be coated is subjected to negative pressure prior to application of the coating. This eliminates the possibility of trapping gas in the gaps so a waiting time is no longer necessary.

Abstract: A method of filling high aspect ratio vias and lines on the upper surface of a substrate prevents voids from being formed therein. The method comprises the steps of filling the lines and vias by surface diffusion at room temperature and at a pressure of 1 Torr. Step coverage of the fill material and sputtering parameters are chosen to satisfy a predetermined relationship. The upper surface of the substrate comprises regions of exposed aluminum, aluminum-copper or copper alloys. After filling the vias and lines, the exposed aluminum, aluminum-copper or copper alloys are reacted with a gas containing germanium to form a germanium alloy over the upper surface of the substrate.

Abstract: An improved and new method for forming stacked polysilicon contacts for use in multilevel conducting interconnection wiring in semiconductor integrated circuits has been developed. The polysilicon contacts are self-aligned between wiring levels and the fabrication process results in a substantially planar top insulating layer surface.

Abstract: An improved method for depositing a flow fill layer of an integrated circuit. Two flowlayers and two cap layers are deposited. The wafer is warmed between the deposition of the first cap layer and the deposition of the second flowlayer, to evaporate water from the first flowlayer. Preferably, each of the cap layers is deposited in two separate steps of plasma enhanced chemical vapor deposition, to inhibit crack formation in the flowlayers. Most preferably, after the depositions of each flowlayer, the flowlayer is planarized by flowing H.sub.2 O.sub.2 thereupon.