Abstract: A method for formation of a wiring layer in a semiconductor device, which includes the steps of: forming a first conductive layer upon a substrate; forming a second conductive layer on the first conductive layer, the second conductive layer having a melting point lower than that of the first conductive layer; and melting (or flowing) the second conductive layer. The first conductive layer is composed of aluminum or an aluminum alloy, and the impurity may be Si or Cu, while the second conductive layer has a melting point lower than that of the first conductive layer by 10.degree. C. or more.

Abstract: Voids in via holes in integrated circuits have been effectively removed by heating the vias to a relatively low temperature and then subjecting the entire structure (including the vias) to artificial gravitational forces. Said forces may be steadily applied, as in centrifuging, or they may be applied intermittently by using a jerking motion which is repeated several times. A number of different ways for implementing such jerking motion are described. These include magnetic repulsion, vertical pulling by a motor, and providing a pressure differential between the top and bottom sides of the integrated circuit holder.

Abstract: A wiring structure of semiconductor device and a method for manufacturing the same which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole or a via hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface thereof the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for the semiconductor device of the next generation.

Abstract: An method for the fabrication of an ohmic, low resistance contact to heavily doped silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for surface planarization using a borophosphosilicate glass insulator deposited on the silicon. After the glass is flowed to planarize its surface, contact holes are patterned in the glass and the exposed silicon substrate contacts are implanted. Instead of activating the implant with a rapid-thermal-anneal at this point the Ti/TiN barrier metallurgy is applied first followed by the anneal. This provides support for the glass at the upper corners of the contact opening during the anneal and thus prevents them from deforming and encroaching into the contact hole opening.

Abstract: A method of forming a BPSG dielectric layer on a wafer without delamination in the fabrication of an integrated circuit device wherein a BPSG deposition chamber is used is described. Semiconductor device structures are provided in and on a semiconductor substrate. The BPSG deposition chamber is cleaned according to the following steps. The deposition chamber is cleaned using a fluorine-containing gas. The fluorine-containing gas is pumped out of the deposition chamber wherein residual fluorine-containing gas remains within the deposition chamber. A plasma is flowed into the deposition chamber wherein the plasma consumes all of the residual fluorine-containing gas. The plasma is purged from the deposition chamber to complete the cleaning of the BPSG deposition chamber. Thereafter, a layer of BPSG is deposited over the semiconductor device structures wherein the BPSG layer is deposited while the wafer is within the BPSG deposition chamber.

Abstract: A contact hole burying method is provided including the steps of: coating an oxide layer on a substrate and removing the oxide layer except for a portion thereof to form a contact hole extending through the oxide layer in electrical contact with the oxide layer; sequentially forming a metal barrier layer and wet layer on the oxide layer and inside the contact hole to form an electrical connection to the substrate; forming a conductive metal layer on the wet layer; removing impurity ions and oxide material, which remain in the conductive metal layer which decrease mobility of metal atoms on a surface of said conductive layer due to absorption and oxidation, by a cleaning-etching process using a plasma; and reflowing the conductive metal layer at a relatively low temperature in a reactive furnace where the cleaning-etching process is performed to completely fill the contact hole.

Abstract: A method for increasing the oxide removal rate of oxide chemical-mechanical polishing is provided for planarizing dielectric layers. The method of the invention is employed in the process for forming multilayer interconnects. The process employs doped oxide deposition and polish processing instead of undoped oxide deposition and polish. Doped oxides such as BPTEOS (boron phosphorous tetra-ethyl orthosilicate), BSG (boron silane-based glass), PSG (phosphorous silane-based glass), and BPSG (boron phosphorous silane-based glass) can be used. The polish rate of doped oxide film is 2 to 3 times the polish rate of undoped oxide film. By forming the planarized dielectric layers from doped oxide films, the throughput of the CMP process step is increased thus reducing the cost of manufacturing.

Abstract: A method of smoothing irregularities in a surface of a semiconductor device using flowable particles which are dispersed onto the surface of the semiconductor device. The irregularities in the surface of the semiconductor device are filled with flowable particles smaller in size than the irregularities which are to be smoothed, and the particles are thereafter heated so that they flow and fill the irregularities, forming a smooth layer of flowable particle material which does not require polishing. The flowable particles may be mixed with non-flowable particles which are encapsulated in the layer of flowable particle material to form a homogeneous layer. The non-flowable particles may be augmentors which modify the properties of the layer. The particles may be dispersed with a spin-on process.

Abstract: An element including a polycide electrode is formed on a silicon substrate, and after a BPSG film is deposited as an interlevel insulating film and a contact hole is formed therein, the substrate is lamp annealed in an atmosphere containing oxygen to reflow the BPSG film. After an HF process, an Al wiring is formed on the BPSG film, contacting the polycide electrode via the contact hole. It is possible to prevent an increase in the contact resistance of the polycide electrode.

Abstract: An annealing method includes providing a wafer having a film stack including at least a flowable film and a semirigid film formed on the flowable film. The film stack is exposed to an initial temperature followed by exposure to an intermediate temperature for an intermediate exposure time period. Then, the film stack is exposed to a final anneal temperature for a final anneal exposure time period. The film stack may include another nonflowable or flowable film formed on the semirigid film. The film stack may be exposed to one or more additional intermediate temperatures for additional intermediate exposure time periods. The film stack may be an oxide/polysilicon/oxide film stack and the oxide films may be doped oxides. A device or wafer having a film stack annealed in accordance with the annealing method is also provided.

Abstract: This invention relates to a method for removing residual spin-on-glass (SOG) during a planarization processing step wherein the SOG is used as a sacrificial planarization medium and subjected to a full etchback to an underlying interlevel dielectric (ILD) layer. The SOG is applied over the ILD layer, and etched back into the ILD layer by reactive-ion-etching under conditions of comparable etch rates for both SOG and ILD. At endpoint there some residual pockets of SOG can be present as well as a region of SOG along the edges of the wafer where it is clamped in the etchback tool. The residual SOG must be removed completely to avoid SOG cracking after thermal processing and SOG outgassing during subsequent metal deposition. For this purpose an aqueous etch consisting of hydrofluoric acid buffered with ammonium fluoride is used.

Abstract: A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.

Abstract: A manufacturable method for forming a highly reliable electrical interconnection. An electrical interconnection pattern is first formed in a dielectric layer on a semiconductor substrate as recessed regions in the dielectric layer. Sidewalls containing a material which wets copper are then formed against the walls within the recessed regions. A conductive layer primarily comprising copper is thereafter deposited over the surface and in the recessed regions of the dielectric layer. The conductive layer is then reflowed to fill the recessed regions of the dielectric layer with substantially no void formation.

Abstract: A method for avoiding separation between a TEOS layer and the underlying dielectric layer is described, A first dielectric layer is deposited over semiconductor device structures in and on a semiconductor substrate and planarized. A conducting layer is deposited overlying the first dielectric layer and patterned thereby exposing portions of the first dielectric layer, The exposed portions of the first dielectric layer are treated with N.sub.2 plasma, A second dielectric layer is deposited overlying the patterned conducting layer and the exposed portions of the first dielectric layer, The treating of the exposed portions of the first dielectric layer with N.sub.

Abstract: A method of laser planarizing metallic thin films minimizes the laser fluences required to melt or nearly melt the metalization. This is accomplished by reducing the optical reflectivity of the metallic lines and vias by using textured thin films. This reduction of optical reflectivity, in turn, reduces the minimum fluence needed to melt or nearly melt the metal using a laser, thus improving the process window and minimizing the damage to the surrounding media.

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.