Abstract: In a method for forming a field effect transistor, a metal nitride layer is formed on a gate electrode insulating layer. Tantalum amine derivatives represented by the chemical formula Ta(NR1)(NR2R3)3, in which R1, R2 and R3 represent H or a C1-C6 alkyl group, may be used to form the metal nitride layer. Nitrogen may then be implanted into the metal nitride layer to increase the nitrogen content of the layer.

Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric. The lanthaide metal is contained in the screen layer or at the interface between the screen metal layer and the gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Abstract: Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods and apparatus for forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use of selective metal capping techniques and their attendant yield problems are avoided. Various cluster tool configurations including gas-cluster ion-beam processing modules for copper capping, cleaning, etching, and film formation steps are disclosed.

Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.

Abstract: The invention relates to a method and device for depositing at least one layer, particularly a semiconductor layer, onto at least one substrate, which is situated inside a process chamber of a reactor while being supported by a substrate holder. The layer is comprised of at least two material components provided in a fixed stoichiometric ratio, which are each introduced into the reactor in the form of a first and a second reaction gas, and a portion of the decomposition products form the layer, whereby the supply of the first reaction gas, which has a low thermal activation energy, determines the growth rate of the layer, and the second reaction gas, which has a high thermal activation energy, is supplied in excess and is preconditioned, in particular, by an independent supply of energy. The first reaction gas flows in a direction toward the substrate holder through a multitude of openings, which are distributed over a surface of a gas inlet element, said surface being located opposite the substrate holder.

Abstract: Transistors having a Hafnium-Silicon gate electrode and high-k dielectric are disclosed. A workpiece is provided having a gate dielectric formed over the workpiece, and a gate formed over the gate dielectric. The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

Abstract: A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.

Abstract: The present invention provides a method of forming a diffusion barrier layer comprising a TaSiN layer. The method includes depositing a TaN layer into a via hole which penetrates an insulation layer exposing a first metal line layer, and transforming the TaN layer into a TaSiN layer using a radio frequency (RF) power and a (remote) plasma using SiH4 gas. Transforming the TaN layer into a TaSiN layer may include: loading a structure including the TaN layer into a plasma reaction chamber; injecting SiH4 gas into the plasma reaction chamber; and forming the TaSiN layer by reacting Si— or Si atom-containing species with the TaN layer.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: A transparent conductive oxide (TCO) based film is formed on a substrate. The film may be formed by sputter-depositing, so as to include both a primary dopant (e.g., Al) and a co-dopant (e.g., Ag). The benefit of using the co-dopant in depositing the TCO inclusive film may be two-fold: (a) it may prevent or reduce self-compensation of the primary dopant by a more proper positioning of the Fermi level, and/or (b) it may promote declustering of the primary dopant, thereby freeing up space in the metal sublattice and permitting more primary dopant to create electrically active centers so as to improve conductivity of the film. Accordingly, the use of the co-dopant permits the primary dopant to be more effective in enhancing conductivity of the TCO inclusive film, without significantly sacrificing visible transmission characteristics. An example TCO in certain embodiments is ZnAlOx:Ag.

Abstract: A method for forming electrode materials uniformly and conformally within openings having small dimensions, including sublithographic dimensions, or high aspect ratios. The method includes the steps of providing an insulator layer having an opening formed therein, and forming a conformal conductive or semiresistive material over and within the opening. The method is a CVD or ALD process for forming metal nitride, metal aluminum nitride, and metal silicon nitride electrode compositions. The methods utilize metal precursors containing one or more ligands selected from alkyl, allyl, alkene, alkyne, acyl, amide, amine, immine, imide, azide, hydrazine, silyl, alkylsilyl, silylamine, chelating, hydride, cyclic, carbocyclic, cyclopentadienyl, phosphine, carbonyl, or halide. Suitable precursors include monometallic precursors having the general formula MRn, where M is a metal, R designates a ligand as indicated above and n is an integer corresponding to the number of ligands bonded to the central metal atom.

Abstract: The method includes providing a patterned structure in a process chamber, where the patterned structure contains a micro-feature formed in a dielectric material and a contact layer at the bottom of the micro-feature, and depositing a metal carbonitride or metal carbide film on the patterned structure, including in the micro-feature and on the contact layer. The method further includes forming an oxidation-resistant diffusion barrier by increasing the nitrogen-content of the deposited metal carbonitride or metal carbide film, depositing a Ru film on the oxidation-resistant diffusion barrier, and forming bulk Cu metal in the micro-feature. A semiconductor contact structure is described.

Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.

Abstract: A method for manufacturing a micromechanical component and a micromechanical component manufactured using this method are described, the micromechanical component having a first substrate, which in turn has at least one cavity and one printed conductor. At least a part of the printed conductor is applied to at least a part of the walls of the cavity. In particular, the floor of the cavity is considered part of the cavity walls.

Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.

Abstract: A semiconductor wafer processing method for planarizing an additional layer formed on the front side of a semiconductor wafer. First, the wafer is held on a chuck table included in a cutting device in the condition where the additional layer is exposed, and a table base supporting the chuck table is moved toward a working position. In concert with the movement of the table base, the exposed surface of the additional layer is cut by a bit of a cutting tool rotationally driven by a spindle motor. Thereafter, the exposed surface of the additional layer is polished by a polishing device to planarize the exposed surface of the additional layer.

Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon implanted layer, a tungsten nitride layer on the silicon implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.

Abstract: A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible.

Abstract: The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).

Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.

Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.

Abstract: A first gate electrode and a second gate electrode are formed on a semiconductor substrate, and then a resist pattern is formed so as to selectively leave open a portion including an overlap between the first and second gate electrodes. Next, the overlap between the gate electrodes is removed through isotropic etching. Etching is carried out at this time by an amount within a range of 140% to 200% of the film thickness of the second gate electrode. Next, a normal inter-layer insulating film and light-shielding film are formed. It is possible to eliminate the overlap between the gate electrodes adjacent to an opening of the light-shielding film, suppress the height of the light-shielding film at that portion, reduce shading for the light condensed by a lens and thereby improve the light condensing efficiency of the lens.

Abstract: Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting ions into opposite sides of the gate pattern, to form a lightly doped drain structure while implanting ions into a portion of the high-voltage device region under the same conditions as the low-voltage device region to form an electrostatic discharge protecting device region; forming a spacer at the side surface of the gate pattern; forming a source region and a drain source at field regions disposed at the opposite sides of the gate pattern, respectively; and forming a metal layer on the front surface of the substrate including the gate pattern.

Abstract: The embodiments provides an improved tungsten silicide etching process with reduced etch rate micro-loading effect. In one embodiment, a method for etching a layer formed on a substrate is provided. The method includes providing a substrate into a plasma processing chamber, the substrate having a metal silicide layer formed thereon and a patterned mask defined over the metal silicide layer. The method also includes supplying an etching gas mixture of a fluorine-containing gas, a chlorine-containing gas, a nitrogen-containing gas, and an oxygen-containing gas to the plasma processing chamber, wherein the ratio of the nitrogen-containing gas to the fluorine-containing gas is between about 5 to about 15.

Abstract: A semiconductor device manufacturing method capable of preventing an infliction of damage upon an interlayer insulating film and moisture adsorption thereto due to opening to atmosphere in a process of forming a CuSiN barrier by infiltrating Si into a surface of a copper-containing metal film and nitrifying a Si-infiltrated portion is disclosed. When a semiconductor device is manufactured through the processes of preparing a semiconductor substrate having a copper-containing metal film exposed on a surface thereof; purifying a surface of the copper-containing metal film by using radicals or by using a thermo-chemical method; infiltrating Si into the surface of the copper-containing metal film; and nitrifying a Si-infiltrated portion of the copper-containing metal film by radicals, the purification process, the Si introduction process and the nitrification process are successively performed without breaking a vacuum.

Abstract: A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes forming a photoresist pattern for ion implantation, implanting ions into the aluminum layer, and annealing by using a rapid thermal process.

Abstract: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams.

Abstract: A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.

Abstract: A method for manufacturing a CMOS image sensor is provided. A metal line can be formed over a semiconductor substrate including a transistor structure. Dangling bonding on the surface of the semiconductor substrate can be removed after forming the metal line by injecting a preset amount of hydrogen (H) atoms on the surface of the semiconductor substrate. Then, a thermal treatment can be performed on the resulting structure.

Abstract: Embodiments relate to a metal wiring in a semiconductor device that may be formed by depositing a metal layer on a semiconductor substrate, and performing ion bombardment on a surface of the metal layer to thereby forming the metal wiring. According to embodiments, the metal layer may be etched and ion bombardment may then be performed on the surface of the metal wiring to form the metal wiring.

Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.

Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.

Abstract: A method for forming a silicide layer on a silicon surface is provided. First, inert gas ions are implanted into the silicon surface. Then, a metal layer is formed on the surface and subsequently converted into the suicide layer. Thereby the resistance of the silicide can be reduced and the uniformity can be raised without substantially altering the doping concentration of conductive component(s). Thus, the efficiency of the semiconductor device can be enhanced.

Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.

Abstract: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Abstract: A method is provided for producing a solid-state imaging device in which a plurality of pixels are arranged two-dimensionally so as to form a photosensitive region, each of the pixels including a photodiode that photoelectrically converts incident light to store a signal charge and read-out elements for reading out the signal charge from the photodiode, and a vertical driving circuit for driving the plurality of pixels in the photosensitive region in a row direction, a horizontal driving circuit for driving the same in a column direction and an amplify circuit for amplifying an output signal are formed with MOS transistors. The method includes: forming an element isolation region with a STI (Shallow Trench Isolation) structure between the plurality of photodiodes and the plurality of MOS transistors; and forming a gate oxide film of the MOS transistors to have a thickness of 10 nm or less.

Abstract: A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.

Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

Abstract: For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film successively over a gate insulating film disposed over the main surface of a semiconductor substrate, and patterning them to form a gate electrode having a stacked structure consisting of the polycrystalline silicon film and tungsten silicide film. The polycrystalline silicon film has two regions, one region formed by an impurity-doped polycrystalline silicon and the other one formed by non-doped polycrystalline silicon. The tungsten silicide film is deposited so that the resistivity of it upon film formation would exceed 1000 ??cm.

Abstract: Methods of forming CMOS devices and structures thereof. A workpiece is provided having a first region and a second region. A high k gate dielectric material is formed over the workpiece. A first gate material comprising a first metal is formed over the high k gate dielectric material. The first gate material in the second region is implanted with a material different than the first metal to form a second gate material comprising a second metal. The work function of the CMOS device is set by the material selection of the gate materials.

Abstract: A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

Abstract: The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffusion layer. The silicide film is thicker on the gate electrode than on the source-drain diffusion layer. The manufacturing method comprises forming a gate electrode on a gate insulating film, followed by forming a source-drain diffusion layer. Then, atoms inhibiting a silicidation are selectively introduced into the source-drain diffusion layer, and a high melting point metal film is formed on the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into silicide films selectively on the gate electrode and the source-drain diffusion layer.

Abstract: The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one illustrative embodiment, the method comprises forming a metal seed layer above a patterned layer of insulating material, the patterned layer of insulating material defining a plurality of field areas, deactivating at least a portion of the metal seed layer in areas where the metal seed layer is positioned above at least some of the field areas, and performing a deposition process to deposit a metal layer above the metal seed layer. In some embodiments, the metal may be comprised of copper, platinum, nickel, tantalum, tungsten, cobalt, etc. Portions of the metal seed layer may be deactivated by implanting ions into portions of the metal seed layer positioned above at least some of the field areas. The implanted ions may be comprised of nitrogen, carbon, silicon, hydrogen, etc.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

Abstract: A semiconductor device having a gate electrode free from increasing of resistance of the gate electrode, from decreasing of capacitance of the insulation film due to depletion, and from penetrating of impurity. The semiconductor device includes a silicon layer, a gate insulating film formed on the silicon layer, a metal boron compound layer formed on the gate insulating film, and a gate electrode formed on the metal boron compound layer and containing at least silicon.

Abstract: A method and structure to reduce electromigration failure of semiconductor interconnects. In various embodiments, the area around a via is selectively doped with metallic dopants. The method and resulting structure reduce electromigration failure without adding unnecessary, performance-degrading resistance.

Abstract: A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and ion implanting elements into the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.