Abstract: A TAMR (Thermally Assisted Magnetic Recording) write head is formed with a narrow pole tip, a trailing edge magnetic shield and, optionally, a plasmon shield. The narrow pole tipped write head uses the energy of laser generated edge plasmons, formed in a plasmon generating layer, to locally heat a PMR magnetic recording medium slightly below its Curie temperature, Tc. When combined with the effects of the narrow tip, this local heating to a temperature below Tc is sufficient to create good transitions and narrow track widths in the magnetic medium. The write head is capable of writing effectively on state-of-the-art PMR recording media having Hk of 20 kOe or more.

Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.

Abstract: Methods for etching an etching stop layer disposed on the substrate using a cyclical etching process are provided. In one embodiment, a method for etching an etching stop layer includes performing a treatment process on the substrate having a silicon nitride layer disposed thereon by supplying a treatment gas mixture into the processing chamber to treat the silicon nitride layer, and performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process etches the treated silicon nitride layer.

Abstract: A method for patterning a substrate is described. The patterning method may include conformally depositing a material layer over a pattern according to a conformal deposition process, selectively depositing a second material layer on an exposed surface of the material layer according to a selected deposition process recipe; partially removing the material layer using a plasma etching process to expose a top surface of the pattern, open a portion of the material layer at a bottom region between adjacent features of the pattern, and retain a remaining portion of the material layer on sidewalls of the pattern; and removing the pattern using one or more etching processes to leave a final pattern comprising the remaining portion of the material layer and the second layer.

Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate comprising silicon in a processing chamber, delivering a plasma to the surface of the substrate while biasing the substrate, exposing the surface of the substrate to ammonium fluoride (NH4F), and annealing the substrate to a first temperature to sublimate one or more volatile byproducts.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes dry-etching a member containing silicon in a first pressure range equal to or more than a first pressure or in a second pressure range equal to or less than a second pressure, wherein the first pressure is obtained by multiplying a saturated pressure by 0.85, the saturated pressure is defined as a pressure under which an etching rate is one of a maximum value or a value obtained by multiplying the maximum value by a predetermined coefficient, and the etching rate is a half value of the maximum value under the second pressure.

Abstract: Provided is a method of etching a silicon oxide film, which includes supplying a mixture gas of a halogen element-containing gas and a basicity gas onto a surface of the silicon oxide film; modifying the silicon oxide film to produce a reaction product; and heating the reaction product to remove the reaction product. Modifying the silicon oxide film and heating the reaction product are performed using one chamber. In heating the reaction product, the reaction product is selectively heated by a heating unit.

Abstract: A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.

Abstract: There is provided a plasma etching method including a first process of etching an intermediate layer, which contains silicon and nitrogen and is positioned below a resist mask formed on a surface of a substrate, to cause a silicon layer positioned below the intermediate layer to be exposed through the resist mask and the intermediate layer, a second process of subsequently supplying a chlorine gas to the substrate to cause a reaction product to attach onto sidewalls of opening portions of the resist mask and the intermediate layer, and a third process of etching a portion of the silicon layer corresponding to the opening portion of the intermediate layer using a process gas containing sulfur and fluorine to form a recess in the silicon layer.

Abstract: Various embodiments provide double patterning methods and structures. In an exemplary method, a to-be-etched layer can be provided. A stress layer can be formed on the to-be-etched layer. The stress layer can have a tensile stress. A plurality of discrete sacrificial layers can be formed on the stress layer. A sidewall-spacer material layer covering the plurality of sacrificial layers and the stress layer can be formed. The sidewall-spacer material layer can be etched to form a sidewall spacer on a sidewall of each sacrificial layer of the plurality of sacrificial layers. The stress layer at each side of the each sacrificial layer can be etched to form a groove passing through a thickness of the stress layer. The plurality of sacrificial layers can be removed.

Abstract: A method of producing an optoelectronic component comprises the steps of: A) providing a radiation-emitting layer sequence (1) having an active zone (13), which emits electromagnetic primary radiation when in operation, B) providing a first wavelength conversion layer (2), which converts the primary radiation at least partially into electromagnetic secondary radiation, and C) arranging the first wavelength conversion layer (2) on the radiation-emitting layer sequence (1) in the beam path of the primary radiation.

Abstract: A method is provided for manufacturing a semiconductor device having a heat-resistant resin film with flip-chip connection structure using a solder bump or a gold bump and an epoxy resin compound laminated thereon, in which adhesiveness is improved particularly after exposure to high temperature and high humidity environments for a long period of time, thereby enhancing the reliability of the semiconductor device. The method, in accordance with the present invention, for manufacturing a semiconductor device having a heat-resistant resin film formed on a semiconductor element and an epoxy resin compound layer laminated thereon, comprises the steps of carrying out a plasma treatment on a surface of the heat-resistant resin film on which the epoxy resin compound layer is laminated using a nitrogen atom-containing gas containing at least one of nitrogen, ammonia, and hydrazine.

Abstract: Methods for etching a substrate are provided herein. In some embodiments, a method of etching a substrate may include generating a plasma by providing only a first RF signal having a first frequency and a first duty cycle; applying only a second RF signal to bias the plasma towards the substrate, wherein the second RF signal has the first frequency and a second duty cycle different than the first duty cycle; adjusting a phase variance between the first and second RF signals to control an ion energy distribution in the plasma; and etching the substrate with the plasma.

Abstract: A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: A flip-chip light emitting diode comprises a transparent base-plate, at least a first electrical semi-conductive layer, a light emitting layer, a second electrical semi-conductive layer, at least a first ohmic contact, a second ohmic contact and a third ohmic contact are installed above the transparent base-plate. The at least first ohmic contact is electrically connected to the third ohmic contact through a connection passage. A first electrode area is formed above the second electrical semi-conductive layer. The second ohmic contact is disposed above the transparent base-plate and adjacent to a side of the first ohmic contact. A second electrode area is formed on the second ohmic contact.

Abstract: A surface wave plasma (SWP) source couples pulsed microwave (MW) energy into a processing chamber through, for example, a radial line slot antenna, to result in a low mean electron energy (Te). To prevent impingement of the microwave energy onto the surface of a substrate when plasma density is low between pulses, an ICP source, such as a helical inductive source, a planar RF coil, or other inductively coupled source, is provided between the SWP source and the substrate to produce plasma that is opaque to microwave energy. The ICP source can also be pulsed in synchronism with the pulsing of the MW plasma in phase with the ramping up of the MW pulses. The ICP also adds an edge dense distribution of plasma to a generally chamber centric MW plasma to improve plasma uniformity.

Abstract: A method of forming an electrode is disclosed. A carbon nanotube is deposited on a substrate. A section of the carbon nanotube is removed to form at least one exposed end defining a first gap. A metal is deposited at the at least one exposed end to form the electrode that defines a second gap.

Abstract: A method for cleaning a processing chamber, for example, a strip chamber, configured for processing a wafer is provided which includes the steps of introducing an oxygen-containing gas into the processing chamber, generating an oxygen plasma from the oxygen-containing gas in the processing chamber, establishing a pressure of the oxygen plasma in the processing chamber of at least 1 Torr and maintaining the pressure of at least 1 Torr for at least 40 seconds. A system is also provided including a strip chamber for receiving and stripping the wafer and including a gas inlet and plasma generator means, as well as a controller configured for performing, when no wafer is present in the strip chamber, controlling inflow of an oxygen-containing gas into the processing chamber through the gas inlet and controlling the plasma generator means to generate an oxygen plasma.

Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.

Abstract: The present invention discloses a method for preparing switch transistor comprising: sequentially forming a control electrode, an insulation layer, an active layer, and a source/drain metal layer of the switch transistor on a glass substrate; patterning the source/drain metal layer to expose the active layer; and proceeding an etching process to the exposed active layer in a way of gradually reducing etching rate to form a channel of the switch transistor. The present invention further discloses an equipment for etching the switch transistor. In the way mentioned above, the present invention can minimize the damages to the switch transistor and improve the reliability of the switch transistor.

Abstract: A method for etching features into an etch layer in a stack disposed below a patterned mask with mask features is provided. Coating providing molecules are provided. The coating providing molecules are pyrolyzed, which only produces a first set of byproducts and a second set of byproducts, wherein the first set of byproducts have a sticking coefficient between 10?6 to 5×10?3 and wherein the second set of byproducts includes all remaining byproducts from the pyrolysis wherein all remaining byproducts from the pyrolysis have sticking coefficients less than 10?6. The stack is exposed to the first set of byproducts, causing the first set of byproducts to deposit a coating. The etch layer is etched.

Abstract: Methods of forming contact holes include forming a first guide pattern over an etching target layer. The first guide pattern has first openings each extending in a first direction and each first opening arranged in a direction perpendicular to the first direction. A first BCP structure is formed in each first opening. The first BCP structure includes first material layers in the first direction at a first pitch in each of the first openings, and second material layers filling a remaining portion of each first opening. First holes are formed by removing the first material layers. A second guide pattern is formed over the first guide pattern and the second material layers, and the above processes are performed on the second guide pattern to form second holes. Portions of the etching target layer overlapped by the first holes or the second holes are removed to form a desired pattern.

Abstract: A method for selective etching of an SiGe mixed semiconductor layer on a silicon semiconductor substrate by dry chemical etching of the SiGe mixed semiconductor layer with the aid of an etching gas selected from the group including ClF3 and/or ClF5, a gas selected from the group including Cl2 and/or HCl being added to the etching gas.

Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process.

Abstract: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: A method of fabricating a semiconductor device is disclosed. A substrate having an oxide layer is provided. At least a portion of the oxide layer is removed and forms a nitride layer. The nitride layer is removed, leaving nitride precipitates. The nitride precipitates are removed using phosphoric acid.

Abstract: Techniques for forming a three dimensional (3D) feature on a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method comprising: forming a resist structure on the substrate, the resist structure having a first resist portion with a first thickness, a second resist portion with a second thickness, and a third resist portion with a third thickness, where the first thickness may be less than the second thickness, and where the second thickness may be less than the third thickness; implanting charged particles into the substrate through the first and second resist portions and forming an implanted region in the substrate; and etching the substrate to form the 3D feature on the substrate.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: The molecular etcher carbonyl fluoride (COF2) or any of its variants, are provided for, according to the present invention, to increase the efficiency of etching and/or cleaning and/or removal of materials such as the unwanted film and/or deposits on the chamber walls and other components in a process chamber or substrate (collectively referred to herein as “materials”). The methods of the present invention involve igniting and sustaining a plasma, whether it is a remote or in-situ plasma, by stepwise addition of additives, such as but not limited to, a saturated, unsaturated or partially unsaturated perfluorocarbon compound (PFC) having the general formula (CyFz) and/or an oxide of carbon (COx) to a nitrogen trifluoride (NF3) plasma into a chemical deposition chamber (CVD) chamber, thereby generating COF2. The NF3 may be excited in a plasma inside the CVD chamber or in a remote plasma region upstream from the CVD chamber.

Abstract: Etching of a thin film stack including a lower thin film layer containing an advanced memory material is carried out in an inductively coupled plasma reactor having a dielectric RF window without exposing the lower thin film layer, and then the etch process is completed in a toroidal source plasma reactor.

Abstract: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.

Abstract: Methods of etching a silicon substrate at a high rate using a chemical vapor etching process are provided. A silicon substrate may be etched by heating the silicon substrate in a process chamber and then flowing hydrochloric acid and a germanium-carrying compound into the process chamber. The substrate may be heated to at least 700° C. The hydrochloric acid flow rate may be at least approximately 100 (standard cubic centimeters per minute) sccm. In some embodiments, the hydrochloric acid flow rate may be between approximately 10 slm and approximately 20 standard liters per minute (slm). The germanium-carrying compound flow rate may be at least approximately 50 sccm. In some embodiments, the germanium-carrying compound flow rate may be between approximately 100 sccm and approximately 500 sccm. The etching may extend fully through the silicon substrate.

Abstract: Hydrogen concentration and oxygen vacancies in an oxide semiconductor film are reduced. Reliability of a semiconductor device which includes a transistor using an oxide semiconductor film is improved. One embodiment of the present invention is a semiconductor device which includes a base insulating film; an oxide semiconductor film formed over the base insulating film; a gate insulating film formed over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film provided therebetween. The base insulating film shows a signal at a g value of 2.01 by electron spin resonance. The oxide semiconductor film does not show a signal at a g value of 1.93 by electron spin resonance.

Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.

Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.

Abstract: Provided is a method of selectively etching a portion of silicon existing on a surface of a substrate to be processed, which includes: loading the substrate to be processed into a chamber; and supplying an FNO gas and an F2 gas that are diluted with an inert gas into the chamber such that the FNO gas and the F2 gas are reacted with the portion of silicon existing on the surface of the substrate to be processed.

Abstract: A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by depositing and patterning a dielectric material on the substrate, and the conductive path is provided by a conductive layer deposited on the bump stop. The conductive layer can also be roughened to reduce stiction.

Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

Abstract: Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.

Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.

Abstract: A method of selectively removing fluorocarbon layers from overlying low-k dielectric material is described. These protective plasma treatments (PPT) are delicate alternatives to traditional post-etch treatments (PET). The method includes sequential exposure to (1) a local plasma formed from a silicon-fluorine precursor followed by (2) an exposure to plasma effluents formed in a remote plasma from a fluorine-containing precursor. The remote plasma etch (2) has been found to be highly selective of the residual material following the local plasma silicon-fluorine exposure. The sequential process (1)-(2) avoids exposing the low-k dielectric material to oxygen which would undesirably increase its dielectric constant.

Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

Abstract: A system and method for etching a material, including a compound having a formulation of XYZ, wherein X and Y are one or more metals and Z is selected from one or more Group 13-16 elements, such as carbon, nitrogen, boron, silicon, sulfur, selenium, and tellurium, are disclosed. The method includes a first etch process to form one or more first volatile compounds and a metal-depleted layer and a second etch process to remove at least a portion of the metal-depleted layer.

Abstract: An aspect of the invention is to provide a method and apparatus for etching the silicon oxide layer of a semiconductor substrate, whereby the processing time for cleaning or rinsing, as well as any undesired aftereffects by residual hydrofluoric acid, may be reduced, in using the dry etching method involving the use of dense carbon dioxide that contains hydrofluoric acid, during the manufacturing process of a micro-electronic device.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate; and a plurality of convex structures formed on a surface of the substrate and arranged in a longitudinal direction of the substrate, each convex structure having a top surface, a bottom surface located on the surface of the substrate, a first end surface and a second end surface parallel to each other, and a front side surface and a rear side surface parallel to each other, in which the rear side surface of one of two adjacent convex structures and the front side surface of the other are located on a same plane to allow the plurality of convex structures to form a zigzag structure.

Abstract: A method of making a Si containing gas distribution member for a semiconductor plasma processing chamber comprises forming a carbon member into an internal cavity structure of the Si containing gas distribution member. The method includes depositing Si containing material on the formed carbon member such that the Si containing material forms a shell around the formed carbon member. The Si containing shell is machined into the structure of the Si containing gas distribution member wherein the machining forms gas inlet and outlet holes exposing a portion of the formed carbon member in an interior region of the Si containing gas distribution member.

Abstract: The invention provide apparatus and methods for creating gate structures on a substrate in real-time using Vacuum Ultra-Violet (VUV) data and Electron Energy Distribution Function (EEDƒ) data and associated (VUV/EEDƒ)-related procedures in (VUV/EEDƒ) etch systems. The (VUV/EEDƒ)-related procedures can include multi-layer-multi-step processing sequences and (VUV/EEDƒ)-related models that can include Multi-Input/Multi-Output (MIMO) models.

Abstract: A method of manufacturing a transistor includes: forming an oxide semiconductor film and a gate electrode on a substrate, the oxide semiconductor film having a channel region, and the gate electrode facing the channel region; and forming an insulating film covering the gate electrode and the oxide semiconductor film. Infiltration of moisture from the insulating film into the oxide semiconductor film is suppressed by the substrate.

Abstract: An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.