Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: Methods are provided for removing an oxide layer from a metal pad on an integrated circuit in order to reduce contact resistance. In one embodiment, aluminum oxide, on the surface of a bond pad substantially comprised of aluminum, is reacted with a first chemical agent to form an inorganic salt, and the inorganic salt is then reacted with a second chemical agent leaving a substantially bare, that is, unoxidized, aluminum surface.

Abstract: A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.

Abstract: A method for manufacturing a semiconductor device by etching a SiN film on a surface of a substrate by using a gas containing a halogen element includes supplying a gas containing a basic gas at the initial stage of a process for supplying the gas containing the halogen element to the surface of the SiN film. By supplying the gas containing the basic gas at the initial stage of the etching, a SiNO film covering the surface of the SiN film is changed to a film of reaction products mainly including water (H2O) and ammonium hexafluorosilicate ((NH4)2SiF6).

Abstract: An object is to provide a semiconductor device which achieves miniaturization as well as suppressing a defect. Further, another object is to provide a semiconductor device which achieves miniaturization as well as keeping favorable characteristics. Is provided a semiconductor device including: a source wiring and a drain wiring each of which include a first conductive layer and a second conductive layer having a smaller thickness than the first conductive layer; an insulating layer which has an opening portion and is provided over the source wiring and the drain wiring; an oxide semiconductor layer which is in contact with part of the second conductive layer of the source wiring or the drain wiring in the opening portion; a gate insulating layer provided over the oxide semiconductor layer; and a gate electrode provided over the gate insulating layer.

Abstract: A method for producing a component, and a component, in particular a micromechanical and/or microfluidic and/or microelectronic component, is provided, the component including at least one patterned material region, and in a first step the patterned material region is produced in that microparticles of a first material are embedded in a matrix of a second material, and in a second step the patterned material region is rendered porous by etching using a dry etching method or a gas-phase etching method.

Abstract: A method of removing a high molecular weight organic-comprising hard mask or BARC from a surface of a porous low k dielectric material, where a change in the dielectric constant of the low k dielectric material is less than about 5% after application of the method. The method comprises exposing the organic-comprising hard mask or BARC to nitric acid vapor which contains at least 68% by mass HNO3.

Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.

Abstract: An ashing device and ashing method that can positively remove resist from a wafer while preventing degradation of the film material properties of exposed porous Low-K film on the wafer. The ashing device of the present invention introduces a gas to a dielectric plasma generating chamber 14, excites said gas to generate a plasma, and performs plasma processing using said gas plasma on a processing work S in use of a Low-K film. The ashing gas introduced from a gas regulator 20 is an inert gas to which H2 has been added. The configuration is formed so that plasma is generated from the gas blend, and the resist is removed by the hydrogen radicals generated.

Abstract: Provided are a method of forming a through hole, which can inhibit misalignment between central axes of holes in both surfaces of a substrate, which is free from metal contamination, and which inhibits notching so as to improve the dimensional accuracy, the method including: preparing a silicon substrate; preparing a supporting substrate for supporting the silicon substrate; fixing the silicon substrate and the supporting substrate to form a composite substrate; and carrying out dry etching to the composite substrate from a silicon substrate side of the composite substrate toward a supporting substrate side of the composite substrate to form a through hole in the silicon substrate, in which the supporting substrate in the preparing a supporting substrate has a hole formed at a region corresponding to a region of the through hole to be formed in the silicon substrate, on a surface of the supporting substrate facing the silicon substrate.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: Disclosed is a method for removing an oxide film formed on a surface of a silicon wafer, comprising steps of: preparing a silicon wafer having an oxide film formed thereon; arranging a discoid wafer mounting stage, which has a contact portion with the oxide film being formed of an acid-resistant resin layer, in a reaction container of a vapor-phase etching apparatus; mounting the silicon wafer on the mounting stage in such a manner that a wafer center coincides with a central axis of the mounting stage; and circulating a hydrogen fluoride containing gas into the reaction container and removing the oxide film from an interface between a chamfered surface and a wafer lower surface toward the inner side of the wafer until a desired interval a is obtained, wherein the desired interval a is adjusted by changing a stage diameter of the mounting stage.

Abstract: An optical waveguide arrangement is provided which comprises an active ridge waveguide structure 12 formed by etching of a semiconductor substrate 1, 2, 3. There is also provided an auxiliary waveguide-like structure 8 formed on the substrate adjacent the active ridge waveguide structure 12 to control the etched profile of the active waveguide structure. The arrangement of the auxiliary structure 8 on the substrate controls the etched profile over the cross-section of the active waveguide structure 12 and along the length of the active waveguide structure 12. Advantageously, this arrangement reduces or eliminates the disadvantages associated with etch-process induced asymmetries in the shape of closely spaced waveguides.

Abstract: A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A plasma is formed from the provided etch gas. A tungsten containing layer patterned with wide and narrow features is etched with the provided plasma.

Abstract: The present invention relates to a plasma etching method in which a special area for detecting an end point needs not to be set and an equipment therefor. At an etching step of forming SF6 gas into plasma to etch an etching ground on a Si film, the step is configured by two steps of: a large-amount supply step of supplying a large amount of SF6 gas; and a small-amount supply step of supplying a small amount of SF6 gas. An end-point detecting processor 34 measures an emission intensity of Si or SiFx in the plasma at the small-amount supply step, and determines that an etching end point is reached when the measured emission intensity becomes equal to or less than a previously set reference value.

Abstract: A process is provided for etching a mask layer and removal of residue from a structure having an area sheltered from directional etching. The structure has a shape that forms a silhouette area obstructed from being etched by anisotropic bombardment originating from a first direction, and a mask formed over the mask layer over the structure; A first etch process removes at least a part of the mask layer and retains at least a part of mask layer in the sheltered area. A second etch process removes at least a part of the mask layer in the sheltered area by hydrogen based microwave plasma etching.

Abstract: The present invention generally relates to methods for producing MEMS or NEMS devices and the devices themselves. A thin layer of a material having a lower recombination coefficient as compared to the cantilever structure may be deposited over the cantilever structure, the RF electrode and the pull-off electrode. The thin layer permits the etching gas introduced to the cavity to decrease the overall etchant recombination rate within the cavity and thus, increase the etching rate of the sacrificial material within the cavity. The etchant itself may be introduced through an opening in the encapsulating layer that is linearly aligned with the anchor portion of the cantilever structure so that the topmost layer of sacrificial material is etched first. Thereafter, sealing material may seal the cavity and extend into the cavity all the way to the anchor portion to provide additional strength to the anchor portion.

Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.

Abstract: Disclosed herein is a nanowire including silicon rich oxide and a method for producing the same. The nanowire exhibits excellent electrically conducting properties and optical characteristics, and therefore is effectively used in a variety of applications including, for example, solar cells, sensors, photodetectors, light emitting diodes, laser diodes, EL devices, PL devices, CL devices, FETs, CTFs, surface plasmon waveguides, MOS capacitors and the like.

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics.

Abstract: According to an embodiment, a method for etching polycrystalline silicon includes a step of holding the polycrystalline silicon at a temperature higher than or equal to TE (K) given in a following equation; and a step of etching the polycrystalline silicon by dry etching with an etching gas containing CF4 and O2, T E = - 0.114 ? x + 0.0556 k × ln ? { ( 1 - r / d ) × - 6.27 ? x + 5.38 - 2.01 ? x + 3.11 } where d (nm) is etching amount of the polycrystalline silicon, r (nm) is surface roughness of the polycrystalline silicon after the etching, x is ratio of flow rate of CF4 gas to sum of flow rate of the CF4 gas and flow rate of O2 gas, and k (eV/K) is Boltzmann constant.

Abstract: A surface cleaning apparatus comprising a chamber, and a thermal transfer device. The chamber is capable of holding a semiconductor structure therein. The thermal transfer device is connected to the chamber. The thermal transfer device has a surface disposed inside the chamber for contacting the semiconducting structure and controlling a temperature of the semiconductor structure in contact with the surface. The thermal transfer device has a thermal control module connected to the surface for heating and cooling the surface to thermally cycle the surface. The thermal control module effects a substantially immediate thermal response of the surface when thermally recycling the surface.

Abstract: The present invention provides a silicon-containing surface modifier wherein the modifier contains one or more of a repeating unit shown by the following general formula (A) and a partial structure shown by the following general formula (C).The present invention has an object to provide a resist underlayer film applicable not only to a negatively developed resist pattern formed by a hydrophilic organic compound but also to a conventional positively developed resist pattern formed by a hydrophobic compound.

Abstract: An ion source that utilizes exited and/or atomic gas injection is disclosed. In an ion beam application, the source gas can be used directly, as it is traditionally supplied. Alternatively or additionally, the source gas can be altered by passing it through a remote plasma source prior to being introduced to the ion source chamber. This can be used to create excited neutrals, heavy ions, metastable molecules or multiply charged ions. In another embodiment, multiple gasses are used, where one or more of the gasses are passed through a remote plasma generator. In certain embodiments, the gasses are combined in a single plasma generator before being supplied to the ion source chamber. In plasma immersion applications, plasma is injected into the process chamber through one or more additional gas injection locations. These injection locations allow the influx of additional plasma, produced by remote plasma sources external to the process chamber.

Abstract: The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures.

Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.

Abstract: The invention provides a method for subjecting laminated thin films disposed below a photoresist mask pattern to plasma processing, wherein the roughness on the side walls of the formed pattern is reduced, and the LER and LWR are reduced. When etching a material to be processed to form a gate electrode including thin films such as a gate insulating film 205, a conducting layer 204, a mask layer 203 and an antireflection film 202 laminated on a semiconductor substrate 206 and a photoresist mask pattern 201 disposed on the antireflection film, prior to etching the mask pattern 201, plasma is generated from nitrogen gas or a mixed gas including nitrogen gas and deposition gas to subject the mask pattern 201 to a plasma curing process so as to reduce the roughness on the surface and side walls of the mask pattern 201, and then the laminated thin films 202, 203 and 204 disposed below the mask pattern 201 are subjected to a plasma etching process.

Abstract: Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 ? per minute to about 20 ? per minute during the etching process.

Abstract: A dry etching method for texturing a surface of a substrate is disclosed. The method includes performing a first dry etching onto the surface of the substrate thereby forming a surface texture with spikes and valleys, the first dry etching comprising etching the surface of the substrate in a plasma comprising fluorine (F) radicals and oxygen (O) radicals, wherein the plasma comprises an excess of oxygen (O) radicals. The method may further include performing a second dry etching onto the surface texture thereby smoothening the surface texture, the second dry etching comprising chemical isotropic etching the surface texture, obtained after the first dry etching, in a plasma comprising fluorine (F) radicals, wherein the spikes are etched substantially faster than the valleys.

Abstract: A structure. The structure includes: a hole layer; a hole layer including a top hole layer surface, wherein the hole layer has a thickness in a first direction that is perpendicular to the hole layer surface; a bottom antireflective coating (BARC) layer on and in direct physical contact with the hole layer at the top hole layer surface; a photoresist layer on and in direct physical contact with the BARC layer, wherein a continuous hole in the first direction extends completely through the photoresist layer, the BARC layer, and the hole layer; and a polymerized hole shrinking region in direct physical contact with the photoresist layer at a lateral surface of the photoresist layer and with the hole layer at the top hole layer surface, wherein the hole shrinking region does not extend below the hole layer surface in a direction from the BARC layer to the hole layer.

Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

Abstract: At least a first reticle is stored in a housing of a stocker. A first gas is delivered to the housing. At least one reticle pod having an additional reticle is delivered into a enclosure within the housing of the stocker. A second gas different from the first gas is delivered to the enclosure. The reticle pod is automatically retrieved from the enclosure. The delivery and retrieval of the reticle pod and delivery of the first gas and the second gas are automatically controlled.

Abstract: A silicon carbide layer is thermally etched by supplying the silicon carbide layer with a process gas that can chemically react with silicon carbide, while heating the silicon carbide layer. With this thermal etching, a carbon film is formed on the silicon carbide layer. Heat treatment is provided to the silicon carbide layer to diffuse carbon from the carbon film into the silicon carbide layer.

Abstract: A corrosion resistant component of a plasma chamber includes a liquid crystalline polymer. In a preferred embodiment, the liquid crystalline polymer (LCP) is provided on an aluminum component having an anodized or non-anodized surface. The liquid crystalline polymer can also be provided on an alumina component. The liquid crystalline polymer can be deposited by a method such as plasma spraying. The liquid crystalline polymer may also be provided as a preformed sheet or other shape adapted to cover the exposed surfaces of the reaction chamber. Additionally, the reactor components may be made entirely from liquid crystalline polymer by machining the component from a solid block of liquid crystalline polymer or molding the component from the polymer. The liquid crystalline polymer may contain reinforcing fillers such as glass or mineral fillers.

Abstract: A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.

Abstract: A micromechanical method for manufacturing a cavity in a substrate, and a micromechanical component manufactured with this method. In this method, in a first step a first layer is produced on or in a substrate. At least one second layer is then applied onto the first layer. An access hole is produced in this second layer. Material of the first layer and of the substrate can be dissolved out through this hole, so that a cavity is produced in the substrate beneath at least a portion of the second layer. This second layer above the cavity can subsequently be used as a membrane. In addition, the possibility also exists of depositing further layers onto the second layer, only the totality of which layers constitutes the membrane. The material of the first layer is selected so that dissolving out the material of the first layer produces a transition edge in the first layer, which edge at is at a predefinable angle between the substrate and the second layer.

Abstract: The present invention provides a method of manufacturing a semiconductor device. The method includes stacking a SiO2 film, a N-containing stopper film, and a resist pattern in this order on a semiconductor substrate, performing etching on the stopper film and the SiO2 film with a F-containing etching gas, with the resist pattern serving as a mask to form an opening, and performing ashing on the resist pattern to remove the resist pattern, using a gas containing an oxygen gas and an inert gas under the condition that the ratio of the oxygen radical to the inert-gas radical becomes equal to or lower than 5.

Abstract: There are provided a processing liquid for suppressing pattern collapse of a microstructure formed of polysilicon which includes at least one compound selected from the group consisting of pyridinium halides containing an alkyl group having 12, 14 or 16 carbon atoms, and water; and a method for producing a microstructure using the processing liquid.

Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.

Abstract: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area.

Abstract: There are provided a processing liquid for suppressing pattern collapse of a microstructure which includes at least one compound selected from the group consisting of an imidazolium halide containing an alkyl group having 12, 14 or 16 carbon atoms, a pyridinium halide containing an alkyl group having 14 or 16 carbon atoms and an ammonium halide containing an alkyl group having 16 or 18 carbon atoms, and water; and a method for producing a microstructure formed of silicon oxide using the processing liquid.

Abstract: A method for etching a line pattern in an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The method includes opening the ARC layer, in which an ARC opening gas comprising CF3I, a fluorocarbon (including hydrofluorocarbon) containing gas, and an oxygen containing gas are provided, a plasma is formed from the ARC opening gas to open the ARC layer, and providing the ARC opening gas is stopped. Line pattern features are etched into the etch layer through the opened ARC layer.

Abstract: Disclosed is a supercritical processing apparatus and a supercritical processing method for suppressing the pattern collapse or the injection of material constituting a processing liquid into a substrate. A processing chamber receives a substrate subjected to a processing with supercritical fluid, and a liquid supply unit supplies a processing liquid including a fluorine compound to the processing chamber. A liquid discharge unit discharges the supercritical fluid from the processing chamber, a pyrolysis ingredient removing unit removes an ingredient facilitating the pyrolysis of a liquid from the processing chamber or from the liquid supplied from the liquid supply unit, and a to heating unit heats the processing liquid including a fluorine compound of hydrofluoro ether or hydrofluoro carbon.

Abstract: Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of H2O2 and HNO3 to remove damaged chalcogenide from the sidewalls of the memory cell structures.

Abstract: In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.

Abstract: A method for processing a sample using an electrically neutral reactive cluster is provided. The surface of a sample is processed by jetting out a mixed gas that is composed of a reactive gas and a gas with a boiling point lower than that of the reactive gas from a gas jetting part of a vacuum process room in which the sample is placed by a pressure in a range in which the mixed gas is not liquefied, in a predetermined direction, while adiabatically-expanding the mixed gas, thereby generating a reactive cluster and jetting the reactive cluster against the sample in the vacuum process room.

Abstract: A method of manufacturing a semiconductor device, includes supplying a first etching gas and a second etching gas having a decomposition rate lower than that of the first etching gas from one end of a substrate accommodating region in a process chamber where a plurality of substrates are stacked while exhausting an inside of a process chamber from other end of the substrate accommodating region; and etching a first portion of the plurality of substrate at the one end of the substrate accommodating region using a portion of radicals generated from the first etching gas and second etching gas, and etching a second portion of the plurality of substrates at the other end of the substrate accommodating region using at least a portion of a remaining radicals of the radicals generated from the first etching gas and second etching gas.

Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process.

Abstract: A substrate processing apparatus cleaning method that includes: containing a cleaning gas in a reaction tube without generating a gas flow of the cleaning gas in the reaction tube by supplying the cleaning gas into the reaction tube and by completely stopping exhaustion of the cleaning gas from the reaction tube or by exhausting the cleaning gas at an exhausting rate which substantially does not affect uniform diffusion of the cleaning gas in the reaction tube from at a point of time of a period from a predetermined point of time before the cleaning gas is supplied into the reaction tube to a point of time when several seconds are elapsed after starting of supply of the cleaning gas into the reaction tube; and thereafter exhausting the cleaning gas from the reaction tube.