Abstract: For fabricating a phase change memory cell, a layer of phase change material and a layer of a first electrode material are deposited. In addition, the first electrode material is patterned using an etchant including a low-reactivity halogen element such as bromine or iodine to form a first electrode. By using the low-reactivity halogen element, change to the composition of the phase change material and formation of undercut and deleterious halogen by-product are avoided.

Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer on a layer that is to be subjected to etching and contains at least one of silicon carbonate, silicon oxide, sapphire, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum nitride, the mask layer having an opening and including a nickel chrome film, a gold film, and a nickel film in this order when seen from the layer to be subjected to etching; and performing etching on the layer to be subjected to etching, with the mask layer serving as a mask.

Abstract: A dielectric layer including cerium oxide and aluminum oxide acting as a single dielectric layer, and a method of fabricating such a dielectric layer, produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. Such a dielectric layer including cerium oxide and aluminum oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memory, or as a dielectric in an NROM device, among others, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film.

Abstract: Certain embodiments of the present invention are directed to a method of fabricating a mixed-scale electronic interface. A substrate is provided with a first set of conductive elements. A first layer of nanowires may be formed over the first set of conductive elements. A number of channels may be formed, with each of the channels extending diagonally through a number of the nanowires of the first layer. A number of pads may be formed, each of which is electrically interconnected with an underlying conductive element of the first set of conductive elements and one or more adjacent nanowires of the first layer of nanowires. The pads and corresponding electrically interconnected nanowires define a number of pad-interconnected-nanowire-units. Additional embodiments are directed to a method of forming a nanoimprinting mold and a method of selectively programming nanowire-to-conductive element electrical connections.

Abstract: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning the dielectric layer and the lower electrode layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer and a lower electrode; and sequentially forming a first metal interconnection line connected with the contact plug and second metal interconnection lines connected with the capacitor.

Abstract: A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions. A conductive layer is formed on the first interlayer dielectric to fill the contact holes. Forming a hard mask layer on the conductive layer and etching the hard mask layer and the conductive layer to form contact plugs in the contact holes. Finally, forming a conductive layer pattern that is located on the contact plug and portions of the first interlayer dielectric adjacent to the contact plug and having a hard mask thereon.

Abstract: A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed over the first barrier layer. The second barrier layer is comprised of TaN or WN. We planarize a first conductive layer to form a first contact plug in the contact hole. We reactive ion etch (e.g., W touch up etch) the top surfaces using a Cl and B containing etch. Because of the composition of the barrier layers and RIE etch chemistry, the barrier layers are not significantly etched selectively to the dielectric layer. In a second embodiment, a barrier film is comprised of WN.

Abstract: A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode.

Abstract: Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants, wherein at least one of the plurality of etchants comprises an inert gas and oxygen, wherein the etchant oxidizes the at least one layer that can be oxidized such that the etching stops, the plurality of etchants leaving substantially unaffected a masked region associated with each layer of the plurality of layers, wherein two or more of the plurality of layers comprises a memory stack, and preventing corrosion of at least one of the plurality of layers comprising a conductive metal oxide by supplying oxygen to the stack after etching the unmasked region without breaking the vacuum.

Abstract: A thin-film capacitor assembly includes a first metal bottom electrode, a dielectric layer, a second metal etch-stop layer, and a subsequent metal top electrode. The first metal bottom electrode is in contact with the dielectric layer. The second metal etch-stop layer is in contact with the dielectric layer. The subsequent metal top electrode is in contact with the second metal etch-stop layer. Processing of the thin-film capacitor assembly includes totally removing a stiffener after assembling the first metal bottom electrode as a layer to the dielectric layer and the second metal etch-stop layer. The stiffener is removed from above and on the second metal etch-stop layer. The thin-film capacitor assembly is laminated to a mounting substrate.

Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.

Abstract: Method for recovering treated metal silicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal silicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then exposed to one or more silicon-containing compounds at conditions sufficient to recover the metal silicide surface.

Abstract: An inventive semiconductor device production method is a method for producing a semiconductor device having a metal interconnection by etching a metal film including a lower layer of a first metal material and an upper layer of a second metal material different from the first metal material. In the production method, the upper layer is selectively etched under conditions such that an etching rate for the upper layer is higher than an etching rate for the lower layer. The etching is terminated when the lower layer is exposed. Thereafter, the upper layer is over-etched under conditions such that the etching rate for the upper layer is substantially equal to the etching rate for the lower layer. Then, the lower layer is selectively etched.

Abstract: A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before being dipped in a cleaning solution containing both the etch retardant and an etchant. The dip in etch retardant modifies the surface of the BPSG, thereby lessening the enhanced etching experienced during the initiation of the dip into the etchant/etch retardant cleaning solution. Results of a etchant/etch retardant clean, both with and without the prepassivation, can be illustrated on a graph depicting the change in contact diameter as a function of dip time. Specifically, the results define “best fit” lines on that graph.

Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

Abstract: In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.

Abstract: A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.

Abstract: A method of multilevel microfabrication processing is provided. The method includes providing a planar substrate that comprises one or more material layers. A first hardmask layer placed on top of the substrate is patterned into the lithographic pattern desired for the top lithographic layer. Subsequent hardmask layers are patterned until the number of hardmask layers equals the number of lithographic layers desired. The method includes etching into the substrate and stripping the top hardmask layer. Furthermore, the method includes alternating etching into the substrate and stripping the subsequent hardmask layers until the bottom hardmask layer is stripped.

Abstract: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.

Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.

Abstract: Nanowire articles and methods of making the same are disclosed. A conductive article includes a plurality of inter-contacting nanowire segments that define a plurality of conductive pathways along the article. The nanowire segments may be semiconducting nanowires, metallic nanowires, nanotubes, single walled carbon nanotubes, multi-walled carbon nanotubes, or nanowires entangled with nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. A strapping material may be positioned to contact a portion of the plurality of nanowire segments. The strapping material may be patterned to create the shape of a frame with an opening that exposes an area of the nanowire fabric. Such a strapping layer may also be used for making electrical contact to the nanowire fabric especially for electrical stitching to lower the overall resistance of the fabric.

Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.

Abstract: A method and system for selectively and uniformly etching a dielectric layer with respect to silicon and polysilicon in a dry plasma etching system are described. The etch chemistry comprises the use of fluorohydrocarbons, such as CH2F2 and CHF3. High etch selectivity and acceptable uniformity can be achieved by selecting a process condition, including the flow rate of CH2F2 and the power coupled to the dry plasma etching system, such that a proper balance of active etching radicals and polymer forming radicals are formed within the etching plasma.

Abstract: A method of manufacturing a semiconductor device, includes: forming a resin layer with a resin containing an aromatic compound on a surface, where an electrode is formed, of a semiconductor substrate, by avoiding at least part of the electrode; removing an oxide film from a surface of the electrode using Ar gas and carbonizing the surface of the resin layer to form a carbonized layer; forming wiring from the electrode to over the carbonized layer; and etching, after forming the wiring, the carbonized layer by O2 plasma using the wiring as a mask so as to remove the carbonized layer partially.

Abstract: To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.

Abstract: A method of forming a metal line is provided. A first metal layer and a second metal layer protecting the first metal layer are formed on a base substrate. The first metal layer includes aluminum or aluminum alloy. A photoresist pattern having a linear shape is formed on the second metal layer. The first and second metal layers are dry-etched using etching gas and the photoresist pattern as an etching mask. An etching material is removed from the base substrate, to prevent corrosion of the dry-etched first metal layer. Therefore, the source metal pattern without corrosion may be formed through a dry-etching process so that a manufacturing cost is decreased.

Abstract: A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming an insulation layer over a substrate; forming a hard mask layer over the insulation layer; forming a photoresist pattern over the hard mask layer; forming a polymer over the photoresist pattern to increase a thickness of the photoresist pattern; patterning the hard mask layer by using the photoresist pattern having the increased thickness; and selectively removing the insulation layer by using the photoresist pattern having the increased thickness and the hard mask layer as an etch mask to form a contact hole.

Abstract: The present invention relates to a method for fabricating a semiconductor device with a fine pattern even without decreasing a line width of a photoresist pattern. The method includes the steps of: forming a target etching layer on a substrate; forming a plurality of etch mask patterns with high pattern density in a first region and a low pattern density in a second region on the target etching layer; removing a native oxide layer grown on the target etching layer such that a line width of each etch mask pattern decreases in more extents in the second region than in the first region; and etching the target etching layer by using the plurality of etch mask patterns as a mask.

Abstract: A method for forming a metal pattern in a semiconductor device includes preparing a semi-finished substrate with a metal layer for use as a metal pattern, performing a cleaning process inducing oxidation over an upper surface of the metal layer to form an anti-scattering reflection layer over the upper surface of the metal layer, forming a photoresist pattern over the anti-scattering reflection layer, and etching the anti-scattering reflection layer and the metal layer exposed by the photoresist pattern to form the metal pattern.

Abstract: Methods of etching a dielectric layer and a cap layer over a conductor to expose the conductor are disclosed. In one embodiment, the methods include the use of a silicon dioxide (SiO2) etching chemistry including octafluorocyclobutane (C4F8) and a titanium nitride (TiN) etching chemistry including tetrafluoro methane (CF4). The methods prevent etch rate degradation and exhibit reduced electro-static discharge (ESD) defects.

Abstract: A fluorine-free integrated process for plasma etching aluminum lines in an integrated circuit structure including an overlying anti-reflection coating (ARC) and a dielectric layer underlying the aluminum, the process being preferably performed in a single plasma reactor. The ARC open uses either BCl3/Cl2 or Cl2 and possibly a hydrocarbon passivating gas, preferably C2H4. The aluminum main etch preferably includes BCl3/Cl2 etch and C2H4 diluted with He. The dilution is particularly effective for small flow rates of C2H4. An over etch into the Ti/TiN barrier layer and part way into the underlying dielectric may use a chemistry similar to the main etch. A Cl2/O2 chamber cleaning may be performed, preferably with the wafer removed from the chamber and after every wafer cycle.

Abstract: A cleaning solution selectively removes a titanium nitride layer and a non-reacting metal layer. The cleaning solution includes an acid solution and an oxidation agent with iodine. The cleaning solution also effectively removes a photoresist layer and organic materials. Moreover, the cleaning solution can be employed in tungsten gate electrode technologies that have been spotlighted because of the capability to improve device operation characteristics.

Abstract: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated from the composite material by etching at least a portion of the metal oxide matrix to release the metal nanoparticles. In accordance with the embodiments of the invention, the nanoparticles are treated with surfactants and wetting agents either while etching or after etching, are isolated from the etchant and dispersed in a solvent medium and/or are otherwise treated or modified for use in a nanoparticle inks. A layer of the metal nanoparticle ink can then be used to form doped, undoped, patterned and unpatterned device layers or structures in micro-devices.

Abstract: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated from the composite material by etching at least a portion of the metal oxide matrix to release the metal nanoparticles. In accordance with the embodiments of the invention, the nanoparticles are treated with surfactants and wetting agents either while etching or after etching, are isolated from the etchant and dispersed in a solvent medium and/or are otherwise treated or modified for use in a nanoparticle inks. A layer of the metal nanoparticle ink can then be used to form doped, undoped, patterned and unpatterned device layers or structures in micro-devices.

Abstract: A system and method of passivating an exposed conductive material includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber. A hydrogen species plasma is formed in the process chamber. A surface layer species is reduced from a top surface of the substrate is reduced. The reduced surface layer species are purged from the process chamber.

Abstract: An apparatus and method are described for etching Ni-containing films using gas phase plasma etching. Etching of Ti—Ni alloys is carried out by exposure to plasma comprising hydrogen halide (HX) and carbonyl etching gases. The Ti in the Ti—Ni alloy is etched via an ion-assisted reaction with HX and the Ni is etched by reacting with CO. The method is particularly well suited for anisotropic etching of Ti—Ni metal gates for CMOS applications. Etching of Ni—Fe layers is carried out by exposure to plasma comprising a carbonyl etching gas.

Abstract: A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

Abstract: A metal layer 12 of aluminum or an aluminum alloy is formed on at least one side of a ceramic substrate 10, and a resist 14 having a predetermined shape is formed on the metal layer 12. Then, an etchant of a mixed solution prepared by mixing ferric chloride with water without adding any acids is used for etching and removing an undesired portion of the metal layer 12 to form a metal circuit 12 on the at least one side of the ceramic substrate 10.

Abstract: The present invention is a method of producing semiconductor devices and an etching liquid with which the titanium nitride film can be removed without thinning of the CoSi layer. A hydrogen peroxide-water mixture is used for removal of the titanium nitride film in the method of producing semiconductor devices by cobalt salicide technology with titanium nitride as the cap film.

Abstract: The present invention is provided to form a metal line layer in a semiconductor device, wherein at least one conductive layer of a plurality of conductive layers is etched, a side wall oxide film is formed on side walls of some conductive layers of the etched conductive layers, and then the other conductive layers are etched. According to the present invention, since it is possible to prevent attacks against the side walls, which may occur due to sputtering and bending of plasma ions, it is possible to enhance yield and reliability of a semiconductor device.

Abstract: Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a photolithographic reticle including positioning the reticle in a first orientation on a reticle support in a processing chamber, wherein the reticle comprises a metal photomask layer formed on an optically transparent substrate, and a patterned resist material deposited on the metal photomask layer, etching the metal photomask layer in the first orientation, positioning the reticle in at least a second orientation, and etching the metal photomask layer in the at least second orientation.

Abstract: Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes.

Abstract: The present invention relates to a method for forming an inductor in a semiconductor device. The method comprises the steps of forming a first metal layer on a semiconductor substrate in which a predetermined structure is formed, and then patterning the first metal layer so that a predetermined region of the semiconductor substrate is exposed; forming a first copper layer on the entire resulting surface and then polishing the first copper layer; forming a second metal layer on the resulting surface including the polished first copper layer and then patterning the second metal layer so that predetermined regions of the first metal layer and the first copper layer are exposed; forming a second copper layer on the formed resulting surface; and polishing the resulting surface and stripping the first and second metal layers.

Abstract: A semiconductor laser element capable of reducing the contact resistance and the thermal resistance and realizing a high reliability is provided. The semiconductor laser element includes: a semiconductor substrate, an active layer formed on the semiconductor substrate, a ridge having a clad layer formed on the active layer and a contact layer formed on the clad layer, an insulation film covering the side surfaces of the clad layer, and an electrode connected to the contact layer, wherein the insulation layer has an end portion in the ridge thickness direction located between the upper surface and the lower surface of the contact layer.

Abstract: A method and apparatus that produces highly ordered, nanosized particle arrays on various substrates. These regular arrays may be used as masks to deposit and grow other nanoscale materials.

Abstract: A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.

Abstract: A method of repairing a semiconductor chip containing copper is taught, whereby copper is selectively removed from the chip. The method involves processing the chip inside a chamber in which the chip is exposed to various gases and an energy source, such as a focused ion beam. To the extent the chip may have non-copper materials, such as nitride and oxide layers, on top of the copper that is to be removed, those non-copper materials will first be selectively removed. Such removal typically results in a hole (a so-called “elevator shaft”) leading to the copper that is to be removed. Next, the method teaches the introduction of a combination of nitrogen and oxygen into the chamber and the directing of the ion beam at the spot where the copper is to be removed. In this manner, the copper on the chip is cleanly and reliably removed, without causing damage to the processing chamber.

Abstract: The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

Abstract: A chromeless phase lithography mask (30) that does not require photoresist to manufacture has a quartz substrate (32) is etched by using a plasma (38) containing one of a nitrogen augmented hydro-fluorocarbon oxygen mixture and a nitrogen augmented fluorocarbon oxygen mixture. Various hydro-fluorocarbons or fluorocarbons may be used. The nitrogen addition results in etched openings in the quartz substrate that have substantially vertical sidewalls in a uniform manner across the substrate. Surface roughness is minimized and edges of the openings are well-defined with minimal rounding. The etch rate is rendered controllable by reducing bias power without degrading a desired vertical sidewall profile.