Abstract: Fabrication of metal-on-conductive-diffusion-barrier-on-gate-dielectric structures is done by: etching the metal, by plasma-assisted anisotropic etching, down to and into the barrier metal; and then etching the remainder of the barrier layer by a dry chemical-downstream-etching process, during which the barrier layer is not exposed to ion bombardment. In the case of tungsten over titanium nitride, high selectivity and good profiles are preferably obtained, by: during the tungsten etch, using a combination of low temperature, relatively low bias, and the addition of nitrogen; and during the titanium nitride etch, using a chemical downstream etch instead of the conventional wet etch (in boiling H2SO4). (This allows better control of undercutting, and eliminates wet strip process.

Abstract: There is provided a method for forming a metal line of a semiconductor device, in which a (TiAl)N layer having a lower reflectivity and permeability is formed as anti-reflective coating layer. Since the (TiAl)N anti-reflective coating layer effectively prevent a metal line from reflecting in lightening process using a shorter wavelength such as DUV, a fine metal line can be formed exactly.

Abstract: In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Abstract: A method for etching selected portions of an aluminum-containing layer of a layer stack that is disposed on a substrate. The aluminum-containing layer is disposed below a photoresist mask having a pattern thereon. The method includes providing a plasma processing chamber and positioning the substrate having thereon the layer stack, including the aluminum containing layer and the photoresist mask, within the plasma processing chamber. The method further includes flowing an etchant source gas that comprises HCl, a chlorine-containing source gas, and an oxygen-containing source gas into the plasma processing chamber. The oxygen-containing source gas is preferably CO2. The flow rate of the oxygen-containing source gas is less than about 20 percent of a total flow rate of the etchant source gas. There is also included striking a plasma out of the etchant source gas, wherein the plasma is employed to etch at least partially through the aluminum-containing layer.

Abstract: A wet and vapor acid etching method releases a microelectromechanical systems (MEMS) structure from a substrate by dissolving a sacrificial layer disposed between the MEMS and the substrate. The sacrificial layer may be a silicon dioxide (SiO2) layer having a field portion over which the MEMS does not extend and a support portion over which the MEMS does extend. The field portion of the SiO2 layer is quickly removed using conventional wet hydrofluoric (HF) etching followed by rinsing and drying and then the support portion is removed using conventional vapor HF etching from a solution greater than 45% by weight percent. The wet HF chemical etch quickly removes the large field portion of the sacrificial layer. The HF vapor etch removes the small support portion of the sacrificial layer below the MEMS to release the MEMS from the substrate without stiction thereby preventing damage to the MEMS when released.

Abstract: A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate.

Abstract: A method mending the erosion of bonding pad. A passivation layer and a polyimide layer are sequentially formed on a wafer to cover a bonding pad, where the polyimide layer is patterned to expose a portion of the passivation layer. The polyimide layer is used as a mask for etching the passivation layer, so as to expose the bonding pad. The bonding pad is eroded by the etchant residue remaining after etching the passivation layer on the bonding pad. After removing the eroded part of the bonding pad, an oxide layer is formed subsequently to prevent a further erosion.

Abstract: A method for producing an electronic device, comprises the steps of: depositing a thin film on a substrate; etching a portion of the thin film by a reactive ion etching so as to leave a remaining portion of the thin film behind; and removing the remaining thin film by a physical etching using an inert gas.

Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

Abstract: Generally, after etching process for gate electrode patterning, oxidation process is performed to compensate for etching damage. There is provided a method for forming a gate electrode of a semiconductor device, which prevents the metal layer comprised of the gate electrode for being oxidized in such an oxidation process. In the present invention, a polysilicon layer is etched to form a gate electrode pattern and re-oxidation process is performed to compensate for the etching damage. After this, an inter-layer insulating layer is formed over the entire structure and partially removed so as to expose the polysilicon layer. A part of the polysilicon layer is then selectively removed to form an opening in the inter-layer insulating layer. Here, the other part of the polysilicon layer, which will be connected to a metal layer later, is exposed through the opening. The metal layer is then buried within the opening to complete the formation of the gate electrode made of poly-metal structure.

Abstract: The invention includes a process for the production of semiconductor devices comprising the steps of depositing a metal layer on a semiconductor substrate, depositing a hardmask layer on said metal layer, depositing a photoresist on said hardmask layer, patterning said photoresist, thereby exposing and patterning portions of said hardmask layer, etching said exposed portions of said hardmask layer with a hardmask etchant, thereby exposing and patterning portions of said metal layer, removing, or not, said photoresist, and etching said exposed portions of said metal layer with a metal etchant and semiconductor devices made by said process.

Abstract: A method for forming a patterned platinum layer on a microelectronic substrate includes the steps of forming a platinum layer on the microelectronic substrate, and forming a mask layer on the platinum layer. In particular, the mask layer defines exposed portions of the platinum layer, and the mask layer comprises a mask material including titanium. The exposed portions of the platinum layer are then selectively removed to form the patterned platinum layer. Related structures are also disclosed.

Abstract: An interconnection pattern made of aluminum alloy, such as Al-Cu, on a semiconductor IC, is dry etched in an etching gas containing a chlorine component. Residual chlorine components on the substrate are difficult to remove, thus causing corrosion problems with respect to the patterned aluminum alloy layer. Accordingly, to prevent such corrosion, a photo resist stripping process is carried out at a location down stream of the etching process using a conventional stripping gas, such as CF4+O2, at room temperature. Next, and before the resist-stripped substrate is exposed to open air, the substrate is heated in a vacuum to a temperature above 100° C., to thus remove residual chlorine components. In an alternative method, the heating process is carried out concurrently with the resist stripping process.

Abstract: A method for fabricating a capacitor is described. A dielectric layer and a polysilicon layer thereon are provided. A patterned oxide layer and spacers on the sidewalls of the patterned oxide layer are formed. The polysilicon layer is etched using the oxide layer and spacer as an etching mask. The oxide layer and spacer are then removed. A dielectric layer and a conductive layer are sequentially formed on the polysilicon layer.

Abstract: A method is provided for forming an unlanded via hole that substantially solves both the problems of high resistance and via profile loss due to etching. A patterned conductor layer on a first dielectric layer is provided firstly. A first insulating layer is then formed on the first dielectric layer and the conductor layer. A second dielectric layer is formed on the first insulating layer and subsequently etched back until the conductor layer is exposed. The following procedure is to form a second insulating layer on the second dielectric layer and the conductor layer. A third dielectric layer is formed on the second insulating layer. Thereafter, a patterned photoresist layer is formed on the third dielectric layer. Then the etching process is used to etch the third dielectric layer and the second insulating layer to form an unlanded via hole. Finally, the photoresist layer is removed. The unlanded via hole proposed in according with the present invention produces an unlanded via having a good profile.

Abstract: A method of manufacturing a semiconductor wafer wherein a layer of hardmask material is formed on the surface of a metal layer formed on a layer of interlayer dielectric formed on a semiconductor substrate on and in which active devices have been formed. A layer of photoresist is formed on the surface of the layer of hardmask material, patterned and developed exposing portions of the underlying layer of hardmask material. The semiconductor wafer is placed in an etched and the layer of hardmask material is etched in a first process utilizing a combination fluorine and chlorine chemistry and the metal layer is etched in a second process utilizing a combination fluorine and chlorine chemistry.

Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

Abstract: An Integrated Circuit Design which adds, to the standard conducting lines of the bulk metal layer, a pattern of a support structure which supports subsequent deposition in such a way that it eliminates previously experienced concavity or dishing of the subsequent deposition within areas which have a low density or absence of conducting lines. The dummy pattern enhances the deposition of filler material between conducting lines of the Integrated Circuit such that planarization of the bulk metal results in a smoother surface of the areas of the signal lines of the integrated circuit and within large open areas. Concurrently the present invention provides a means of successfully collecting data that are needed for Damascene processing.

Abstract: Disclosed herein is a post-etch treatment for plasma etched metal-comprising features in semiconductor devices. The post-etch treatment significantly reduces or eliminates surface corrosion of the etched metal-comprising feature. It is particularly important to prevent the formation of moisture on the surface of the feature surface prior to an affirmative treatment to remove corrosion-causing contaminants from the feature surface. Avoidance of moisture formation is assisted by use of a high vacuum; use of an inert, moisture-free purge gas; and by maintaining the substrate at a sufficiently high temperature to volatilize moisture.

Abstract: A method for manufacturing a semiconductor wafer begins by placing the wafer into a process chamber (74). A metal etch gas is then provided through a gas fitting (52) having an outlet tube (52b). The outlet tube (52b) is threadless and is made of a material which will not substantially corrode in the presence of the corrosive etch gas. In addition, the outlet tube (52b) contains gas distribution openings (84) which improve gas distribution within a gas channel (54b) of a gas ring (54). The elimination of the threading in the gas feed inlet (54a) of the gas ring (54) will allow a sidewall of the inlet (54a) to be anodized for greater corrosion protection. The reduction in corrosion will improve wafer yield, reduce manufacturing costs, and reduce equipment down time.

Abstract: A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.

Abstract: A contact hole reaching a surface of a silicon substrate and a contact hole penetrating a resistor are formed on an interlayer insulation film by simultaneous etching. Then, a laminated film having a lower Ti layer and an upper TiN layer is formed as a substrate layer (barrier layer) of a wiring on the interlayer insulation film to bury the contact hole. Then, an annealing treatment is carried out at a temperature of 620.degree. C. Consequently, the laminated film buried in the contact hole penetrating the resistor and the resistor are caused to electrically come in contact with each other on a side face of the wiring (side contact).

Abstract: A dual damascene process using selective tungsten chemical vapor deposition is provided for forming composite structures for local interconnects comprising line trenches with contact holes, and composite structures for intermetal interconnects comprising line trenches with via holes. It is shown that by forming a seed layer in judiciously selected portions of the dual damascene structure and depositing tungsten selectively in one step, contact holes and via holes can be formed free of voids and key-holes.

Abstract: A method for generating information for producing a pattern, defined by design information on a medium, using at least one direct-writing pattern generating process, which first provides the design information and then calculates correction data based on the provided design information and depending on the pattern generating process which corrects pattern faults in the pattern to be generated which were caused by the pattern generating process. The design and correction information is then separately provided to the direct-writing pattern generating process for its activation.

Abstract: A process for forming a via in a semiconductor device using a self-aligned tungsten pillar to connect upper and lower conductive layers separated by a dielectric. A Ti/TiN layer is formed on an underlying substrate layer, an aluminum-copper layer is formed on the Ti/TiN layer, a TiN layer is formed on the aluminum-copper layer and a tungsten layer is formed on the TiN layer. In one continuous etching step, the stack of tungsten, TiN, Al--Cu, Ti/TiN is then patterned and etched. A first dielectric is deposited overlying the exposed regions of the substrate layer and the conductive stack. The wafer is then planarized to expose the top of the tungsten layer. The wafer is again patterned and the tungsten is etched using the titanium nitride as an etch stop. A second dielectric is deposited to fill the resulting gaps and CMP processes are used to planarize the wafer and expose the top of the tungsten pillar.

Abstract: A multi-step dry-etching method that sequentially employs plasma etching and reactive ion etching process steps to form the pairs of adjacent, doped polysilicon gate electrodes of a twin-well CMOS device. The initial dry-etching process step uses to best advantage the speed of plasma etching to rapidly form pairs of adjacent p- and n-type gate-precursor features with substantially vertical sidewalls from the upper 50-80% of a doped polysilicon layer which lies on an insulating film. The gate-precursor features and, subsequently, the gate electrodes are formed from pairs of adjacent p- and n-type regions within the doped polysilicon layer which lie over pairs of adjacent n- and p-wells (the twin wells of the CMOS device), respectively, within a substrate. The subsequent dry-etching process step uses reactive ion etching to complete the formation of the pairs of adjacent, doped polysilicon gate electrodes from the remaining 50-20% of the etched, doped polysilicon layer without over-etching the insulating film.

Abstract: A new method of cleaning metal precipitates after the etching of metal lines using a two-step process is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer wherein metal precipitates form at the interface between the barrier metal layer and the metal layer. The metal layer is covered with a layer of photoresist which is exposed to actinic light and developed and patterned to form the desired photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask to form metal lines whereby the metal precipitates are exposed on the surface of the barrier metal layer.

Abstract: A method for fabricating semiconductor devices that allows for the integration of anti-reflective coatings into the fabrication process. A method for removing an inorganic anti-reflective coating is disclosed that includes the step of exposing the layer of inorganic anti-reflective coating to atomic fluorine. An asher is used to generate fluorine atoms from NF.sub.3 precursor gas. The NF.sub.3 precursor gas is mixed with an inert carrier such as helium. In one embodiment, sequential etch steps are performed in an asher so as to sequentially remove both a layer of photoresist and a layer of inorganic anti-reflective coating.

Abstract: A new method of etching metal lines using SF.sub.6 gas during the overetch step to prevent undercutting of the anti-reflective coating layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer. A silicon oxide layer is deposited overlying the metal layer. The silicon oxide layer is covered with a layer of photoresist which is exposed, developed, and patterned to form the desired photoresist mask. The silicon oxide layer is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer is etched away where it is not covered by the patterned hard mask to form metal lines. Overetching is performed to remove the barrier layer where it is not covered by the hard mask wherein SF.sub.

Abstract: A process for reducing dimensions of circuit elements in a semiconductor device. The process reduces feature sizes by using an intermediate etchable mask layer between a photo-resistive mask and a layer to be etched. The etchable mask layer below the photo-resistive mask is etched and portions remain which undercut the pattern on the photo-resistive mask. After removing the photo-resistive mask, the remaining mask portions are then used to mask the layer to be etched. By undercutting the photo-resistive mask, the mask portions form a pattern having features with widths that are less than widths of features in the photo-resistive mask. The layer to be etched can then be etched to provide circuit elements with reduced dimensions.

Abstract: A process for forming a semiconductor device using a conductive etch stop. The process includes the steps of fabricating a wafer structure up to a first level oxide deposition. A conductive etch stop is deposited over the first level oxide deposition, and selected portions of the conductive etch stop are removed. An inter-level oxide layer is deposited on the conductive etch stop, and selected portions of the inter-level oxide deposition are etched up to the conductive etch stop. The conductive etch stop may be either removed from the semiconductor or left as a conductor.

Abstract: An interconnect layer is fabricated using a tungsten hard mask by forming a tungsten based layer over an aluminum based layer. A photoresist layer is deposited over the tungsten based layer and patterned. The tungsten based layer is patterned by applying a fluorine-based etchant using the photoresist layer as an etch mask. Then the aluminum based layer is patterned by applying a chlorine based etchant using the tungsten based layer as an etch mask.

Abstract: Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). The first disposable gate structure (26) may comprise a replaceable material. A second disposable gate structure (28) of the second complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A replacement layer (70) may be formed over the first disposable gate structure (26). The replacement layer (70) may comprise a replacement material. At least a portion of the replaceable material of the first disposable gate structure (26) may be substitutionally replaced with the replacement material of the replacement layer (70) to form a first gate structure (80).

Abstract: A wiring pattern forming method includes the step of: forming resist patterns on an aluminum or aluminum alloy conductive layer, the resist patterns including a low density pattern area and a high density pattern area; etching and removing a portion of a thickness of the conductive layer by an etching process presenting anti-microloading effect by using the resist patterns as an etching mask, and etching and removing another portion of the thickness of the conductive layer by an etching process presenting microloading effect by using the resist patterns as an etching mask. A method of forming an aluminum or aluminum alloy wiring pattern is provided which can maintain a high etching rate and reduce electron shading damage.

Abstract: A method for forming a passivation layer with improved planarity includes patterning a top interconnect metal layer through two steps of etching, in which the metal layer is formed over a substrate that has device elements already formed thereon. The first etching process is isotropic etching, which undercuts an etching mask layer. The upper sharp corners of the metal layer are removed. The second etching process in anisotropic etching to complete an opening that exposes the substrate. A PSG layer and a silicon nitride layer are sequentially formed to serve as a passivation layer. Since the aspect ratio is reduced due to undercutting, a void within the opening is avoided, and a crack in the passivation layer within the opening is also avoided.

Abstract: A carbon-containing film, which is made of a carbon-containing material, is adhered to the inner wall of a chamber. A semiconductor substrate is arranged in the chamber whose inner wall has the carbon-containing film adhered thereto. A plasma of a process gas which contains a rare gas is generated in the chamber, and such an electric field as to cause ions contained in the plasma to be attracted to a surface of the semiconductor substrate is applied in order to etch a part of the surface layer of the semiconductor substrate. During the etching, a film which contains a constituent or constituents of an etched film adheres to the surface of the carbon-containing film. The carbon-containing film prevents the peeling off of such an adhering film from the inner wall of the chamber, thereby reducing the generation of particles.

Abstract: A method and system for patterning a metal layer of a semiconductor device is disclosed. The method and system includes providing a material with an antireflective low dielectric constant hard mask layer (antireflective low k hard mask layer) on top of the metal layer, and providing a photoresist pattern on top of the anti-reflective low k hard mask layer. The method and system further includes etching of the anti-reflective low k hard mask layer and etching of the metal layer, wherein the photoresist is removed but the anti-reflective low k hard mask layer remains. In a preferred embodiment, the mask layer can also be applied at low temperatures (i.e., >300.degree.) to ensure that the physical properties of the integrated circuit are not affected. Finally, the low k material does not have to be removed after processing.

Abstract: A method for forming integrated circuit conductors. The method includes the steps of placing in a reactive ion etching chamber a semiconductor body having disposed over a surface thereof: a metalization layer comprising an aluminum layer disposed between a pair of barrier metal layers; and, a photoresist layer disposed on a selected portion of a surface of an upper one of the pair of barrier layers. Radio frequency energy is inductively coupled into the chamber while silicon tetrachloride and chlorine are introduced into the chamber at rates selected to etch portions of the metalization layer exposed by the photoresist with aluminum having substantially vertical sidewalls. The silicon tetrachloride is introduced into the chamber at a rate in the range of 4 to 8 sccm. The rate of the chlorine is in the range of 50 sccm to 150 sccm. The chamber is at a pressure of about 12 milliTorr during the etching of the metalization layer.

Abstract: An apparatus and method are presented for electrically determining whether delamination has occurred at one or more interfaces within a semiconductor wafer. The semiconductor wafer includes a test structure formed within dielectric layers upon an upper surface of a semiconductor substrate. The test structure includes an electrically conductive structure, a pair of electrically conductive contact plugs, and a probe pad. The conductive structure is formed within an opening in a first dielectric layer, and is in electrical contact with the upper surface of the semiconductor substrate. The conductive structure is preferably made up of the same vertical stack of layers of selected electrically conductive materials used to form interconnects within the semiconductor wafer. A second dielectric layer if formed over the first dielectric layer and the conductive structure. The pair of electrically conductive contact plugs extend vertically through respective holes in the second dielectric layer.

Abstract: The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.

Abstract: An etch method includes providing a material layer consisting essentially of a group member selected from the group consisting of an indium oxide (InO), a tin oxide (SnO), a mixture of indium and tin oxides, a compound of indium and of tin and of oxygen having the general formulation In.sub.x Sn.sub.y O.sub.z where z is substantially greater than zero but less than 100% and where the sum x+y fills the remainder of the 100%, and a mixture of the preceding ones of the group members. A reactive gas including a halogen-containing compound and an oxygen-containing compound is supplied to a vicinity of the material layer. Also, an electric field is supplied to react the supplied reactive gas with the material layer so as to form volatile byproducts of reactive gas and the material layer.

Abstract: A method for plasma assisted CVD deposition of tungsten and of tungsten compounds is described wherein a plasma containing a high density of active hydrogen species is maintained to scavenge fluorine and fluoride species formed by the decomposition of the tungsten precursor WF.sub.6. The activated hydrogen species also assist in the breaking of W--F bonds, thereby facilitating the decompoition process and forming high density, high conductivity, fluoride free conductive films of tungsten and of tungsten compounds. The ability to form such fluoride free tungsten films with the assistance of activated hydrogen species, permits the deposition of tungsten directly onto gate oxides thereby enabling the formation of tungsten gate electrodes without underlying polysilicon. Low conductivity tungsten contacts including in-situ formed tungsten compound barrier layers may also be formed by this process.

Abstract: A method for improving the patterning process of a conductive layer using a dual-layer cap of oxynitride and silicon nitride. The oxynitride layer acts as a BARC (Bottom Anti-Reflective Coating) to improve photolithography process performance. The oxynitride is formed by plasma-enhanced chemical vapor deposition.

Abstract: There is provided a method of etching metallic film for a semiconductor device, in which a semiconductor substrate with a metallic film exposed in a film pattern is inserted onto a chuck in a chamber of an electrostatic shielded radio frequency (ESRF) inductive-coupled plasma source, the ESRF inductive-coupled plasma source also including a coil connected to an upper electrode, a lower electrode connected to the chuck, a gas supply assembly, a pressure control assembly and a temperature control assembly. An etching gas is supplied to the chamber at a predetermined etch gas supply rate. Pressure inside the chamber is maintained at a predetermined pressure level. The upper and lower electrodes are powered with predetermined upper and lower powers, respectively, at predetermined upper and lower RFs, respectively. The chamber walls are cooled to a predetermined temperature.

Abstract: A process for plasma etching metal films comprising the steps of forming a noble gas plasma, then transporting the noble gas plasma to a mixing chamber. An organohalide is added to the noble gas plasma in the mixing chamber. The organohalide is selected to have a vapor pressure allowing the formation of activated complexes to etch the metal films and form organometallic compounds as the etch byproducts. The activated complexes thus formed are transported downstream to an etching chamber. In the etching chamber the selected substrate is exposed to the activated complexes, causing the substrate to be etched and organometallic compounds to be formed as byproducts from the reaction of the activated complexes and etching of the substrate. The organometallic byproducts can then be removed from the etch chamber.

Abstract: A passivation coating is formed on a photoresist mask to increase the resistance of the mask during subsequent etching of an underlying conductive layer to form a pattern of sub-half micron conductive lines. In an embodiment of the invention, the passivation coating is formed by exposing the mask to a plasma containing nitrogen. The passivating coating maintains the substantially vertical mask profile during subsequent etching, such as high density plasma etching, thereby improving the dimensional integrity of the sub-half micron conductive lines.

Abstract: A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate.

Abstract: A refractory metal layer is formed on the entire surface of an interlayer insulating film having a connection hole, and then etched back by using an etching gas containing at least one of Kr, Xe, and Rn, each of which is an inert gas element having a large atomic weight. A contact plug is formed by using a resulting refractory metal layer. By employing this manufacturing method, a refractory metal layer formed by the blanket CVD method can be etched while the loading effect is prevented during overetching, and a contact plug having a flat burying surface can be formed without causing any abnormal eroded portion in a connection hole of an interlayer insulating film.

Abstract: A method in a plasma processing system having a top electrode and a bottom electrode for etching through a portion of a selected layer of a layer stack of a wafer. The method includes the step of etching at least partially through the selected layer while providing a first radio frequency (RF) signal having a first RF frequency to the top electrode. The method further includes the step of providing a second RF signal having a second RF frequency lower than the first RF frequency to the bottom electrode.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket chlorine containing plasma etchable layer. There is then formed upon the blanket chlorine containing plasma etchable layer a blanket hard mask layer. There is then formed upon the blanket hard mask layer a patterned photoresist layer. There is then etched the blanket hard mask layer to form a patterned hard mask layer while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer. There is then etched the blanket chlorine containing plasma etchable layer to form a patterned chlorine containing plasma etchable layer while employing a second plasma etch method in conjunction with at least the patterned hard mask layer as a second etch mask layer.