Abstract: A wafer having on one side a device area with a plurality of devices is processed by providing a protective film and applying the protective film, for covering the devices on the wafer, to the one side of the wafer, so that a front surface of the protective film is in direct contact with the one side of the wafer. The protective film is heated during and/or after applying the protective film to the one side of the wafer, so that the protective film is attached to the one side of the wafer, and the side of the wafer opposite to the one side is processed. Further, the invention relates to a method of processing such a wafer in which a liquid adhesive is dispensed only onto a peripheral portion of a protective film and/or only onto a peripheral portion of the wafer.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.

Abstract: Particular embodiments described herein provide for an electronic device that can include a nanowire channel. The nanowire channel can include nanowires and the nanowires can be about fifteen (15) or less angstroms apart. The nanowire channel can include more than ten (10) nanowires and can be created from a MXene material.

Abstract: A testing apparatus for measuring a strength of a chip includes: a cassette mounting base on which to mount a cassette capable of accommodating wafer units; a frame fixing mechanism that fixes an annular frame of the wafer unit; a conveying mechanism that conveys the wafer unit between the cassette and the frame fixing mechanism; a pushing-up mechanism that pushes up a predetermined chip included in the wafer supported by the annular frame fixed by the frame fixing mechanism; a pick-up mechanism having a collet picking up the chip pushed up by the pushing-up mechanism; a strength measuring mechanism having a support unit supporting the chip picked up by the collet; and a collet moving mechanism that moves the collect from a position facing the pushing-up mechanism to a position facing the support unit.

Abstract: A method includes receiving a structure having a substrate, a conductive feature over the substrate, and a dielectric layer over the conductive feature. The method further includes forming a hole in the dielectric layer to expose the conductive feature; forming a first metal-containing layer on sidewalls of the hole; and forming a second metal-containing layer in the hole and surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. The method further includes applying a first chemical to recess the dielectric layer, resulting in a top portion of the first and the second metal-containing layers protruding above the dielectric layer; and applying a second chemical having fluorine or chlorine to the top portion of the first metal-containing layer to convert the top portion of the first metal-containing layer into a metal fluoride or a metal chloride.

Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.

Abstract: A substrate processing method includes the steps of: rotating a substrate horizontally around a vertical rotational axis, placing a facing member facing the substrate from above such that an inner peripheral surface of an extension portion of the facing member faces the substrate radially from the outside, rotating the facing member around the rotational axis, supplying a processing liquid to an upper surface of the substrate being in a rotated state, and placing a guard that surrounds the substrate further radially outside from the extension portion in plan view at a height position, at which processing liquid scattered from the upper surface of the substrate toward the outside in the radial direction is received by the guard, in accordance with affinity of the processing liquid for the inner peripheral surface of the extension portion.

Abstract: A method for temporary bonding workpiece includes steps as follows. A combining step is performed, wherein an adhesive layer is formed on a surface of at least one substrate and/or at least one workpiece. A bonding step is performed, wherein the substrate and the workpiece are bonded by the adhesive layer. A processing step is performed, wherein the workpiece is processed. A debonding step is performed, wherein the adhesive layer is irradiated with a laser so as to separate the workpiece from the substrate. The adhesive layer is formed by an adhesive, the adhesive includes a polymer and a light absorbing material, a content of the polymer in a solid content of the adhesive is in a range of 50 wt % to 98 wt %, a content of the light absorbing material in the solid content of the adhesive is in a range of 2 wt % to 50 wt %.

Abstract: A method for producing a SiC single crystal with few dislocations and defects and a large diameter enlargement ratio is provided. A method for producing a SiC single crystal by solution process, wherein a bottom face of a seed crystal is (0001) or (000-1) face and has circular shape with at least a partially removed section and a circular arc-shaped section on an outer periphery, the number of the removed sections is one or more, shapes of the removed sections are bow-shaped with a minor arc or semi-circumference removed along a chord connecting two points on the circular arc, a central angle formed by a center of the circular shape and the two points is 40° or greater, and a total of the central angles of the removed sections is no greater than 180°, the method comprising forming a meniscus and growing the single crystal from the bottom face.

Abstract: A method for producing a thin substrate layer having a thickness of at most 100 ?m by detaching a substrate layer from the ingot by producing a tensile stress induction on an ingot, and wherein the tensile stress induction is effected by a stressor layer structure integrally bonded to a first surface of the ingot. The stressor layer structure and the ingot have different thermal expansion coefficients, and the stressor layer structure is removed from the substrate layer after detachment of the substrate layer from the ingot. The stressor layer structure has at least one layer sequence with a first titanium-containing layer and a nickel-containing layer. The titanium-containing layer adjoins with a bottom side a first surface of the ingot and the nickel-containing layer adjoins with a bottom side a top side of the titanium-containing layer.

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

Abstract: A method for forming gate cuts during RMG processing and the resulting device are provided. Embodiments include forming Si fins over a substrate; forming a STI layer over the substrate and recessed, exposing upper portions of the Si fins; forming polysilicon dummy gate electrodes perpendicular to the Si fins, separated by STI regions, on the upper portions of the Si fins and on the STI layer between the Si fins; forming a hardmask over the polysilicon dummy gate electrodes; etching through the hardmask and polysilicon dummy gate electrodes forming cavities between some of the Si fins; oxidizing polysilicon exposed on sides of the cavities and any residual polysilicon remaining at a bottom of one or more of the cavities; filling the cavities with SiN; removing the polysilicon dummy gate electrodes; and forming RMGs.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: In one aspect, the present disclosure relates to a device including a silicon substrate, wherein at least a portion of the substrate surface can be a silicon nanowire array; and a layer of alumina covering the silicon nanowire array. In some embodiments, the device can be a solar cell. In some embodiments, the device can be a p-n junction. In some embodiments, the p-n junction can be located below the bottom surface the nanowire array.

Abstract: The present invention is a substrate for growing a single crystal diamond layer including: at least, a base material made of a single crystal diamond, and an iridium film or a rhodium film heteroepitaxially grown on a side of the base material where the single crystal diamond layer is to be grown; wherein a peripheral end portion of a surface of the base material on the side where the single crystal diamond layer is to be grown is chamfered with a curvature radius (r), the curvature radius satisfying (r)?50 ?m. As a result, there is provided a substrate for growing a single crystal diamond layer and a method for producing a single crystal diamond substrate, the substrate and the method in which a single crystal diamond having uniform and high crystallinity can be reproducibly produced at low cost.

Abstract: A method of fabricating a semiconductor sensor device includes providing a substrate, supporting a source region and a drain region with the substrate, forming an insulator layer above the source region and the drain region, and forming a porous metallic gate region above the insulator layer using plasma enhanced atomic layer deposition (PEALD).

Abstract: A method is provided in which a substrate including various materials of different fracture toughness (KIc) can be spalled in a controlled manner. In particular, a surface step region is formed within a surface portion of the substrate prior to formation of a stressor layer. The presence of the surface step region within the surface portion of the substrate controls the depth and ease at which crack initiation occurs within the substrate.

Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.

Abstract: A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The multiple-sample-holder polishing setup includes a frame. The frame has a hollow center, one or more long and short rods and a recess for accommodating a polishing head. The setup includes one or more sample holders. The sample holder is to be attached to the one or more long and short rods of the frame. A paddle is affixed to each sample holder. A sample is attached to the paddle. The sample is coated with a thin epoxy layer prior to polishing thereby allowing for easy inspection for site of interests as well as quick material removal.

Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.

Abstract: There is provided a method of fabricating a semiconductor device, the method including: forming a semiconductor component portion at a first surface of a substrate; applying a grinding treatment to a second surface of the substrate that is opposite from the first surface to form a fracture surface; applying a fracture surface removal treatment to predetermined positions of the fracture surface of the second surface; and forming an electrode at the second surface.

Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.

Abstract: A method of treating the surface of a semiconductor wafer through the formation of a bonding system is provided in order to enhance the handling of the wafer during subsequent processing operations. The method generally comprises the steps of applying a release layer and an adhesive to different wafers; bonding the wafers together to form a bonded wafer system; performing at least one wafer processing operation (e.g., wafer grinding, etc.) to form a thin processed wafer; debonding the wafers; and then cleaning the surface of the processed wafer with an organic solvent that is capable of dissolving the release layer or any residue thereof. The adhesive includes a vinyl-functionalized polysiloxane oligomeric resin, a Si—H functional polysiloxane oligomeric resin, a catalyst, and optionally an inhibitor, while the release layer is comprised of either a silsesquioxane-based resin or a thermoplastic resin.

Abstract: The yield of a peeling process is improved. A first step of forming a peeling layer to a thickness of greater than or equal to 0.1 nm and less than 10 nm over a substrate; a second step of forming, on the peeling layer, a layer to be peeled including a first layer in contact with the peeling layer; a third step of separating parts of the peeling layer and parts of the first layer to form a peeling trigger; and a fourth step of separating the peeling layer and the layer to be peeled are performed. The use of the thin peeling layer can improve the yield of a peeling process regardless of the structure of the layer to be peeled.

Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.

Abstract: One embodiment is a method for semiconductor processing. In this method, a precursor film is provided over a semiconductor substrate, where the precursor film is made of a structural former and porogen. Prior to cross-linking, the porogen is removed by exposure to UV radiation having one or more wavelengths in the range of 150 nm to 300 nm, while a temperature of 300° C. to 500° C. is applied to the semiconductor substrate. Meanwhile, a Argon:Helium flow rate of 80>Ar>10 slm, 80>He>10 slm is set for the ambient substrate environment where the ratio of Ar:He ranges from 0:1 to 1:0 by volume or molality.

Abstract: A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an active region of an integrated circuit chip. The crack stop comprises self healing material which, upon propagation of a crack, is structured to seal the crack and prevent further propagation of the crack.

Abstract: A microfabricated device is fabricated by depositing a first metal layer on a substrate to provide a first electrode of an electrostatic actuator, depositing a first structural polymer layer over the first metal layer, depositing a second metal layer over said first structural polymer layer to form a second electrode of the electrostatic actuator, depositing an insulating layer over said first structural polymer layer, planarizing the insulating layer, etching the first structural polymer layer through the insulating layer and the second metal layer to undercut the second metal layer, providing additional pre-formed structural polymer layers, at least one of which has been previously patterned, and finally bonding the additional structural layers in the form of a stack over the planarized second insulating layer to one or more microfluidic channels. The technique can also be used to make cross over channels in devices without electrostatic actuators, in which case the metal layers can be omitted.

Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.

Abstract: A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface.

Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.

Abstract: A hybrid laminated body is provided that includes a light-transmitting support, a latent release layer disposed upon the light-transmitting support, a joining layer disposed upon the latent release layer, and a polyamide thermoplastic priming layer disposed upon the joining layer. The hybrid laminated body can further include a substrate to be processed such as, for example, a silicon wafer to be ground. Also provided is a method for manufacturing the provided laminated body.

Abstract: A surface of a semiconductor wafer is subjected to high flattening processing. A resin application and grinding step is repeatedly carried out, the step including determining as a reference surface a flat surface obtained by applying a curable material to one entire surface of a wafer sliced out from a semiconductor single crystal ingot with the use of a wire saw apparatus and performing surface grinding with respect to the other surface of the wafer, and determining as a reference surface the other surface of the wafer subjected to the surface grinding and performing the surface grinding with respect to the one surface of the wafer.

Abstract: A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer, etching the hard mask layer to form a first and a second hard mask pattern in the first and the second regions, respectively, reducing a width of the second hard mask pattern formed in the second region and etching the etch target layer using the first hard mask pattern and the second hard mask pattern having the reduced width as an etch barrier to form the etch target patterns in the first and the second regions.

Abstract: The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing: a support substrate formed from a material that is at least partially transparent at a determined wavelength; a layer to be separated; and a separation layer interposed between the support substrate and the layer to be separated, the separation layer being adapted to be separated by exfoliation under the action of radiation having a wavelength corresponding to the determined wavelength. Furthermore, the method comprises, during the step for forming the composite step, a treatment step modifying the optical properties in reflection at the interface between the support substrate and the separation layer or on the upper face of the support substrate.

Abstract: A method of manufacturing a composite substrate for a semiconductor device, the method comprising: selecting a substrate wafer comprising: a first layer of single crystal material suitable for epitaxial growth of a compound semiconductor thereon and having a thickness of 100 ?m or less;a second layer having a thickness of no less than 0.5 ?m and formed of a material having a lower thermal expansion coefficient than the first layer of single crystal material and/or is formed of a material which has a higher fracture strength than that of the first layer of single crystal material; and a third layer forming a handling wafer on which the first and second layers are disposed, wherein the substrate wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.

Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.

Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.

Abstract: Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms.

Abstract: A method is provided in which a substrate including various materials of different fracture toughness (KIc) can be spalled in a controlled manner. In particular, a surface step region is formed within a surface portion of the substrate prior to formation of a stressor layer. The presence of the surface step region within the surface portion of the substrate controls the depth and ease at which crack initiation occurs within the substrate.

Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.

Abstract: A method for testing TSVs is provided. A plurality of TSVs is formed in a semiconductor substrate. Wiring layers and a first contact array are formed on the front-side of the substrate. The wiring layers couple each of the TSVs to a respective contact of the first contact array. Conductive adhesive is deposited over the first contact array. The conductive adhesive electrically couples contacts of the first contact array. A carrier is bonded to the front-side of the substrate with the conductive adhesive. After bonding the carrier to the substrate, the back-side of the substrate is thinned to expose each of the TSVs on the back-side of the substrate. A second contact array is formed, having a contact coupled to each respective TSV. Conductivity and connections of the TSVs, wiring layers, and contacts are tested by testing for conductivity between contacts of the second contact array.

Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.

Abstract: A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface.

Abstract: Disclosed are a liquid processing method, a liquid processing apparatus, and a recording medium that can prevent convex portions of a target substrate from collapsing when a rinsing liquid is dried. A base surface of a target substrate is hydrophilized and the surfaces of convex portions become water-repellent by surface-processing the target substrate which includes a main body, a plurality of convex portions protruding from the main body, and a base surface formed between the convex portions on the substrate main body. Next, a rinsing liquid is supplied to the target substrate which has been subjected to the surface processing. Thereafter, the rinsing liquid is removed from the target substrate.

Abstract: A method of manufacturing a thin film device, the method includes: forming a functional film having a predetermined pattern on a surface of a first substrate; covering the surface of the first substrate and the functional film with an insulating film; and transferring the insulating film and the functional film from the first substrate to a second substrate.

Abstract: Provided is a coating method of an alignment film, including: providing a board, having a substrate, the substrate forming an alignment liquid coating area thereon; forming a barrier structure around the alignment liquid coating area; coating an alignment liquid in the alignment liquid coating area, wherein the barrier structure blocks the alignment liquid to diffuse outside the alignment liquid coating area; and curing the alignment liquid to form an alignment film. The present invention may assure that the formed alignment film can not affect other areas adjacent to the alignment liquid coating area.