Abstract: In a wafer processing method, the back side of a wafer having a plurality of devices on the front side thereof is ground, thereby reducing the thickness of the wafer to a predetermined thickness. The back side of the wafer is polished after performing the back grinding step, thereby removing a grinding strain, and a silicon nitride film is formed on the back side of the wafer. The thickness of the silicon nitride film to be formed in the silicon nitride film forming step is set to 6 to 100 nm. Thus, the silicon nitride film having a thickness of 6 to 100 nm is formed on the polished back side of the wafer from which a grinding strain has been removed. Accordingly, each device constituting the wafer can ensure a sufficient die strength and a sufficient gettering effect.

Abstract: Manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. The stress layer may comprise a flexible material.

Abstract: Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.

Abstract: A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface.

Abstract: A microscopic metallic structure is produced by creating or exposing a patterned region of increased conductivity and then forming a conductor on the region using electrodeposition. In some embodiments, a microscopic metallic structure is formed on a substrate, and then the substrate is etched to remove the structure from the substrate. In some embodiments, a focused beam of gallium ion without a deposition precursor gas scans a pattern on a silicon substrate, to produce a conductive pattern on which a copper structure is then formed by electrochemical deposition of one or more metals. The structure can be freed from the substrate by etching, or can used in place. A beam can be used to access an active layer of a transistor, and then a conductor can be electrodeposited to provide a lead for sensing or modifying the transistor operation while it is functioning.

Abstract: In an imprint method according to one embodiment, a template on which a template pattern is formed is pushed against resist on a substrate to be transferred while the resist is cured in this state. The template is subsequently separated from the cured resist. The template is then degassed from the template pattern surface side between after the template is separated from the cured resist and till the template is pushed against resist at the next shot.

Abstract: An integrated circuit is formed by coating a top surface of a wafer that has been processed through all integrated circuit chip manufacturing steps prior to backgrind with photoresist, applying backgrind tape over a top surface of the photoresist, backgrinding a back surface of the wafer to a specified thickness, removing the backgrind tape from the top surface of the photoresist, and removing the photoresist. The surface of the integrated circuit and any devices that may be bonded to the surface of the integrated circuit are protected by the photoresist layer during removal of the backgrind tape.

Abstract: A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate.

Abstract: Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems.

Abstract: Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.

Abstract: A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer.

Abstract: A method for forming a semiconductor device is provided including processing a wafer having a target material; forming a first pattern over the target material; forming a protection layer over the first pattern; and forming a second pattern, over the target material and not over the protection layer, without an etching step between the forming the first pattern and the forming the second pattern.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

Abstract: A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radiofrequency generator applying to the insulator layer a power density greater than 0.6 W/cm2 but less than 10 W/cm2 for at least 10 seconds to less than 200 seconds. Substrate bonding and layer transfer may be carried out subsequently to transfer the thin layer of substrate and the insulator layer to a second substrate.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a liquid on a region of a die, and then forming an identification mark through the liquid on the die.

Abstract: Wafer-based solar cells are efficiently produced by extruding a dopant bearing material (dopant ink) onto one or more predetermined surface areas of a semiconductor wafer, and then thermally treating the wafer to cause diffusion of dopant from the dopant ink into the wafer to form corresponding doped regions. A multi-plenum extrusion head is used to simultaneously extrude interdigitated dopant ink structures having two different dopant types (e.g., n-type dopant ink and p-type dopant ink) in a self-registered arrangement on the wafer surface. The extrusion head is fabricated by laminating multiple sheets of micro-machined silicon that define one or more ink flow passages. A non-doping or lightly doped ink is co-extruded with heavy doped ink to serve as a spacer or barrier, and optionally forms a cap that entirely covers the heavy doped ink. A hybrid thermal treatment utilizes a gaseous dopant to simultaneously dope exposed portions of the wafer.

Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Abstract: An object of the present invention is to provide a method for manufacturing a display device by improving the utilization efficiency of materials and simplifying manufacturing process. Another object of the invention is to provide a technique for forming a pattern such as a wiring having a predetermined shape included in a display device with good controllability. A method for manufacturing a wiring substrate of the invention includes the steps of: forming a first region having a subject material; modifying the surface of the subject material partly to form a second region having a boundary with respect to the first region; continuously discharging a composition containing a conductive material to a part of the first region across the boundary and the second region; solidifying the composition to form a conductive layer; and removing the conductive layer formed in a part of the first region across the boundary.

Abstract: The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to about 95 vol % of a first solvent, wherein the first solvent comprises a cyclic ester. A balance of the mixture comprises a second solvent, wherein the second solvent comprises a volatile organic liquid.

Abstract: Methods for fabricating porous low-k materials are provided, such as plasma enhanced chemically vapor deposited (PE-CVD) and chemically vapor deposited (CVD) low-k films used as dielectric materials in between interconnect structures in semiconductor devices. More specifically, a new method is provided which results in a low-k material with significant improved chemical stability and improved elastic modulus, for a porosity obtained.

Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .

Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus. The method comprise: a first process of forming a film containing a predetermined element on a substrate by supplying a source gas containing the predetermined element to a substrate processing chamber in which the substrate is accommodated; a second process of removing the source gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; a third process of modifying the predetermined element-containing film formed in the first process by supplying a modification gas that reacts with the predetermined element to the substrate processing chamber; a fourth process of removing the modification gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; and a filling process of filling an inert gas in a gas tank connected to the substrate processing chamber.

Abstract: To provide a temporary bonding adhesive for a semiconductor wafer that reduces damage to a semiconductor wafer, makes it readily detachable, and can shorten the time required for thermal decomposition, and a manufacturing method for a semiconductor device using this. A temporary bonding adhesive for a semiconductor wafer, being a temporary bonding adhesive used for temporarily bonding a semiconductor wafer onto a supporting substrate in order to process a semiconductor wafer, and for detaching a semiconductor wafer from a supporting substrate by heating after processing, containing a resin composition composition whereof the 50% weight loss temperature decreases after irradiation by active energy rays.

Abstract: The present invention relates to a method of manufacturing a semiconductor device having a shared contact for connection between a source/drain region and a gate electrode. After formation of a gate electrode via a gate insulating film on a semiconductor substrate, a top surface of the substrate is covered with a cover film. After removal of the cover film from at least one of sidewall surface of the gate electrode and a part of the top surface of the substrate adjacent to the sidewall surface, a semiconductor layer is epitaxially grown on a top surface of an exposed substrate to electrically connect the substrate and the at least one sidewall surface of the gate electrode. Then, a source/drain region is formed in a top surface part of the substrate or the semiconductor layer using the gate electrode as a mask.

Abstract: A material substrate is prepared which has a first surface and a second surface opposite to each other in a thickness direction and is made of silicon carbide. The material substrate is partially carbonized to divide the material substrate into a carbonized portion made of a material obtained by carbonizing silicon carbide, and a silicon carbide portion made of silicon carbide. This step of partially carbonizing the material substrate is performed to partially carbonize the second surface. In order to adjust a shape of the material substrate when viewed in a planar view, a portion of the material substrate is removed. This step of removing the portion of the material substrate includes the step of processing the carbonized portion. Accordingly, a silicon carbide substrate having a desired planar shape can be obtained readily.

Abstract: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property. When the light absorbing layer absorbs energy of the laser beam, due to emission of gas that is within the light absorbing layer, or sublimation, evaporation, or the like of the light absorbing layer, a part of the light absorbing layer and a part of the layer having a light-transmitting property in contact with the light absorbing layer are removed. By using the remaining part of the layer having a light-transmitting property or the remaining part of the light absorbing layer as a mask and etching the first layer, the first layer can be processed into a desired shape.

Abstract: The invention relates to a method for finishing the surface of semiconducting substrate that has a set of layers and a useful semiconducting layer on at least one of the faces of the substrate, wherein the useful layer has a rough free surface. The method smoothes out the rough free surface of the useful layer by creating a protective layer covering the surface of the useful layer with a thickness 1 to 3 times larger than the peak-to-valley distance of the surface of the useful layer, at least one polishing-oxidation sequence that includes the successive steps of polishing the surface of the protective layer, with the polishing being adjusted so as not to attack the useful layer, and performing a thermal oxidation with supply of oxygen gas of the substrate in order to transform a portion of the useful layer into an oxide layer and reduce the roughness of the surface of the useful layer.

Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.

Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.

Abstract: It is an object of the present invention to provide a method for forming a layer having functionality including a conductive layer and a colored layer and a flexible substrate having a layer having functionality with a high yield. Further, it is an object of the present invention to provide a method for manufacturing a semiconductor device that is small-sized, thin, and lightweight. After coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, after attaching an adhesive to the layer having functionality, the layer having functionality is peeled from the substrate. Further, after coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, an adhesive is attached to the layer having functionality. Thereafter, the layer having functionality is peeled from the substrate, and a flexible substrate is attached to the layer having functionality.

Abstract: A method of forming a pattern of an inorganic material film, which method is more versatile, easy, and practical. The method includes the steps of: (a) forming a sacrifice layer having a pattern on a substrate by employing a material having a different thermal expansion coefficient from that of an inorganic material of the inorganic material film; (b) forming an inorganic material layer on the substrate, on which the sacrifice layer has been formed, at a predetermined deposition temperature by employing the inorganic material; (c) lowering a temperature of at least the inorganic material layer to produce cracks in the inorganic material layer formed on the sacrifice layer; and (d) removing the sacrifice layer and the inorganic material layer formed thereon.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of: (1) coating a solution containing an organic semiconductor material on a water-repellent surface of a water-repellent stamp substrate; (2) drying the thus coated organic semiconductor material-containing solution on the water-repellent surface to crystallize the organic semiconductor material in contact with the water-repellent surface, thereby forming a semiconductor layer; (3) thermally treating the semiconductor layer formed on the stamp substrate; and (4) pressing the stamp substrate at a side, in which the thermally treated organic semiconductor layer is formed, against a surface of a substrate to be transferred so that the organic semiconductor layer is transferred to the surface of the substrate to be transferred.

Abstract: In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.

Abstract: A process for forming a patterned thin film structure on a substrate is disclosed. A pattern is printed with a material, such as a masking coating or an ink, on the substrate, the pattern being such that, in one embodiment, the desired thin film structures will be formed in the areas where the printed material is not present, i.e., a negative image of thin film structure to be formed is printed. In another embodiment, the pattern is printed with a material that is difficult to strip from the substrate, and the desired thin film structures will be formed in the areas where the printed material is present, i.e., a positive image of the thin film structure is printed. The thin film material is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned thin film structures.

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.

Abstract: Methods and systems for planarization of a die-to-wafer integration. A planarization coating may be applied to the die-to-wafer assembly, and a planarization plate may be used in the planarization process. The planarization plate may include perforations configured to allow a portion of the planarization coating to extrude through the planarization plate.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.

Abstract: A method for forming a pattern includes the step of forming an electrically conductive film by applying a liquid composition onto a first plate. The liquid composition includes an organic solvent and conductive particles surface-modified with a fatty acid or an aliphatic amine. Then, a second pattern, which is a reverse pattern of a first pattern, is formed on the first plate by pressing a second plate having a concave-convex pattern on a surface thereof on a surface of the first plate having the electrically conductive film on the surface thereof. Then, the first pattern of the electrically conductive film is transferred onto convex top faces of the second plate. Then, the second pattern is transferred onto a surface of a transfer substrate by pressing the surface of the first plate having the second pattern thereon on the surface of the transfer substrate.

Abstract: An electrical device, such as a semiconductor device, and methods of manufacturing the same. A semiconductor device having a shallow trench isolation (STI) layer may include a pad oxide layer formed over a semiconductor substrate, a trench formed over the substrate, a liner insulating layer formed over the trench, a gap-fill insulating layer formed over the liner insulating layer and a gate layer formed over the substrate. The gap-fill insulating layer may have a relatively and/or substantially planar polished surface. Methods of fabricating a semiconductor device having a shallow trench isolation (STI) layer may include performing a first chemical mechanical polishing over a gap-fill insulating layer to expose and/or target a portion of a liner insulating layer and performing a second chemical mechanical polishing over a gap-fill insulating layer to remove a portion of a liner insulating layer.

Abstract: A process for forming a patterned thin film structure on a substrate or in-mold decoration film is disclosed. A pattern is printed with a material, such as a masking coating or ink, on the substrate, the pattern being such that, in one embodiment, the desired structures will be formed in the areas where the printed material is not present, i.e., a negative image of thin film structure to be formed is printed. In another embodiment, the pattern is printed with a material that is difficult to strip from the substrate, and the desired thin film structures will be formed in the areas where the printed material is present, i.e., a positive image of the thin film structure is printed. The thin film material is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned thin film structure.

Abstract: Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design.

Abstract: A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.

Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.

Abstract: A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped SiGe layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron-doped SiGe layer is configured to propagate a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.

Abstract: Wafer-based solar cells are efficiently produced by extruding a dopant bearing material (dopant ink) onto one or more predetermined surface areas of a semiconductor wafer, and then thermally treating the wafer to cause diffusion of dopant from the dopant ink into the wafer to form corresponding doped regions. A multi-plenum extrusion head is used to simultaneously extrude interdigitated dopant ink structures having two different dopant types (e.g., n-type dopant ink and p-type dopant ink) in a self-registered arrangement on the wafer surface. The extrusion head is fabricated by laminating multiple sheets of micro-machined silicon that define one or more ink flow passages. A non-doping or lightly doped ink is co-extruded with heavy doped ink to serve as a spacer or barrier, and optionally forms a cap that entirely covers the heavy doped ink. A hybrid thermal treatment utilizes a gaseous dopant to simultaneously dope exposed portions of the wafer.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.