Abstract: A polishing method includes performing conditioning process of injecting a conditioning agent onto a surface of a non-foam polishing pad arranged on a polishing table at a predetermined pressure, and polishing a surface of a polishing target while supplying a polishing slurry containing oxide particles and a surfactant onto the polishing pad, wherein an average of a residual cerium amount is equal to or smaller than 0.35 at % when a plurality of measurement regions, each 200 ?m? in area including the surface of the polishing pad, in a cross section of the polishing pad are measured after the conditioning process.

Abstract: A method and system for treating a dielectric film on a plurality of substrates includes disposing the plurality of substrates in a batch processing system, the dielectric film on the plurality of substrates having a dielectric constant value less than the dielectric constant of SiO2. The plurality of substrates are heated, and a treating compound comprising a CxHy containing compound, wherein x and y represent integers greater than or equal to unity is introduced to the process system. A plasma is formed and at least one surface of the dielectric film on said plurality of substrates is exposed to the plasma.

Abstract: A chip package structure is provided, includes a chip that having a plurality of pads and an adhesive layer on the back side; an encapsulated structure is covered around the four sides of the chip to expose the pads, and the through holes is formed within the encapsulated structure; a patterned first protective layer is formed on the portion surface of encapsulated structure, the portion of active surface of the chips, and the pads of the chip and the through holes are to be exposed; a metal layer is formed on the portion surface of the patterned first protective layer and formed to electrically connect the pads and to fill with the through holes; the patterned second protective layer is formed on the patterned first protective layer and the portion of metal layer, and the portion surface of metal layer is to be exposed; a patterned UBM layer is formed on the exposed surface of the metal layer and the portion surface of the patterned second protective layer; and the conductive elements is formed on the patter

Abstract: Methods and systems are provided for low pressure baking to remove impurities from a semiconductor surface prior to deposition. Advantageously, the short, low temperature processes consume only a small portion of the thermal budget, while still proving effective at removing interfacial oxygen from the semiconductor surface. The methods and systems are particularly well suited for treating semiconductor surfaces before epitaxy.

Abstract: A method is provided for producing a porogen-residue-free ultra low-k film with porosity higher than 50% and a high elastic modulus above 5 GPa. The method starts with depositing a SiCOH film using Plasma Enhanced Chemical Vapor Deposition (PE-CVD) or Chemical Vapor Deposition (CVD) onto a substrate and then first Performing an atomic hydrogen treatment at elevated wafer temperature in the range of 200° C. up to 350° C. to remove all the porogens and then performing a UV assisted thermal curing step.

Abstract: A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.

Abstract: An apparatus for efficiently collecting reaction by-products in exhaust gases of a semiconductor processing or flat panel display processing device is provided. The collection apparatus includes a heating section connected to a process chamber of the semiconductor processing or flat panel display processing device. The heating section is designed to preheat the reaction by-products to prevent or reduce liquefaction of the reaction by-products. A by-product pile up section then rapidly cools the heated reaction by-products to convert the same into a solid form.

Abstract: A semiconductor chip has devices formed on a first principal plane of a semiconductor substrate, wherein a second principal plane of the semiconductor substrate is planarized, and an organic film having plus charges on an outer side is provided on the second principal plane.

Abstract: A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane.

Abstract: To provide a manufacturing apparatus of a semiconductor device, which does not use a stepper in a manufacturing process in the case where mass production of semiconductor devices is carried out by using a large-sized substrate. A thin film formed over a substrate having an insulating surface is selectively irradiated with a laser beam through light control means, specifically through an electro-optical device to cause ablation; accordingly, the thin film is partially removed, thereby processing the thin film in a remaining region into a desired shape. The electro-optical device functions as a variable mask by inputting an electrical signal based on design CAD data of the semiconductor device.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.

Abstract: A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.

Abstract: A method of fabricating an array substrate for a liquid crystal display device comprises forming a gate line, a data line that crosses the gate line and a thin film transistor connected to the gate line and the data line on a substrate, and forming an organic insulating material layer on the gate line, the data line and the thin film transistor. The organic insulating material layer has photo curability, flexibility and dynamic stability. The method further comprises forming a passivation layer that has a drain contact hole from the organic insulating material layer by using a stamp that has a convex portion. The drain contact hole exposes a drain electrode of the thin film transistor. The method also comprises forming a pixel electrode on the passivation layer. The pixel electrode is connected to the drain electrode through the drain contact hole.

Abstract: A resist pattern processing apparatus comprises a stage for mounting a substrate having a patterned photoresist arranged on a surface thereof, a UV-emitting part for emitting UV rays to the stage, and an annular member for surrounding the whole periphery of the substrate. This allows the annular member to restrain ozone supplied near a mounting surface for the substrate on the stage from diffusing to the periphery of the stage, whereby the ozone concentration becomes even in the surface of the substrate mounted on the stage.

Abstract: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property. When the light absorbing layer absorbs energy of the laser beam, due to emission of gas that is within the light absorbing layer, or sublimation, evaporation, or the like of the light absorbing layer, a part of the light absorbing layer and a part of the layer having a light-transmitting property in contact with the light absorbing layer are removed. By using the remaining part of the layer having a light-transmitting property or the remaining part of the light absorbing layer as a mask and etching the first layer, the first layer can be processed into a desired shape.

Abstract: An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.

Abstract: A method of manufacturing an IC device includes providing a workpiece having least one dielectric layer disposed on a surface of the workpiece. The method also includes processing the dielectric layer to form a plurality of apertures in the dielectric layer, where the processing includes at least one micromask-prone process. The method further includes subsequent to the processing step, cryogenically treating the workpiece. In the method, the treating step removes particles deposited on or in the plurality of apertures during the processing step and maintains the plurality of apertures, where the particles are generated from micromask features resulting from the micromask-prone process.

Abstract: Disclosed are methods of making fine patterns by exploiting difference in threshold laser fluence of materials and a thin film transistor (TFT) fabrication methods using the same, and more particularly, to a method of forming a fine pattern and a method of fabricating a TFT through the same method, in which a plurality of layers different in threshold laser fluence are stacked and then exposed to a laser so that a layer having a low threshold laser fluence can be selectively removed, thereby making fine patterns precisely and forming a cavity of a gate electrode precisely and easily.

Abstract: It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Abstract: A method of forming an integrated circuit structure includes forming an opening in a substrate, with the opening extending from a top surface of the substrate into the substrate. The opening is filled with a filling material until a top surface of the filling material is substantially level with the top surface of the substrate. A device is formed over the top surface of the substrate, wherein the device includes a storage opening adjoining the filling material. A backside of the substrate is grinded until the filling material is exposed. The filling material is removed from the channel until the storage opening of the device is exposed.

Abstract: The present invention relates to a high-power semiconductor laser having low divergence and low astigmatism, this laser being including, in an active layer, a first part in the form of a narrow monomode stripe with transverse index guiding terminating in a second part flaring out from the first part, also with transverse index guiding.

Abstract: Provided are a unit for supplying chemical liquid, and apparatus and method for treating a substrate using the unit. A pre-wet, photoresist, and edge bead removal nozzles are mounted on a single nozzle body. Therefore, the equipment installing space can be saved as compared with a case where the nozzles are installed on respective nozzle arms, thereby making better use of a space for installing equipments.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: A manufacturing method of a semiconductor device of which cost can be suppressed by using a nanoimprinting method is provided. In the invention, a gate insulating film, a conductive film, and a resist are formed in sequence over a semiconductor film and a resist is hardened while pressing a mold formed with a pattern to the resist. Therefore, the pattern is transferred to the resist, the surface of the resist to which the pattern is transferred is ashed until a part of the conductive film is exposed, the resist having the ashed surface is used a mask, and the conductive film is etched.

Abstract: A semiconductor device includes a substrate, a semiconductor device structure over the substrate, an insulating film that covers the semiconductor device structure, and a stress-compensation film over the insulating film. The stress-compensation film has a first stress that compensates a second stress working to bend the substrate.

Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

Abstract: An interlayer insulating film is formed on a semiconductor substrate having a semiconductor element formed thereon. At this time, there are protrusions higher than surroundings thereof and non-protruding portions lower than the protrusions on the surface of the interlayer insulating film. First, a first polishing process is carried out on the surface of the interlayer insulating film with use of a first abrasive having non-Prestonian properties produced by mixing abrasive materials including abrasive grains, a polymer additive and water at a predetermined first mixture ratio. Then, after the first abrasive process shifts to an automatically stopping state, a second polishing process is carried out on the surface of the interlayer insulating film with use of a second abrasive having the concentration of polymer additive lower than that of the first abrasive and produced by mixing the abrasive materials at a second mixture ratio different from the first mixture ratio.

Abstract: A Cl2 gas plasma is generated at a site within a chamber between a substrate and a metal member. The metal member is etched with the Cl2 gas plasma to form a precursor. A nitrogen gas is excited in a manner isolated from the chamber accommodating the substrate. A metal nitride is formed upon reaction between excited nitrogen and the precursor, and formed as a film on the substrate. After film formation of the metal nitride, a metal component of the precursor is formed as a film on the metal nitride on the substrate. In this manner, a barrier metal film with excellent burial properties and a very small thickness is produced at a high speed, with diffusion of metal being suppressed and adhesion to the metal being improved.

Abstract: Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer, and a central opening that exposes a central active area of the wafer. The extrusion head is then moved relative to the wafer, and the extrusion material is continuously extruded through outlet orifices of the extrusion head to form elongated extruded structures on the active area of the wafer. The mask prevents deposition of the extrusion material along the peripheral edges of the wafer, and facilitates the formation of unbroken extrusion structures. The mask may be provided with a non-rectangular opening to facilitate the formation of non-rectangular (e.g., circular) two-dimensional extrusion patterns.

Abstract: A method of treating the surface of a semiconductor substrate has cleaning the semiconductor substrate having a pattern formed thereon by using a chemical solution, removing the chemical solution by using pure water, forming a water repellent protective film on the surface of the semiconductor substrate, rinsing the semiconductor substrate by using pure water, and drying the semiconductor substrate.

Abstract: It is an object of the present invention to provide a method for forming a layer having functionality including a conductive layer and a colored layer and a flexible substrate having a layer having functionality with a high yield. Further, it is an object of the present invention to provide a method for manufacturing a semiconductor device that is small-sized, thin, and lightweight. After coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, after attaching an adhesive to the layer having functionality, the layer having functionality is peeled from the substrate. Further, after coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, an adhesive is attached to the layer having functionality. Thereafter, the layer having functionality is peeled from the substrate, and a flexible substrate is attached to the layer having functionality.

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.

Abstract: A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 ?m and equal to or less than 10 ?m is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 ?m and equal to or less than 10 ?m to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.

Abstract: A dielectric cap layer of a sophisticated metallization system may be provided in a locally restricted manner so as to enable direct contact of the dielectric material of one metallization layer with a low-k dielectric material of a subsequent metallization layer, which may thus provide enhanced adhesion and overall mechanical integrity.

Abstract: A method (and semiconductor device) of forming a high shrinkage stressed silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in a stress management technique (SMT) provides increased tensile stress to a channel of an nFET device to enhance carrier mobility. A spin-on polysilazane-based dielectric material is applied to a semiconductor substrate and baked to form a film layer. The film layer is cured to remove hydrogen from the film which causes shrinkage in the film when it recrystallizes into silicon nitride. The resulting silicon nitride stressed layer introduces an increased level of tensile stress to the transistor channel region.

Abstract: Embodiments in accordance with the present invention relate to multi-stage curing processes for chemical vapor deposited low K materials. In certain embodiments, a combination of electron beam irradiation and thermal exposure steps may be employed to control selective outgassing of porogens incorporated into the film, resulting in the formation of nanopores. In accordance with one specific embodiment, a low K layer resulting from reaction between a silicon-containing component and a non-silicon containing component featuring labile groups, may be cured by the initial application of thermal energy, followed by the application of radiation in the form of an electron beam.

Abstract: A method for forming an internal electrode pattern having a predetermined shape includes the following: a step of forming a conductive layer by applying a metal paste on a first support, the metal paste containing metal powder and a binder; a step of forming a resin layer on a second support, the resin layer having a pattern negative to the internal electrode pattern; a step of compression bonding the first support and the second support to each other in such a manner that the conductive layer and the resin layer are opposite to each other; and a step of removing the second support from the first support so as to transfer a conductive layer to the second support, the conductive layer having the pattern negative to the internal electrode pattern, thereby forming the internal electrode pattern having the predetermined shape on the first support.

Abstract: A method of preparing a porous dielectric film on a substrate is described. The method comprises exposing the porous dielectric film to infrared (IR) radiation, while not exposing the porous dielectric film to any ultraviolet (UV) radiation preceding, during and following the IR exposure.

Abstract: Broadly speaking, the present invention provides a method and an apparatus for planarizing a semiconductor wafer (“wafer”). More specifically, the present invention provides for depositing a planarizing layer over the wafer, wherein the planarizing layer serves to fill recessed areas present on a surface of the wafer. A planar member is positioned over and proximate to a top surface of the wafer. Positioning of the planar member serves to entrap electroless plating solution between the planar member and the wafer surface. Radiant energy is applied to the wafer surface to cause a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase in turn causes plating reactions to occur at the wafer surface. Material deposited through the plating reactions forms a planarizing layer that conforms to a planarity of the planar member.

Abstract: Disclosed is a method for manufacturing an optoelectronic semiconductor device having a p-n junction diode, which includes the steps of: (a) etching at least one surface of the p-n junction diode in a depth direction to form a plurality of continuous, isolated or mixed type electrode pattern grooves with a certain array; and (b) filling the formed grooves with a conductive ink containing a transparent conducting particle through an inkjet and then performing heat treatment to form a buried transparent electrode, the optoelectronic semiconductor device, and an apparatus for manufacturing the optoelectronic semiconductor device. In the present invention, covering loss is significantly reduced due to a buried transparent electrode so that the high efficiency of photoelectric conversion can be implemented, and there can be provided the easiness of a manufacturing process and the enhancement of productivity through the unification of etching and electrode forming processes.

Abstract: There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the first interlayer insulating layer. A plurality of sidewall buffer patterns are formed on the first interlayer insulating layer having the via plug, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. The sidewall layer is deposited on the first interlayer insulating layer and the sidewall buffer patterns. The sidewall layer is etched such that sidewall patterns remains on sidewalls of the sidewall buffer patterns.

Abstract: In a manufacturing method for a semiconductor device, a first impurity diffusion layer for a low impurity concentration drain of a second conductivity type is formed within a semiconductor layer of a first conductivity type, and a second impurity diffusion layer for a high impurity concentration drain of the second conductivity type is formed adjacent to the first impurity diffusion layer, with the second impurity diffusion layer having a higher impurity concentration than the first impurity diffusion layer. An interlayer insulating film is formed on the semiconductor substrate layer. A drain extension region having a high thermal conductivity is formed on a surface of the first impurity diffusion layer. A contact hole is formed through the interlayer insulating film and up to the second impurity diffusion layer.

Abstract: A method of forming an organic semiconductor pattern is provided. A pattern is formed on a first substrate. An adhesive is coated on the pattern to form an adhesive pattern. An organic semiconductor layer is formed on a second substrate. The second substrate is combined with the first substrate to remove a portion of the organic semiconductor layer attached to the pattern from the second substrate to form the organic semiconductor pattern.

Abstract: There is provided a cleaning method and production method that suppresses the adhesion of foreign matters including impurity, fine particles and the like on a surface of a compound semiconductor. A method of cleaning a nitride-based compound semiconductor in accordance with the present invention includes the steps of: preparing a nitride-based compound semiconductor (or a substrate preparation step); and cleaning. In the step of cleaning, a cleaning liquid having a pH of 7.1 or higher is used to clean the nitride-based compound semiconductor.

Abstract: The present invention provides processes for producing horizontal nanowires that are separate and oriented and allow for processing directly on a substrate material. The nanowires grow horizontally by suppressing vertical growth from a nucleating particle, such as a metal film. The present invention also provides for horizontal nanowire growth from nucleating particles on the edges of nanometer-sized steps. Following processing, the nanowires can be removed from the substrate and transferred to other substrates. The present invention also provides for nanowires produced by these processes and electronic devices comprising these nanowires. The present invention also provides for nanowire growth apparatus that provide horizontal nanowires, and processes for producing nanowire devices.

Abstract: The invention concerns a method of producing at least one mechanical component of a MEMS or NEMS structure from a monocrystalline silicon substrate, comprising the steps of: forming anchoring zones in one face of the substrate to delimit the mechanical component, forming, on the face of the substrate, a lower protective layer made of material other than silicon and obtained by epitaxy from the face of the substrate, forming, on the lower protective layer, a silicon layer obtained by epitaxy from the lower protective layer, forming an upper protective layer on the silicon layer, etching the upper protective layer, the silicon layer and the lower protective layer, according to a pattern defining the mechanical component, until the substrate is reached and to provide access routes to the substrate, forming a protective layer on the walls formed by the etching of the pattern of the mechanical component in the epitaxied silicon layer, releasing the mechanical component by isotropic etching of the substrate from

Abstract: An object is to provide a semiconductor device including a microcrystalline semiconductor film with favorable quality and a method for manufacturing the semiconductor device. In a thin film transistor formed using a microcrystalline semiconductor film, yttria-stabilized zirconia having a fluorite structure is formed in the uppermost layer of a gate insulating film in order to improve quality of a microcrystalline semiconductor film to be formed in the initial stage of deposition. The microcrystalline semiconductor film is deposited on the yttria-stabilized zirconia, so that the microcrystalline semiconductor film around an interface with a base particularly has favorable crystallinity while by crystallinity of the base.

Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.

Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having an improved structure in which optical extraction efficiency is improved. The method of manufacturing a nitride-based semiconductor light-emitting device including an n-doped semiconductor layer, an active layer, a p-doped semiconductor layer, an n-electrode and a p-electrode includes: forming an azobenzene-functionalized polymer film on a base layer by selecting one layer from the group consisting of the n-doped semiconductor layer, the p-doped semiconductor layer, the n-electrode and the p-electrode as the base layer; forming surface relief gratings of a micro-pattern caused by a photophysical mass transport property of azobenzene-functionalized polymer by irradiating interference laser beams onto the azobenzene-functionalized polymer film; forming a photonic crystal layer using a metal oxide on a recessed gap of the azobenzene-functionalized polymer film, and removing the azobenzene-functionalized polymer film.