Subsequent Heating Modifying Organic Coating Composition Patents (Class 438/781)
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Patent number: 7855121Abstract: Provided are a method of forming an organic semiconductor thin film and a method of manufacturing a semiconductor device using the. According to example embodiments, a method of forming an organic semiconductor thin film at least may include exposing a lower substrate coated with an organic semiconductor solution using a method of generating a shearing stress to the portion of the lower substrate coated with the organic semiconductor solution. A guide structure may be formed adjacent to the organic semiconductor solution.Type: GrantFiled: March 27, 2009Date of Patent: December 21, 2010Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Laland Stanford Junior UniversityInventors: Do Hwan Kim, Sangyoon Lee, Hector Alejandro Becerril Garcia, Mark Roberts, Zhenan Bao, Zihong Liu
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Patent number: 7825042Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.Type: GrantFiled: December 10, 2009Date of Patent: November 2, 2010Assignee: Applied Materials, Inc.Inventor: Robert P. Mandal
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Patent number: 7820550Abstract: A method of forming a pattern on a wafer is provided. The method includes applying a photoresist on the wafer and exposing the wafer to define a first pattern on the photoresist. The method also includes exposing the wafer to define a second pattern on the photoresist, wherein each of the first and second patterns comprises unexposed portions of the photoresist and developing the wafer to form the first and second patterns on the photoresist, wherein the first and second patterns are formed by removing the unexposed portions of the photoresist.Type: GrantFiled: September 5, 2008Date of Patent: October 26, 2010Assignee: Intel CorporationInventors: Paul Nyhus, Charles Wallace, Swaminathan Sivakumar
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Patent number: 7820777Abstract: A composition comprising: a polymerized substance of a compound (I) that contains m numbers of RSi(O0.5)3 units, wherein m represents an integer of from 8 to 16; and R's each independently represents a non-hydrolysable group, provided that at least two among R's represent groups containing a vinyl group or an ethynyl group, and wherein each one of the RSi(O0.5)3 units is connected to another one of the RSi(O0.5)3 units by sharing an oxygen atom in each one of the RSi(O0.5)3 units, so as to form a cage structure, and wherein within a solid component contained in the composition, a polymerized substance formed by a reaction of the compound (I) represents 60 mass % or more.Type: GrantFiled: September 5, 2006Date of Patent: October 26, 2010Assignee: FUJIFILM CorporationInventors: Kensuke Morita, Koji Wariishi, Kazutaka Takahashi, Makoto Muramatsu
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Patent number: 7816276Abstract: In the present invention, a plurality of heat treatment plates are provided side by side in a linear form on a base of a heat treatment apparatus in a coating and developing treatment system. In the heat treatment apparatus, three transfer member groups are provided which transfer a substrate in zones between adjacent heat treatment plates. At the time when performing a pre-baking treatment in the heat treatment apparatus, the substrate is transferred in order to the heat treatment plates at the same temperature, whereby the heat treatment is dividedly performed on the heat treatment plates. According to the present invention, substrates are subjected to heat treatment along the same route, so that the thermal histories are made uniform among the substrates.Type: GrantFiled: January 26, 2007Date of Patent: October 19, 2010Assignee: Tokyo Electron LimitedInventors: Takahisa Otsuka, Tsuyoshi Shibata
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Patent number: 7807219Abstract: A process of repairing a plasma etched low-k dielectric material having surface-bound silanol groups includes exposing at least one surface of the dielectric material to (a) a catalyst so as to form hydrogen bonds between the catalyst and the surface-bound silanol groups obtaining a catalytic intermediary that reacts with the silane capping agent so as to form surface-bound silane compounds, or (b) a solution comprising a supercritical solvent, a catalyst, and a silane capping agent so as to form hydrogen bonds between a catalyst and the surface-bound silanol groups obtaining a catalytic intermediary that reacts with the silane capping agent so as to form surface-bound silane compounds. Horizontal networks can be formed between adjacent surface-bound silane compounds.Type: GrantFiled: June 27, 2006Date of Patent: October 5, 2010Assignee: Lam Research CorporationInventor: James DeYoung
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Patent number: 7803719Abstract: A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated.Type: GrantFiled: February 24, 2006Date of Patent: September 28, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Janos Farkas, Maria Luisa Calvo-Munoz, Srdjan Kordic
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Patent number: 7799705Abstract: Methods of preparing a low stress porous low-k dielectric material on a substrate are provided. The methods involve the use of a structure former precursor and/or porogen precursor with one or more organic functional groups. In some cases, the structure former precursor has carbon-carbon double or triple bonds. In other cases, one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. In other cases, the structure former precursor has carbon-carbon double or triple bonds and one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. Once the precursor film is formed, the porogen is removed, leaving a porous low-k dielectric matrix with high mechanical strength. Different types of structure former precursors and porogen precursors are described. The resulting low stress low-k porous film may be used as a low-k dielectric film in integrated circuit manufacturing applications.Type: GrantFiled: January 5, 2009Date of Patent: September 21, 2010Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, Haiying Fu, David C. Smith, David Mordo
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Patent number: 7793611Abstract: An apparatus for depositing a solid film onto a substrate from a reagent solution includes a reservoir of solution maintained at a low temperature to inhibit homogeneous reactions. The solution contains multiple ligands to control temperature stability and shelf life. The chilled solution is periodically dispensed onto a substrate positioned in a holder having a raised peripheral structure that retains a controlled volume of solution over the substrate. The solution is periodically replenished so that only the part of the solution directly adjacent to the substrate is heated. A heater maintains the substrate at an elevated temperature at which the deposition of a desired solid phase from the solution may be initiated. The apparatus may also dispense excess chilled solution to cool various components within the apparatus and minimize nucleation of solids in areas other than on the substrate. The apparatus is particularly suited to forming films of II-VI semiconductors.Type: GrantFiled: January 12, 2010Date of Patent: September 14, 2010Assignee: Sisom Thin Films LLCInventor: Isaiah O. Oladeji
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Patent number: 7786022Abstract: In the invention, a silica sol prepared by hydrolyzing and condensing a silane compound represented by the following formula: Si(OR1)4 or R2nSi(OR3)4-n wherein R1s, R2(s) and R3(s) may be the same or different when a plurality of them are contained in the molecule and each independently represents a linear or branched C1-4 alkyl group in the presence of a hydrophilic basic catalyst and a hydrophobic basic catalyst is used for a conventional porous-film forming composition.Type: GrantFiled: February 12, 2008Date of Patent: August 31, 2010Assignees: Shin-Etsu Chemical Co., Ltd., Matsushita Electric Industrial Co., Ltd.Inventors: Yoshitaka Hamada, Fujio Yagihashi, Takeshi Asano, Hideo Nakagawa, Masaru Sasago
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Patent number: 7776689Abstract: A method of fabricating a semiconductor device including depositing a first silicon oxide film on a silicon substrate, depositing a silicon-containing film on the first silicon oxide film, applying a coating solution for silica film formation over the silicon-containing film, and heat-treating the coating solution, thereby forming a second silicon oxide film.Type: GrantFiled: August 21, 2008Date of Patent: August 17, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyasu Shiba, Jota Fukuhara
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Patent number: 7767592Abstract: A method for forming a mask pattern for ion-implantation comprises: forming a gate line pattern over a semiconductor substrate; forming a coating layer on the surface of gate line pattern; performing a plasma treatment on the top portion of the gate line pattern; forming a photoresist layer over the resulting structure; and performing an exposure and a developing processes to form a photoresist pattern on the gate line pattern.Type: GrantFiled: May 10, 2006Date of Patent: August 3, 2010Assignee: Hynix Semiconductor Inc.Inventor: Kyu Sung Kim
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Patent number: 7763482Abstract: A method of fabricating an array substrate for a liquid crystal display device comprises forming a gate line, a data line that crosses the gate line and a thin film transistor connected to the gate line and the data line on a substrate, and forming an organic insulating material layer on the gate line, the data line and the thin film transistor. The organic insulating material layer has photo curability, flexibility and dynamic stability. The method further comprises forming a passivation layer that has a drain contact hole from the organic insulating material layer by using a stamp that has a convex portion. The drain contact hole exposes a drain electrode of the thin film transistor. The method also comprises forming a pixel electrode on the passivation layer. The pixel electrode is connected to the drain electrode through the drain contact hole.Type: GrantFiled: December 31, 2007Date of Patent: July 27, 2010Assignee: LG. Display Co., Ltd.Inventor: Jin-Wuk Kim
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Publication number: 20100184268Abstract: A coating composition for forming an oxide film, which can suppress the phenomenon of an increased wet etching rate caused by a part of the SOG film embedded inside a groove becoming low-density, and which can suppress the volume expansion coefficient to a low level, and a method for producing a semiconductor device using the same are provided. An oxide film is formed inside a groove by: coating a coating composition for forming an oxide film, which contains a polysilazane or a hydrogenated silsesquioxane, and a polysilane, on a substrate having a groove; and thereafter heat treatment in an oxidizing atmosphere. This method is suitable for forming a device isolation region and a wiring interlayer dielectric film.Type: ApplicationFiled: March 30, 2010Publication date: July 22, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Toshiyuki HIROTA
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Patent number: 7754510Abstract: A process for fabricating an electronic device including: depositing a layer comprising a semiconductor; liquid depositing a dielectric composition comprising a lower-k dielectric material, a higher-k dielectric material, and a liquid, wherein the lower-k dielectric material and the higher-k dielectric material are not phase separated prior to the liquid depositing; and causing phase separation of the lower-k dielectric material and the higher-k dielectric material to form a phase-separated dielectric structure wherein the lower-k dielectric material is in a higher concentration than the higher-k dielectric material in a region of the dielectric structure closest to the layer comprising the semiconductor, wherein the depositing the layer comprising the semiconductor is prior to the liquid depositing the dielectric composition or subsequent to the causing phase separation.Type: GrantFiled: April 2, 2007Date of Patent: July 13, 2010Assignee: Xerox CorporationInventors: Yiliang Wu, Hadi K Mahabadi, Beng S Ong, Paul F Smith
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Publication number: 20100173470Abstract: In a method of forming a silicon oxide layer, a spin-on-glass (SOG) layer may be formed on an object including a recess using an SOG composition. The SOG layer may be pre-baked and then cured by contacting with at least one material selected from the group consisting of water, a basic material and an oxidant, under a pressure of from about 1.5 atm to about 100 atm. The cured SOG layer may be baked.Type: ApplicationFiled: January 8, 2010Publication date: July 8, 2010Inventors: Mong-Sup Lee, In-Seak Hwang, Keum-Joo Lee, Jin-Hye Bae, Bo-Wo Choi, Seung-Jae Lee
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Patent number: 7745347Abstract: An experiment is conducted in advance, for finding a temperature of a cooling plate attained as a result of balancing between a temperature of a substrate after heat treatment and a temperature of the cooling plate at the time of cooling of the substrate. Then, before heat treatment of a first substrate, the cooling plate is moved to a position above a hot plate, the cooling plate is heated to that temperature, and thereafter heat treatment of the substrate is started.Type: GrantFiled: April 12, 2007Date of Patent: June 29, 2010Assignee: Tokyo Electron LimitedInventors: Hikaru Ito, Shinji Okada, Masami Yamashita
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Patent number: 7728065Abstract: To provide a material for forming an exposure light-blocking film which includes at least one of a silicon compound expressed by the following structural formula (1) and a silicon compound expressed by the following structural formula (2), wherein at least one of R1 and R2 is replaced by a substituent capable of absorbing exposure light.Type: GrantFiled: June 30, 2006Date of Patent: June 1, 2010Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Yoshihiro Nakata
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Patent number: 7723226Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.Type: GrantFiled: January 17, 2007Date of Patent: May 25, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yung-Cheng Lu, Pei-Ren Jeng, Chia-Cheng Chou, Keng-Chu Lin, Chung-Chi Ko, Tien-I Bao, Shwang-Ming Jeng
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Patent number: 7718521Abstract: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.Type: GrantFiled: June 5, 2008Date of Patent: May 18, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Akira Nishiyama, Yoshinori Tsuchiya, Reika Ichihara
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Patent number: 7713885Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.Type: GrantFiled: May 11, 2005Date of Patent: May 11, 2010Assignee: Micron Technology, Inc.Inventors: Niraj B. Rana, Kevin R. Shea, Janos Fucsko
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Publication number: 20100109054Abstract: Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.Type: ApplicationFiled: December 31, 2009Publication date: May 6, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Shang-Wen Chang
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Patent number: 7709298Abstract: A method for selectively altering a predetermined portion of an object or an external member in contact with the predetermined portion of the object is disclosed. The method includes selectively electrically addressing the predetermined portion, thereby locally resistive heating the predetermined portion, and exposing the object, including the predetermined portion, to the external member.Type: GrantFiled: July 18, 2007Date of Patent: May 4, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventor: Zhiyong Li
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Patent number: 7709383Abstract: A film forming method comprising forming a liquid coating film on a substrate by supplying a liquid containing a coating type thin film forming substance and a solvent onto the substrate, substantially converging a variation in film thickness of the coating film, making the coating film stand by in an atmosphere including moisture under a predetermined condition after the substantial-convergence, the predetermined condition being such that a product of a time for which the coating film is exposed to the atmosphere and a water content per unit volume in an atmosphere in the vicinity of a surface of the coating film is made to be greater than or equal to a predetermined value, and forming a solid thin film on the substrate after the stand-by, the thin film being formed by carrying out an elimination of the solvent in the coating film and heat treatment for generating an irreversible reaction to the coating type thin film forming substance in the coating film.Type: GrantFiled: January 14, 2005Date of Patent: May 4, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hirokazu Kato, Tomoyuki Takeishi, Shinichi Ito
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Patent number: 7700161Abstract: An apparatus for depositing a solid film onto a substrate from a reagent solution includes a reservoir of reagent solution maintained at a sufficiently low temperature to inhibit homogeneous reactions within the reagent solution. The reagent solution contains multiple ligands to further control temperature stability and shelf life. The chilled solution is dispensed through a showerhead onto a substrate. The substrate is positioned in a holder that has a raised structure peripheral to the substrate to retain or impound a controlled volume (or depth) of reagent solution over the exposed surface of the substrate. The reagent solution is periodically or continuously replenished from the showerhead so that only the part of the solution directly adjacent to the substrate is heated. A heater is disposed beneath the substrate and maintains the substrate at an elevated temperature at which the deposition of a desired solid phase from the reagent solution may be initiated.Type: GrantFiled: May 7, 2008Date of Patent: April 20, 2010Assignee: Sisom Thin Films LLCInventor: Isaiah O. Oladeji
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Publication number: 20100090302Abstract: A method of making a resonator, preferably a nano-resonator, includes starting with a FINFET structure with a central bar, first and second electrodes connected to the central bar, and third and fourth electrodes on either side of the central bar and separated from the central bar by gate dielectric. The structure is formed on a buried oxide layer. The gate dielectric and buried oxide layer are then selectively etched away to provide a nano-resonator structure with a resonator element 30, a pair of resonator electrodes (32,34), a control electrode (36) and a sensing electrode (38).Type: ApplicationFiled: October 5, 2007Publication date: April 15, 2010Applicant: NXP, B.V.Inventors: Viet Nguyen Hoang, Dirk Gravesteijn, Radu Surdeanu
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Publication number: 20100093174Abstract: A dielectric film, a method of manufacturing a dielectric film and a method of forming an air-gap. A method of manufacturing a low-k dielectric film may include introducing TMS and 3,3-dimethyl-1-butene into a plasma deposition reactor, polymerizing TMS and 3,3-dimethyl-1-butene using plasma generated in a reactor to deposit an insulation film over a substrate disposed in a reactor and/or subjecting a deposited insulation film to heat treatment concurrently with an inductively coupled plasma (ICP) process. A dielectric film may have a dielectric constant up to approximately 3. A method of forming an air-gap may include depositing a first insulation film over a surface of a patterned substrate, depositing a decahydronaphthalene layer over a portion of a first insulation film, subjecting a patterned substrate to a polishing process, forming a second insulation film, and/or subjecting a second insulation film to heat treatment concurrently with an ICP process.Type: ApplicationFiled: September 24, 2009Publication date: April 15, 2010Inventor: Jae-Young Yang
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Patent number: 7695981Abstract: A seed layer is formed on a substrate using a first biological agent. The seed layer may comprise densified nanoparticles which are bound to the biological agent. The seed layer is then used for a deposition of a metal layer, such as a barrier layer, an interconnect layer, a cap layer and/or a bus line for a solid state device.Type: GrantFiled: May 15, 2006Date of Patent: April 13, 2010Assignee: Siluria Technologies, Inc.Inventors: Haixia Dai, Khashayar Pakbaz, Michael Spaid, Theo Nikiforov
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Patent number: 7691756Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.Type: GrantFiled: September 1, 2006Date of Patent: April 6, 2010Assignee: NXP B.V.Inventors: Janos Farkas, Srdjan Kordic, Cindy Goldberg
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Patent number: 7691433Abstract: The invention relates to a method for a structured application of molecules on a strip conductor and to a molecular memory matrix. The inventive method makes it possible, for the first time, to economically and simply apply any number of molecular memory elements on the strip conductor in a structured and targeted way, thereby making available, also for the first time, a memory matrix at a molecular level.Type: GrantFiled: November 30, 2005Date of Patent: April 6, 2010Assignee: Forschungszentrum Julich GmbHInventors: Stephan Kronholz, Silvia Karthäuser
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Publication number: 20100081291Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.Type: ApplicationFiled: December 10, 2009Publication date: April 1, 2010Applicant: APPLIED MATERIALS, INC.Inventor: Robert P. Mandal
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Patent number: 7687406Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.Type: GrantFiled: July 17, 2006Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventors: Jon Daley, Yoshiki Hishiro
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Patent number: 7678712Abstract: The invention concerns a method for applying a surface modification agent composition for organosilicate glass dielectric films. More particularly, the invention pertains to a method for treating a silicate or organosilicate dielectric film on a substrate, which film either comprises silanol moieties or has had at least some previously present carbon containing moieties removed therefrom. The treatment adds carbon containing moieties to the film and/or seals surface pores of the film, when the film is porous.Type: GrantFiled: March 22, 2005Date of Patent: March 16, 2010Assignee: Honeywell International, Inc.Inventors: Anil S. Bhanap, Robert R. Roth, Kikue S. Burnham, Brian J. Daniels, Denis H. Endisch, Ilan Golecki
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Patent number: 7659357Abstract: The silica film forming material of the present invention comprises a silicone polymer which comprises, as part of its structure, CHx, an Si—O—Si bond, an Si—CH3 bond and an Si—CHx- bond, where x represents an integer of 0 to 2.Type: GrantFiled: November 16, 2005Date of Patent: February 9, 2010Assignee: Fujitsu LimitedInventors: Yoshihiro Nakata, Ei Yano
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Publication number: 20100029057Abstract: A silicone resin which is represented by the following rational formula (1) and solid at 120° C.: (H2SiO)n(HSiO1.5)m(SiO2)k??(1) wherein n, m and k are each a number, with the proviso that, when n+m+k=1, n is not less than 0.5, m is more than 0 and not more than 0.95 and k is 0 to 0.2. The silicone resin of the present invention can be advantageously used in a composition for forming a trench isolation having a high aspect ratio.Type: ApplicationFiled: September 21, 2007Publication date: February 4, 2010Applicant: JSR CorporationInventors: Haruo Iwasawa, Tatsuya Sakai, Yasuo Matsuki, Kentaro Tamaki
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Patent number: 7655576Abstract: In a method for manufacturing a semiconductor device, including forming an insulator film including a material having Si—CH3 bond and Si—OH bond, and irradiating the insulator film with ultraviolet rays, the rate of decrease of C concentration by X-ray photoelectron spectroscopy is not more than 30%, and the rate of decrease of one or more bonds selected from the group consisting of C—H bond, O—H bond and Si—O bond of Si—OH is not less than 10%, as a result of ultraviolet ray irradiation. A low-dielectric-constant insulator film that has a high film strength and can prevent increase of dielectric constant due to moisture absorption, a semiconductor device that can prevent device response speed delay and reliability decrease due to parasite capacity increase, and a manufacturing method therefor are provided.Type: GrantFiled: August 21, 2007Date of Patent: February 2, 2010Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
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Patent number: 7651958Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing a semiconductor device into a mold and subjecting a curable silicone composition that fills the spaces between said mold and said semiconductor device to compression molding, wherein the curable silicone composition comprises the following components: (A) an organopolysiloxane having at least two alkenyl groups per molecule; (B) an organopolysiloxane having at least two silicon-bonded hydrogen atoms per molecule; (C) a platinum-type catalyst; and (D) a filler, wherein either at least one of components (A) and (B) contains a T-unit siloxane and/or Q-unit siloxane. By the utilization this method, a sealed semiconductor device is free of voids in the sealing material, and a thickness of the cured silicone body can be controlled.Type: GrantFiled: December 7, 2004Date of Patent: January 26, 2010Assignee: Dow Corning Toray Company, Ltd.Inventors: Yoshitsuga Morita, Katsutoshi Mine, Junji Nakanishi, Hiroji Enami
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Patent number: 7648918Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate, forming a photo acid generator (PAG) layer on the substrate, exposing the PAG layer to radiation, and forming a photoresist layer on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.Type: GrantFiled: August 20, 2007Date of Patent: January 19, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Shang-Wen Chang
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Patent number: 7648927Abstract: Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or other silicon-containing materials. The photoexcitation process may expose the substrate and/or gases to an energy beam or flux prior to, during, or subsequent a deposition process. Therefore, the photoexcitation process may be used to pre-treat or post-treat the substrate or material, to deposit the silicon-containing material, and to enhance chamber cleaning processes.Type: GrantFiled: June 20, 2006Date of Patent: January 19, 2010Assignee: Applied Materials, Inc.Inventors: Kaushal K. Singh, Joseph M. Ranish
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Publication number: 20100009546Abstract: The present invention is a process for spin-on deposition of a silicon dioxide-containing film under oxidative conditions for gap-filling in high aspect ratio features for shallow trench isolation used in memory and logic circuit-containing semiconductor substrates, such as silicon wafers having one or more integrated circuit structures contained thereon, comprising the steps of: providing a semiconductor substrate having high aspect ratio features; contacting the semiconductor substrate with a liquid formulation comprising a low molecular weight aminosilane; forming a film by spreading the liquid formulation over the semiconductor substrate; heating the film at elevated temperatures under oxidative conditions. Compositions for this process are also set forth.Type: ApplicationFiled: June 26, 2009Publication date: January 14, 2010Applicant: Air Products and Chemicals, Inc.Inventors: Scott Jeffrey Weigel, Mark Leonard O'Neill, Bing Han, Hansong Cheng, Manchao Xiao, Chia-Chien Lee
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Publication number: 20100003181Abstract: A method of forming on a substrate an amorphous silica-based coating film having a low dielectric constant of 3.0 or below and a film strength (Young's modulus) of 3.0 GPa or more, which comprises, as a typical one, the steps of; (a) coating on the substrate a liquid composition containing hydrolysate of an organic silicon compound or compounds hydrolyzed in the presence of tetraalkylammonium hydroxide (TAAOH); (b) setting the substrate in a chamber and then drying a coating film formed on the substrate at a temperature in the range from 25 to 340° C.; (c) heating the coating film at a temperature in the range from 105 to 450° C. with introduction of a superheated steam having such a temperature into the chamber, and (d) curing the coating film at a temperature in the range from 350 to 450° C. with introduction of a nitrogen gas into the chamber.Type: ApplicationFiled: July 11, 2007Publication date: January 7, 2010Applicant: JGC CATALYSTS AND CHEMICALS LTD.Inventors: Miki Egami, Akira Nakashima, Michio Komatsu
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Patent number: 7642199Abstract: A method of producing a silica or silica-like coating by forming a precursor formulation from oligomeric organosilicate. The precursor formulation is coated on a substrate as a continuous liquid phase. The precursor formulation is then cured in an ammoniacal atmosphere to produce a continuous, interconnected, nano-porous silica network.Type: GrantFiled: May 31, 2006Date of Patent: January 5, 2010Assignee: Xerocoat Inc.Inventors: Paul Meredith, Michael Harvey
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Patent number: 7642205Abstract: A method that is performed for heat treating a semiconductor wafer in a process chamber, as an intermediate part of an overall multi-step technique for processing the wafer, includes applying an energy transfer layer to at least a portion of the wafer, and exposing the wafer to an energy source in the process chamber in a way which subjects the wafer to a thermal profile such that the energy transfer layer influences at least one part of the thermal profile. The thermal profile has at least a first elevated temperature event. The method further includes, in time relation to the thermal profile, removing the energy transfer layer in the process chamber at least sufficiently for subjecting the wafer to a subsequent step. An associated intermediate condition of the wafer is described.Type: GrantFiled: April 8, 2005Date of Patent: January 5, 2010Assignee: Mattson Technology, Inc.Inventor: Paul J. Timans
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Patent number: 7638388Abstract: In a method of forming a pattern and a method of manufacturing a capacitor using the same, a conductive layer is formed on a mold layer having an opening. A first buffer layer pattern including a polymer having a repeating unit of anthracene-methyl methacrylate and a repeating unit of alkoxyl-vinyl benzene is formed on the conductive layer in the opening. The first buffer layer pattern is baked to cross-link the polymers and form a second buffer layer pattern that is insoluble in a developing solution. The conductive layer on a top portion of the mold layer is selectively removed by using the second buffer layer pattern as an etching mask. Accordingly, a conductive pattern for a semiconductor device is formed. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.Type: GrantFiled: November 27, 2007Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Min Kim, Jae-Ho Kim, Young-Ho Kim, Boo-Deuk Kim, Seok Han
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Patent number: 7638373Abstract: According to a method of manufacturing a thin-film transistor (TFT) substrate, a gate insulation layer, a semiconductor layer, an ohmic contact layer, and a data metal layer are sequentially formed on a substrate. A photoresist pattern is formed in a source electrode area and a drain electrode area. A data metal layer is etched using the photoresist pattern as an etch-stop layer to form a data wire including a source electrode and a drain electrode. A photoresist pattern is reflowed to cover a channel region between a source electrode and the drain electrode. An ohmic contact layer and the semiconductor layer are etched using the reflowed photoresist pattern as an etch-stop layer to form an active pattern including an ohmic contact pattern and a semiconductor pattern. The reflowed photoresist pattern is etched back to expose a portion of the ohmic contact pattern in the channel region. The ohmic contact pattern is etched using the etched-back photoresist pattern as an etch-stop layer.Type: GrantFiled: January 17, 2008Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Kweon Heo, Chun-Gi You
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Publication number: 20090317971Abstract: A method for restoring the dielectric constant of a low dielectric constant film is described. A porous dielectric layer having a plurality of pores is formed on a substrate. The plurality of pores is then filled with an additive to provide a plugged porous dielectric layer. Finally, the additive is removed from the plurality of pores.Type: ApplicationFiled: June 9, 2009Publication date: December 24, 2009Inventors: Zhenjiang Cui, May Yu, Alexandros T. Demos, Mehul Naik
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Patent number: 7629272Abstract: Processes for forming porous low k dielectric materials from low k dielectric films containing a porogen material include exposing the low k dielectric film to ultraviolet radiation. In one embodiment, the film is exposed to broadband ultraviolet radiation of less than 240 nm for a period of time and intensity effective to remove the porogen material. In other embodiments, the low k dielectric film is exposed to a first ultraviolet radiation pattern effective to increase a crosslinking density of the film matrix while maintaining a concentration of the porogen material substantially the same before and after exposure to the first ultraviolet radiation pattern. The low k dielectric film can be then be processed to form a metal interconnect structure therein and subsequently exposed to a second ultraviolet radiation pattern effective to remove the porogen material from the low k dielectrics film and form a porous low k dielectric film.Type: GrantFiled: June 7, 2005Date of Patent: December 8, 2009Assignee: Axcelis Technologies, Inc.Inventors: Carlo Waldfried, Qingyuan Han, Orlando Escorcia, Ivan Berry, III
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Publication number: 20090294922Abstract: Provided is an organic silicon oxide fine particle capable of satisfying an expected dielectric constant and mechanical strength and having excellent chemical stability for obtaining a high-performance porous insulating film.Type: ApplicationFiled: May 27, 2009Publication date: December 3, 2009Inventors: Yoshitaka Hamada, Fujio Yagihashi, Takeshi Asano, Hideo Nakagawa, Masaru Sasago
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Patent number: 7622399Abstract: A method of forming a low dielectric constant structure. The method comprises providing at a first temperature a dielectric material having a first dielectric constant and a first elastic modulus, and curing the dielectric material by a thermal curing process, in which the material is heated to a second temperature by increasing the temperature at an average rate of at least 1° C. per second. As a result a densified, dielectric material is obtained which has a low dielectric constant.Type: GrantFiled: March 10, 2004Date of Patent: November 24, 2009Assignee: Silecs OyInventors: Jason Reid, Nigel Hackera, Nina Pirilä, Juha Rantala, William McLaughlin
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Patent number: 7615473Abstract: When an ion is introduced into a semiconductor on which a resist is formed, the ion and the resist react with each other to generate a gas (dissociated gas) and a component of the thus-generated dissociated gas is introduced into the semiconductor, which becomes a factor to deteriorate properties of the semiconductor. According to the invention, the dissociated gas to be generated from an organic film is treated. Particularly, the dissociated gas is treated before an ion introduction is performed. As a method of performing such a treatment, the ion introduction is performed by dividing ion introduction processing itself into a plurality of times. The dissociated gas is generated in a maximum quantity just after the ion introduction is started.Type: GrantFiled: January 16, 2003Date of Patent: November 10, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shigenori Hayakawa