Subsequent Heating Modifying Organic Coating Composition Patents (Class 438/781)
  • Patent number: 7468330
    Abstract: A method of forming a structure. The method including: forming a layer of a polymerizable composition including one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, one or more polymerizable diluents, one or more photoacid generators and/or one or more photoinitiators; pressing a surface of a template having a relief pattern into the layer, the template, the layer filling voids in the relief pattern; polymerizing the layer to have thick and thin regions corresponding to the relief pattern; removing the template; removing the thin regions of the dielectric layer; and either curing the layer to create a porous dielectric layer followed by filling spaces between the thick regions of the porous dielectric layer with an electrically conductive material or filling spaces between the thick regions of the dielectric layer with an electrically conductive material followed by curing the dielectric layer to create a porous dielectric layer.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: December 23, 2008
    Assignee: International Business Machines Corporation
    Inventors: Robert David Allen, Richard Anthony DiPietro, Geraud Jean-Michel Dubois, Mark Whitney Hart, Robert Dennis Miller, Ratnam Sooriyakumaran
  • Patent number: 7465977
    Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: December 16, 2008
    Assignee: Microbridge Technologies Inc.
    Inventors: Leslie M. Landsberger, Oleg Grudin
  • Publication number: 20080290472
    Abstract: Provided is a porous-film-forming composition containing silicon-oxide-based fine particles and a polysiloxane compound obtained by hydrolysis and condensation reactions, in the presence of an acid catalyst, of a hydrolyzable silane compound containing at least one tetrafunctional alkoxysilane compound represented by the following formula (1): Si(OR1)4 ??(1) wherein, R1s may be the same or different and each independently represents a linear or branched C1-4 alkyl group and/or at least one alkoxysilane compound represented by the following formula (2): R2nSi(OR3)4-n ??(2) wherein, R2(s) may be the same or different when there are plural R2s and each independently represents a linear or branched C1-8 alkyl group, R3(s) may be the same or different when there are plural R3s and each independently represents a linear or branched C1-4 alkyl group, and n is an integer from 1 to 3 in the reaction mixture containing a large excess of water.
    Type: Application
    Filed: February 12, 2008
    Publication date: November 27, 2008
    Inventors: Fujio Yagihashi, Yoshitaka Hamada, Takeshi Asano, Tsutomu Ogihara, Motoaki Iwabuchi, Hideo Nakagawa, Masaru Sasago
  • Patent number: 7456045
    Abstract: The present invention provides a process for preparing a melt-processed organic-inorganic hybrid material including the steps of maintaining a solid organic-inorganic hybrid material at a temperature above the melting point but below the decomposition temperature of the organic-inorganic hybrid material for a period of time sufficient to form a uniform melt and thereafter, cooling the uniform melt to an ambient temperature under conditions sufficient to produce the melt-processed organic-inorganic hybrid material.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: November 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Patrick W. DeHaven, David R. Medeiros, David B. Mitzi
  • Patent number: 7452735
    Abstract: Composition of carbon nanotubes (CNTs) are produced into inks that are dispensable via printing or stencil printing processes. The CNT ink is dispensed into wells formed in a cathode structure through a stencil.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: November 18, 2008
    Assignee: Applied Nanotech Holdings, Inc.
    Inventors: Yunjun Li, Richard Fink, Mohshi Yang, Zvi Yaniv
  • Patent number: 7446058
    Abstract: An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Griselda Bonilla, Qinghuang Lin, Terry A. Spooner
  • Patent number: 7445953
    Abstract: The invention relates to low temperature curable spin-on glass materials which are useful for electronic applications, such as optical devices. A substantially crack-free and substantially void-free silicon polymer film is produced by (a) preparing a composition comprising at least one silicon containing pre-polymer, a catalyst, and optionally water; (b) coating a substrate with the composition to form a film on the substrate, (c) crosslinking the composition by heating to produce a substantially crack-free and substantially void-free silicon polymer film, having a a transparency to light in the range of about 400 nm to about 800 nm of about 95% or more.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: November 4, 2008
    Assignee: Honeywell International Inc.
    Inventors: Victor Lu, Lei Jin, Arlene J. Suedmeyer, Paul G. Apen, Peter Alfred Smith, JingHong Chen
  • Patent number: 7446057
    Abstract: A method for forming a multilevel structure on a surface by depositing a curable liquid layer on the surface; pressing a stamp having a multilevel pattern therein into the liquid layer to produce in the liquid layer a multilevel structure defined by the pattern; and, curing the liquid layer to produce a solid layer having the multilevel structure therein. Mechanical alignment may be employed to enhance optical alignment of the stamp relative to the substrate via spaced protrusions on the substrate on which the structure is to be formed and complementary recesses in the patterning of the stamp.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Alexander Bietsch, Bruno Michel
  • Publication number: 20080265381
    Abstract: A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a nanoscale manner and which exhibits improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other critical properties is provided. The porous composite material is fabricating utilizing at least one bifunctional organic porogen as a precursor compound.
    Type: Application
    Filed: June 4, 2008
    Publication date: October 30, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Stephen M. Gates, Alfred Grill, Deborah A. Neumayer, Son Nguyen, Vishnubhai V. Patel
  • Patent number: 7442633
    Abstract: Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on the high K dielectric layer. According to one embodiment, the high K dielectric layer includes Al2O3. According to other embodiments, the nano crystals include gold nano crystals and gold nano crystals. One capacitor embodiment includes a MIS (metal-insulator-silicon) capacitor fabricated on silicon substrate, and another capacitor embodiment includes a MIM (metal-insulator-metal) capacitor fabricated between the interconnect layers above silicon substrate. The structure of the capacitor is useful for reducing a resonance impedance and a resonance frequency for an integrated circuit chip. Other aspects are provided herein.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: October 28, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7439111
    Abstract: An object of the invention is to form an insulating film having favorable insulation and planarity. An insulating film is formed by performing heat treatment a resin containing a siloxane polymer after application, in an atmosphere including an inert gas as its main component and having an oxygen concentration of 5% or less and a water concentration of 1% or less. Preferably, an oxygen concentration is 1% or less and a water concentration is 0.1% or less. The resin containing a siloxane polymer includes a methyl group and a phenyl group. Further, the inert gas is nitrogen.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: October 21, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Koji Moriya, Masayuki Sakakura, Hideto Ohnuma
  • Publication number: 20080248280
    Abstract: The invention provides a preparation process of organic-group-modified zeolite fine particles excellent in stability of particle size and to be used for electronic materials or the like. The preparation process comprises a first step of obtaining a liquid containing zeolite seed crystals having a particle size of 80 nm or less which are formed in the presence of a structure directing agent, a second step of adding an organic-group-containing hydrolyzable silane compound to the liquid obtained by the first step, and a third step of maturing the liquid of the second step at temperature higher than that of the first step. A dispersion liquid of zeolite fine particles obtained by the process.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 9, 2008
    Inventors: Yoshitaka Hamada, Masaru Sasago, Hideo Nakagawa, Yasunori Morinaga
  • Publication number: 20080248655
    Abstract: Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.
    Type: Application
    Filed: June 20, 2008
    Publication date: October 9, 2008
    Inventors: Matthew E. Colburn, Dmitriy Shneyder, Shahab Siddiqui
  • Patent number: 7432218
    Abstract: A process of a porous body comprises the steps of disposing a first material in which pores are formed by anodization on a substrate to form a first layer, disposing on the first layer a second material which has a hardness lower than that of the first material and an oxide of which is dissolved by an anodization step to form a second layer, forming a concave structure on a surface of the second layer, oxidizing the second layer, and subjecting the first layer to anodization to dissolve the second layer. A magnetic recording medium or a light-emitting element comprises a first layer which is comprised of an oxide of aluminum and comprises a porous portion on a substrate, and a second layer on the first layer which has a hardness lower than that of the first layer and is comprised of a metal element, wherein the pores are packed with a magnetic substance or a light-emitting material.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: October 7, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aya Imada, Tohru Den
  • Patent number: 7432126
    Abstract: A substrate comprises at least one semiconductor layer applied to a substrate material, whereby the semiconductor layer comprises an inert matrix material, in which an inorganic semiconductor material is embedded in particle form.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: October 7, 2008
    Assignee: Infineon Technologies AG
    Inventor: Günter Schmid
  • Publication number: 20080242113
    Abstract: A method for forming a high-K dielectric film on a silicon substrate includes the steps of processing a surface of the silicon substrate with a diluted hydrofluoric acid, conducting nucleation process of HfN, after the step of processing with the diluted hydrofluoric acid, by supplying a metal organic source containing Hf and nitrogen to the surface of said silicon substrate, and forming an Hf silicate film by a CVD process, after the step of nucleation, by supplying a metal organic source containing Hf and a metal organic source containing Si to the surface of the silicon substrate.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 2, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Shintaro AOYAMA, Tsuyoshi TAKAHASHI, Kouji SHIMOMURA, Miki ARUGA
  • Publication number: 20080242112
    Abstract: A process for fabricating an electronic device including: depositing a layer comprising a semiconductor; liquid depositing a dielectric composition comprising a lower-k dielectric material, a higher-k dielectric material, and a liquid, wherein the lower-k dielectric material and the higher-k dielectric material are not phase separated prior to the liquid depositing; and causing phase separation of the lower-k dielectric material and the higher-k dielectric material to form a phase-separated dielectric structure wherein the lower-k dielectric material is in a higher concentration than the higher-k dielectric material in a region of the dielectric structure closest to the layer comprising the semiconductor, wherein the depositing the layer comprising the semiconductor is prior to the liquid depositing the dielectric composition or subsequent to the causing phase separation.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 2, 2008
    Applicant: XEROX CORPORATION
    Inventors: Yiliang Wu, Hadi K. Mahabadi, Beng S. Ong, Paul F. Smith
  • Patent number: 7427563
    Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: September 23, 2008
    Assignee: LSI Corporation
    Inventors: Hong-Qiang Lu, Peter A. Burke, Wilbur G. Catabay
  • Patent number: 7427570
    Abstract: The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous organosilicate layers are useful, for example, as masks.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: September 23, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20080214018
    Abstract: A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
    Type: Application
    Filed: December 27, 2007
    Publication date: September 4, 2008
    Inventors: Sung Kyu MIN, Ja Chun KU, Chan Bae KIM, Sang Tae AHN, Chai O. CHUNG, Hyeon Ju AN, Hyo Seok LEE, Eun Jeong KIM
  • Publication number: 20080194117
    Abstract: A manufacturing method of a semiconductor device, includes forming a porous organo-siloxane film containing a porogen component having carbon as a main component above a semiconductor substrate, forming an upper-side insulating film having at least one of film density and film composition different from that of the porous organo-siloxane film on the porous organo-siloxane film, and applying at least one of an electron beam and an ultraviolet ray to the porous organo-siloxane film and upper-side insulating film to cause polymerization reaction of the porogen component in the porous organo-siloxane film.
    Type: Application
    Filed: January 25, 2008
    Publication date: August 14, 2008
    Inventors: Hideaki Masuda, Hideshi Miyajima, Tsutomu Shimayama
  • Publication number: 20080194097
    Abstract: A method of reworking a semiconductor substrate and a method of forming a pattern of semiconductor device using the same without damage to an organic anti-reflective coating (ARC) is provided. The method of reworking a semiconductor substrate includes forming a photoresist pattern on a substrate having the organic ARC formed thereon. An entire surface of the substrate having the photoresist pattern formed thereon may be exposed when a defect is present in the photoresist pattern. The entire-surface-exposed photoresist pattern may be removed by performing a developing process without damage to the organic ARC.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 14, 2008
    Inventors: Eun-Sung Kim, Tae-Kyu Kim, Seok-Hwan Oh
  • Patent number: 7407894
    Abstract: There are provided: compound semiconductor particles that can display more excellent performance in functions peculiar to the compound semiconductor (e.g. luminosity and luminescence efficiency); and a production process for obtaining such compound semiconductor particles with economy, good productivity, and ease. Compound semiconductor particles, according to the present invention, are characterized by comprising body particles and a metal oxide, wherein the body particles have particle diameters of smaller than 1 ?m and are covered with the metal oxide and include a compound semiconductor including an essential element combination of at least one element X selected from the group consisting of C, Si, Ge, Sn, Pb, N, P, As, Sb, S, Se, and Te and at least one metal element M that is not identical with the element X, and wherein the metal oxide is a metal oxide to which an acyloxyl group is bonded.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: August 5, 2008
    Assignees: Nippon Shokenbai Co., Ltd.
    Inventors: Masakazu Kobayashi, Mitsuo Takeda
  • Patent number: 7405168
    Abstract: A method and computer readable medium for treating a dielectric film on one or more substrates includes disposing the one or more substrates in a process chamber configured to perform plural treatment processes on a dielectric film. The dielectric film is formed on at least one of said one or more substrates, wherein the dielectric film includes an initial dielectric constant having a value less than the dielectric constant of SiO2. A thermal treatment process that includes annealing the one or more substrates is performed in order to remove volatile constituents from the dielectric film on the one or more substrates and a chemical treatment process is performed on the one or more substrates, including: introducing a treating compound to the dielectric film on the one or more substrates, and heating the one or more substrates.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: July 29, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Eric M. Lee, Dorel I. Toma
  • Patent number: 7399715
    Abstract: A method of forming an organic silica-based film, including: applying a composition for forming an insulating film for a semiconductor device, which is cured by using heat and ultraviolet radiation, to a substrate to form a coating; heating the coating; and applying heat and ultraviolet radiation to the coating to effect a curing treatment, wherein the composition includes organic silica sol having a carbon content of 11.8 to 16.7 mol %, and an organic solvent, the organic silica sol being a hydrolysis-condensation product produced by hydrolysis and condensation of a silane compound selected from compounds shown by the general formulae (1): R1Si(OR2)3, (2): Si(OR3)4, (3): (R4)2Si(OR5)2, and (4): R6b(R7O)3-bSi—(R10)d—Si(OR8)3-cR9c.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: July 15, 2008
    Assignee: JSR Corporation
    Inventors: Hajime Tsuchiya, Hiromi Egawa, Terukazu Kokubo, Atsushi Shiota
  • Publication number: 20080157229
    Abstract: A semiconductor device and a fabricating method thereof are provided. The method includes forming a Tetraethyl Orthosilicate (TEOS) layer on a semiconductor substrate, and performing a heat treatment on the TEOS layer to shrink the LEOS layer, thereby forming a gate oxide layer of a shrunken TEOS layer.
    Type: Application
    Filed: September 24, 2007
    Publication date: July 3, 2008
    Inventor: JONG WON SUN
  • Patent number: 7393795
    Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: July 1, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Robin Cheung, Siyi Li
  • Patent number: 7390434
    Abstract: A dope containing cellulose acylate as a main content of polymer is cast on a front surface of a moving belt in a method of producing a film from a solution. A drying apparatus is confronted to a back surface of said belt to evaporate a solvent in the gel-like film. Further, a condensers are confronted to a cast surface of said gel-like film to condense a solvent vapor for recovery. A wind speed above and near the gel-like film is from 0.01 m/s to 0.5 m/s, and the belt is transported downwards at the casting position PS. When d (mm) is a distance between the casting surface and each condenser, Tw (° C.) is a temperature of each condenser, and Ts (° C.) is a temperature of the casting dope, conditions are satisfied: Q=(Ts?Tw)/d and 5<Q<100. The obtained film is excellent in thickness uniformity and optical properties, and therefore adequate for the optical film.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: June 24, 2008
    Assignee: FUJIFILM Corporation
    Inventor: Tadahiro Tsujimoto
  • Publication number: 20080145677
    Abstract: The present invention relates to a coating composition for insulating film production, a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same, and more particularly to a coating composition for insulating film production having a low dielectric constant and that is capable of producing an insulating film with superior mechanical strength (elasticity), a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same. The coating composition of the present invention comprises an organic siloxane resin having a small molecular weight, and water, and significantly improves low dielectricity and mechanical strength of an insulating film.
    Type: Application
    Filed: January 25, 2008
    Publication date: June 19, 2008
    Inventors: Myung-Sun Moon, Min-Jin Ko, Hye-Yeong Nam, Jung-Won Kang, Bum-Gyu Choi, Byung-Ro Kim, Gwi-Gwon Kang, Young-Duk Kim, Sang-Min Park
  • Patent number: 7387927
    Abstract: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: June 17, 2008
    Assignee: Intel Corporation
    Inventors: Robert B. Turkot, Jr., Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Uday Shah, Suman Datta, Robert S. Chau
  • Patent number: 7387971
    Abstract: A fabricating method for a flat panel display device having a thin film pattern over a substrate is disclosed. The fabricating method includes depositing a hydrophilic resin over a substrate and patterning the hydrophilic resin to form hydrophilic resin patterns over areas outside where thin film patterns are to be formed over the substrate. The fabricating method also includes depositing a hydrophobic nano powder thin film material over the substrate and between the hydrophilic resin patterns and removing the hydrophilic resin patterns to form hydrophobic nano powder thin film patterns over the substrate. Moreover, the fabricating method includes treating the hydrophobic nano powder thin film patterns to form the thin film pattern.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: June 17, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Gee Sung Chae, Mi Kyung Park
  • Patent number: 7384816
    Abstract: An apparatus and method for forming vias in one or more layers, comprising one or more beams located in alignment with the layers for forming one or more vias in one or more areas of the layers. A vacuum mechanism is provided for collecting ablated material caused by the directed beams forming the one or more vias, the vacuum mechanism being in fixed alignment with respect to the one or more beams such that the vacuum applies a removal force on the ablated material at the time and location when the one or more vias is being formed.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: June 10, 2008
    Assignee: Eastman Kodak Company
    Inventors: Ronald S. Cok, Michael L. Boroson, Timothy J. Tredwell, Andrea S. Rivers, Dustin L. Winters
  • Patent number: 7381659
    Abstract: A method for reducing the tensile stress of a low-k dielectric layer includes depositing an organosilicate layer on a substrate, the layer having an initial tensile stress value associated therewith. The layer is annealed in a reactive environment at a temperature and for a duration selected to result in the layer having a reduced tensile stress value with respect the initial tensile stress value following the completion of the annealing.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: June 3, 2008
    Assignee: International Business Machines Corporation
    Inventors: Son Van Nguyen, Thomas M. Shaw
  • Patent number: 7375369
    Abstract: Certain spin-coatable liquids and application techniques are described, which can be used to form nanotube films or fabrics of controlled properties. A spin-coatable liquid for formation of a nanotube film includes a liquid medium containing a controlled concentration of purified nanotubes, wherein the controlled concentration is sufficient to form a nanotube fabric or film of preselected density and uniformity, and wherein the spin-coatable liquid includes less than 1×1018 atoms/cm3 of metal impurities. The spin-coatable liquid is substantially free of particle impurities having a diameter of greater than about 500 nm.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: May 20, 2008
    Assignee: Nantero, Inc.
    Inventors: Rahul Sen, Ramesh Sivarajan, Thomas Rueckes, Brent M. Segal
  • Publication number: 20080102649
    Abstract: There is provided an underlayer coating forming composition for lithography that is used in lithography process of the manufacture of semiconductor devices and that has a high dry etching rate in comparison to photoresists, does not intermix with photoresists, and is capable of flattening the surface of a semi conductor substrate having holes of a high aspect ratio. The underlayer coating forming composition for lithography comprises, a compound having two or more protected carboxylic groups, a compound having two or more epoxy groups, and a solvent.
    Type: Application
    Filed: January 6, 2006
    Publication date: May 1, 2008
    Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Satoshi Takei, Tetsuya Shinjo, Keisuke Hashimoto, Yasushi Sakaida
  • Patent number: 7358299
    Abstract: A composition comprising a siloxane resin, a silicon compound substantially consisting of silicon, carbon and hydrogen, wherein the number ratio of carbon to silicon atoms forming an —X— bond (wherein X is (C)m (where m is an integer in the range of from 1 to 3), or a substituted or unsubstituted aromatic group with 9 or less carbon atoms) in the main chain of one molecule is in the range of from 2:1 to 12:1, and a solvent, is subjected to a heat treatment to form a low dielectric constant film. Accordingly, a low dielectric constant film having excellent resistance against chemicals and excellent moisture resistance is provided. A semiconductor integrated circuit having a fast response can be produced by using the film.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: April 15, 2008
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Ei Yano
  • Patent number: 7358597
    Abstract: A dielectric layer on a semiconductor substrate is made porous by radiation with UV light. The dielectric material contains a photosensitive moiety that absorbs UV radiation and dissociates from the dielectric material. The UV-activated material then may be diffused to create pores in the dielectric layer, and to provide a dielectric layer having a low dielectric constant.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: April 15, 2008
    Assignee: Intel Corporation
    Inventor: Michael D. Goodner
  • Patent number: 7354779
    Abstract: Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable depth of a film to the wafer, such that the variable depth is modulated based on the local topography of the wafer. The resultant topography of the applied film and wafer is substantially planar (e.g., within approximately 100 nm) across the wafer.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: April 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Colin J. Brodsky, Scott J. Bukofsky, Allen H. Gabor
  • Patent number: 7351669
    Abstract: To form a substantially closed void between two structures on a substrate, a flowable liquid dielectric material is deposited to fill partially the space between the structures, and a surface is placed to bridge and substantially close the space between the structures. The substrate is then inverted whilst maintaining the bridge and the deposited material is allowed to flow down to be substantially supported by the surface. The material is set in its substantially supported position, and the surface is removed.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: April 1, 2008
    Assignee: Aviza Technology Limited
    Inventor: John MacNeil
  • Patent number: 7348281
    Abstract: A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating is partially cured by baking at a low temperature. Next, a solvent is dispensed over the coated wafer and allowed to contact the coating for a period of time. The solvent removes the bottom anti-reflective coating at a rate controlled by the bottom anti-reflective coating's bake temperature and the solvent contact time to yield a bottom anti-reflective coating thickness that is thin, while maintaining optimum light-absorbing properties on the dielectric stack. In another possible application of this method, sufficient bottom anti-reflective coating may be removed to only partially fill the vias in order to protect the bottoms of the vias during subsequent processing.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: March 25, 2008
    Assignee: Brewer Science Inc.
    Inventors: Nickolas L. Brakensiek, Carlton A. Washburn, Earnest C. Murphy
  • Patent number: 7345000
    Abstract: A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to an alkyl silane, an alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an aryl silane, an acyl silane, a cyclo siloxane, a polysilsesquioxane (PSS), an aryl siloxane, an acyl siloxane, or a halo siloxane, or any combination thereof. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: March 18, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Robert Kevwitch, Brandon Hansen, Dorel Ioan Toma, Jianhong Zhu
  • Patent number: 7341886
    Abstract: A method and apparatus for forming vias in one or more layers, comprising providing a vacuum chamber, one or more beams in the vacuum chamber. The array of directed beams located in alignment with a layer for ablating one or more areas of the layer for forming vias. A cold trap is also provided in the vacuum chamber that is in fixed alignment with respect to the one or more beams such that the ablated material condenses upon the cold trap at the time and location when the one or more vias is being formed.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: March 11, 2008
    Assignee: Eastman Kodak Company
    Inventors: Ronald S. Cok, Timothy J. Tredwell, Dustin L. Winters, Andrea S. Rivers, Michael L. Boroson
  • Patent number: 7341961
    Abstract: Provided are a method of manufacturing an organic thin film transistor (TFT), the organic TFT manufactured using the method, and a flat panel display device comprising the organic TFT. The method includes: coating a lubricant on a predetermined region of a substrate where an organic semiconductor layer is not to be formed; coating an organic semiconductor layer on the entire substrate; heating the coated substrate to melt the lubricant; and releasing the organic semiconductor layer formed above the predetermined region from the substrate. According to the method, the organic semiconductor layer can be effectively patterned without damaging the substrate and the organic semiconductor material.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: March 11, 2008
    Assignee: Samsung SDI, Co., Ltd.
    Inventors: Min-Chul Suh, Jae-Bon Koo
  • Patent number: 7335586
    Abstract: A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric layer with a silazane to form a monolayer of silane molecules on the surface, and applying a second plasma to the surface of the dielectric layer to induce a polymerization of at least a portion of the silane molecules. The polymerized silane molecules form a cross-linked matrix that builds over a substantial portion of the surface of the dielectric layer and seals at least some of the exposed pores.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. RamachandraRao, Boyan Boyanov, Grant Kloster, Hyun-Mog Park
  • Patent number: 7332445
    Abstract: A porous organosilicate glass (OSG) film: SivOwCxHyFz, where v+w+x+y+z=100%, v is 10 to 35 atomic %, w is 10 to 65 atomic %, x is 5 to 30 atomic %, y is 10 to 50 atomic % and z is 0 to 15 atomic %, has a silicate network with carbon bonds as methyl groups (Si—CH3) and contains pores with diameter less than 3 nm equivalent spherical diameter and dielectric constant less than 2.7. A preliminary film is deposited by a chemical vapor deposition method from organosilane and/or organosiloxane precursors, and independent pore-forming precursors. Porogen precursors form pores within the preliminary film and are subsequently removed to provide the porous film. Compositions, film forming kits, include organosilane and/or organosiloxane compounds containing at least one Si—H bond and porogen precursors of hydrocarbons containing alcohol, ether, carbonyl, carboxylic acid, ester, nitro, primary amine, secondary amine, and/or tertiary amine functionality or combinations.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: February 19, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Aaron Scott Lukas, Mark Leonard O'Neill, Eugene Joseph Karwacki, Jr., Raymond Nicholas Vrtis, Jean Louise Vincent
  • Patent number: 7332444
    Abstract: A method for smoothing areas of a structure made of a first material having a predetermined first glass transition temperature on a carrier includes the steps of: (1) applying a second material having a predetermined second glass transition temperature, so that the surface of the structure of the first material is at least partially covered by the second material; (2) increasing the temperature of the first material to a first predeterminable temperature, which is greater than the first glass transition temperature; and (3) lowering the temperature of the first material below the first glass transition temperature of the first material.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: February 19, 2008
    Assignee: Infineon Technologies AG
    Inventors: Wolf-Dieter Domke, Siegfried Schwarzl
  • Patent number: 7329617
    Abstract: A method is provided for enhancing adhesion between a molding compound and a semiconductor device comprising a semiconductor chip attached on a carrier, such as a lead frame, by coating the semiconductor device with a polymer primer prior to molding the semiconductor device. Such coating may be performed by dipping, dripping or spraying the semiconductor device in or with a polymer solution.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: February 12, 2008
    Assignee: ASM Assembly Automation Ltd.
    Inventors: Jianxiong Li, Chi Chuen Chaw, Ngai Kin Tsui, Deming Liu, Yiu Fai Kwan, Wai Chan
  • Patent number: 7316983
    Abstract: The purpose of the invention is to provide a film formation apparatus capable of forming an EL layer with a high purity and a high density, and a cleaning method. The invention is a formation of an EL layer with a high density by heating a substrate 10 by a heating means for heating a substrate, decreasing the pressure of a film formation chamber with a pressure decreasing means (a vacuum pump such as a turbo-molecular pump, a dry pump, or a cryopump) connected to the film formation chamber to 5×10?3 Torr (0.665 Pa) or lower, preferably 1×10?3 Torr (0.133 Pa) or lower, and carrying out film formation by depositing organic compound materials from deposition sources. In the film formation chamber, cleaning of deposition masks is carried out by plasma.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: January 8, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masakazu Murakami
  • Patent number: 7309662
    Abstract: This invention relates to a method and apparatus for forming a film on the substrate. The method comprises supplying to the chamber in gaseous or vapor form a silicon containing organic compound and an oxidizing agent in the presence of a plasma to deposit a film on the substrate and setting the film such that carbon containing groups are retained therein. In particular embodiments the setting is achieved by exposing the film to H2 plasma.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: December 18, 2007
    Assignee: Aviza Europe Limited
    Inventors: Katherine Giles, Knut Beekmann, Christopher David Dobson, John MacNeil, Antony Paul Wilby
  • Publication number: 20070281497
    Abstract: Methods are provided for processing a substrate comprising a bilayer barrier film thereon. In one aspect, a method comprises depositing a first barrier layer, depositing a second barrier layer on the first barrier layer, depositing a dielectric layer on the bilayer barrier film formed by the first barrier layer and the second barrier layer, and ultraviolet curing the dielectric layer. In another aspect, a method comprises depositing a first barrier layer, depositing a second barrier layer on the first barrier layer, depositing a dielectric layer on the bilayer barrier film formed by the first barrier layer and the second barrier layer, and curing the dielectric layer with an electron beam treatment.
    Type: Application
    Filed: May 21, 2007
    Publication date: December 6, 2007
    Inventors: Yijun Liu, Huiwen Xu, Li-Qun Xia, Chad Peterson, Hichem M'saad