Subsequent Heating Modifying Organic Coating Composition Patents (Class 438/781)
  • Patent number: 7300824
    Abstract: A method is disclosed for packaging semiconductor chips on a flexible substrate employing thin film transfer. The semiconductor chips are placed on a temporary adhesive substrate, then covered by a permanent flexible substrate with a casting layer for planarizingly embedding the chips on the permanent substrate before removing the temporary substrate. With the surface of the chips coplanar with the surface of the complete structure without any gaps, interconnect metal lines can be easily placed on the uninterrupted surface, connecting the chips and other components.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: November 27, 2007
    Inventor: James Sheats
  • Patent number: 7300889
    Abstract: A method for forming a coating film, comprises the steps of: applying a raw material of a low dielectric constant onto a surface of a plate-like material; reducing oxygen concentration in the atmosphere surrounding the plate-like material to be less than or equal to 1% before a surface temperature of said plate-like material to be treated rises to 200° C.; thereafter heating said plate-like material to a temperature greater than or equal to 400° C.; and then maintaining the oxygen content in the atmosphere to be less than or equal to 1% until the surface temperature of said plate-like material to be treated lowers to 200° C. The raw material is an organic SOG obtained by hydrolyzing and condensing at least one alkoxysilane compound into an organic solvent under an acid catalyst.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: November 27, 2007
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Hiroki Endo, Taiichiro Aoki, Akihiko Nakamura
  • Patent number: 7297360
    Abstract: An insulation film comprising an organosilicon polymer and an organic polymer such as polyarylene, polyarylene ether, polyimide, and fluororesin is disclosed, wherein the organosilicon polymer has a relative dielectric constant of 4 or less and has a dry etching selection ratio of 1/3 or less to silicon oxide, fluorine-doped silicon oxide, organosilicate glass, carbon-doped silicon oxide, methyl silsesquioxane, hydrogen silsesquioxane, a spin-on-glass, or polyorganosiloxane. The insulation film is used as an etching stopper or a hard mask in a dry etching process of interlayer dielectric films for semiconductors and can produce semiconductors having excellent precision with minimal damages.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: November 20, 2007
    Assignee: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Eiji Hayashi, Kouji Sumiya, Atsushi Shiota
  • Patent number: 7294579
    Abstract: The present invention relates to a method for forming a contact opening. First, a substrate having at least a dielectric layer formed thereon is provided. Then, a photoresist layer having a first opening is formed on the dielectric layer. A plasma etching operation is performed to form a second opening in the dielectric layer, and the first opening is located above the second opening. The bottom part of the first opening has a diameter smaller than that of the top part of the second opening. Thereafter, the photoresist layer is removed from the dielectric layer. Accordingly, at least a portion of the exposed contact opening will not be oxidized to prevent an increase in the resistance between the conductive pattern and the conductive layer that fills in the contact opening.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: November 13, 2007
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Ying-Chou Chi, Rong-Duo Wang, Ying-Tsung Tu, Chao-Huan Hsu
  • Patent number: 7294586
    Abstract: A method of processing a substrate, comprising forming a chemically amplified resist film on a substrate, irradiating energy beams to the chemically amplified resist film to form a latent image therein, carrying out heat treatment with respect to the chemically amplified resist film, heating treatment being carried out in a manner of relatively moving a heating section for heating the chemically amplified resist film and the substrate forming a gas stream flowing reverse to the relatively moving direction of the heating section between the lower surface of the heating section and the chemically amplified resist film.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: November 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawano, Shinichi Ito, Eishi Shiobara
  • Patent number: 7294584
    Abstract: A siloxane-based resin having a novel structure and a semiconductor interlayer insulating film using the same. The siloxane-based resins have a low dielectric constant in addition to excellent mechanical properties and are useful materials in an insulating film between interconnect layers of a semiconductor device.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yi Yeol Lyu, Ki Yong Song, Joon Sung Ryu, Jong Baek Seon
  • Patent number: 7294585
    Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: November 13, 2007
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, legal representative, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak, Thomas Alan Deis, deceased
  • Patent number: 7291919
    Abstract: The interlayer dielectric film made of a three-dimensionally polymerized polymer is formed by polymerizing: first cross-linking molecules having three or more sets of functional groups in one molecule providing a three-dimensional structure; and a second cross-linking molecule having two sets of functional groups in one molecule providing a two-dimensional structure. In the three-dimensionally polymerized polymer, dispersed are a number of molecular level pores formed by the polymerization of the first and second cross-linking molecules.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: November 6, 2007
    Assignee: Matsushita ELectrical Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Patent number: 7291516
    Abstract: The present invention provides a process for preparing a melt-processed organic-inorganic hybrid material including the steps of maintaining a solid organic-inorganic hybrid material at a temperature above the melting point but below the decomposition temperature of the organic-inorganic hybrid material for a period of time sufficient to form a uniform melt and thereafter, cooling the uniform melt to an ambient temperature under conditions sufficient to produce the melt-processed organic-inorganic hybrid material.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: November 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Patrick W. DeHaven, David R. Medeiros, David B. Mitzi
  • Patent number: 7285501
    Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a solution processed device are described.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: October 23, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Mardilovich, Randy Hoffman, Gregory Herman
  • Patent number: 7285502
    Abstract: A method for forming a porous insulative structure on a semiconductor device structure includes forming a layer of unconsolidated electrically insulative, or dielectric, material with microcapsules dispersed therethrough on at least a portion of the surface of the semiconductor device structure. The microcapsules may be hollow or include a removable filler. Once the layer has been formed, the unconsolidated material is at least partially consolidated. Filler, if any, may be removed from the microcapsules to provide a porous insulative layer or structure. This layer or structure may be configured to support conductive elements or other features of the semiconductor device.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: October 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Tongbi Jiang
  • Patent number: 7279357
    Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: October 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
  • Publication number: 20070232080
    Abstract: A reflow method includes preparing a to-be-processed object, which includes a first layer, a second layer formed in an upper layer to the first layer, and a resist film, which is directly on the second layer and has a pattern allowing formation of an exposure region in which the first layer is exposed and a coverage region in which the first layer is covered, wherein said resist film has an end thereof protruding out further above the exposure region than the edge of the second layer. The resist film has a shape protruding out further above the exposure region than the edge of the second layer. The method also includes covering a part or all of the exposure region by softening and reflowing the resist film.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 4, 2007
    Inventor: Yutaka Asou
  • Publication number: 20070224819
    Abstract: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers which have been formed by a pitch multiplication process in which spacers are formed at the sides of sacrificial mandrels, which are later removed to leave spaced-apart, free-standing spacers. Diblock copolymers, composed of two immiscible block species, are deposited over and in the space between the spacers. The copolymers are made to self-organize, with each block species aggregating with other block species of the same type.
    Type: Application
    Filed: May 3, 2007
    Publication date: September 27, 2007
    Applicant: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Publication number: 20070218706
    Abstract: A heat treating apparatus includes a heating plate for heating a substrate coated with a coating liquid, a cooling plate for cooling the substrate and a heat pipe provided in the cooling plate, a cooling chamber being moved together with the cooling plate by the drive mechanism and accommodating a cooling liquid for cooling one end side of the heat pipe. The apparatus further includes a circulation passage provided in the heat treating apparatus to circulate the cooling liquid in the cooling chamber, a circulation pump for circulating the cooling liquid in the circulation passage; and a heat radiating member provided on the circulation passage to radiate the heat received by the cooling chamber to the outside of the heat treating apparatus.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 20, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Nobuaki Matsuoka
  • Patent number: 7270765
    Abstract: To provide a composition for forming a dielectric layer excellent in dielectric constant and withstand voltage properties, a MIM capacitor and a process for its production. A composition for forming a dielectric layer, which comprises fine particles of perovskite type dielectric crystal, glass frit, and a hydrolysable silicon compound or its oligomer, and a MIM capacitor comprising a substrate, and a bottom electrode layer, a dielectric layer having a structure such that fine particles of perovskite type dielectric crystal are dispersed in a silicon oxide matrix containing glass-forming ions and a top electrode, formed on the substrate in this order.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: September 18, 2007
    Assignee: Asahi Glass Company, Limited
    Inventors: Hiroyuki Tomonaga, Katsuaki Miyatani, Yoshihisa Beppu, Kumiko Takahashi, Kazuo Sunahara
  • Patent number: 7265061
    Abstract: Methods and apparatus for preparing a porous low-k dielectric material on a substrate are provided. The methods optionally involve the use of ultraviolet radiation to react with and remove porogen from a porogen containing precursor film leaving a porous dielectric matrix and further exposing the dielectric matrix to ultraviolet radiation to increase the mechanical strength of the dielectric matrix. Some methods involve activating a gas to create reactive gas species that can clean a reaction chamber. One disclosed apparatus includes an array of multiple ultraviolet sources that can be controlled such that different wavelengths of light can be used to irradiate a sample at a time.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: September 4, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Seon-Mee Cho, Easwar Srinivasan, Brian G. Lu, David Mordo
  • Patent number: 7265063
    Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a component having dielectric sub-layers are described.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: September 4, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Mardilovich, Laura Kramer, Gregory S Herman, Randy Hoffman, David Punsalan
  • Patent number: 7265062
    Abstract: A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: September 4, 2007
    Assignees: Applied Materials, Inc., Air Products and Chemicals, Inc.
    Inventors: Robert P. Mandal, Alexandros T. Demos, Timothy Weidman, Michael P. Nault, Nikolaos Bekiaris, Scott Jeffrey Weigel, Lee A. Senecal, James E. Mac Dougall, Hareesh Thridandam
  • Patent number: 7256146
    Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1?v?0.9, 0?w?0.5, 0.01?x?0.9, 0?y?0.7, 0.01?z?0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: August 14, 2007
    Assignee: International Business Machines Corporation
    Inventors: Stephan A. Cohen, Stephen McConnell Gates, Jeffrey C. Hedrick, Elbert E. Huang, Dirk Pfeiffer
  • Patent number: 7256139
    Abstract: One embodiment of the present invention is a method for fabricating a low-k dielectric film that included steps of: (a) chemical vapor depositing a lower-k dielectric film; and (b) e-beam treating the lower-k dielectric film.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: August 14, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Farhad Moghadam, Jun Zhao, Timothy Weidman, Rick J. Roberts, Li-Quan Xia, Alexandros T. Demos
  • Patent number: 7241704
    Abstract: Methods of preparing a low stress porous low-k dielectric material on a substrate are provided. The methods involve the use of a structure former precursor and/or porogen precursor with one or more organic functional groups. In some cases, the structure former precursor has carbon-carbon double or triple bonds. In other cases, one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. In other cases, the structure former precursor has carbon-carbon double or triple bonds and one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. Once the precursor film is formed, the porogen is removed, leaving a porous low-k dielectric matrix with high mechanical strength. Different types of structure former precursors and porogen precursors are described. The resulting low stress low-k porous film may be used as a low-k dielectric film in integrated circuit manufacturing applications.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: July 10, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Qingguo Wu, Haiying Fu, David C. Smith, David Mordo
  • Patent number: 7238627
    Abstract: Provided is a process for manufacturing an insulating film for a semiconductor device. The process includes preparing a composition for forming an insulating film, wherein the composition comprises a) an organosilicate polymer and b) an organic solvent. The composition is coated on a substrate of a semiconductor device to prepare a coated insulating film, and the coated insulated film is dried and cured. Also provided are an insulating film prepared as described as well as a semiconductor device comprising the insulating film.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: July 3, 2007
    Assignee: LG Chem, Ltd.
    Inventors: Min-Jin Ko, Bum-Gyu Choi, Dong-Seok Shin, Myung-Sun Moon, Jung-Won Kang, Hae-Young Nam, Young-Duk Kim, Gwi-Gwon Kang
  • Patent number: 7232770
    Abstract: A process which uses a silicone resin to form a wafer-to-carrier bonded package that enables wafer thinning and backside processing while the cured resin exhibits high chemical and thermal resistance. The process is versatile in that the constructed wafer package allows for a wide range of chemical exposures to include dilute acid and base etchants, resist and residue strippers, electroplating chemistries, and also providing use in a range of deposition and etch processes that may exceed 300° C. The process utilizes a mixture of silicone monomers that when applied to semiconductor wafers by a spin-coat application, the result is a planarization of the front side device area, and when a subsequent thin coat is applied will facilitate bonding of the wafer-to-carrier package when heat and pressure are applied. The cured silicone bonded wafer-to-carrier package allows for wafer thinning consistent to industry objectives.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: June 19, 2007
    Assignee: General Chemical Performance Products LLC
    Inventors: John C. Moore, Alexander C Smith
  • Patent number: 7232769
    Abstract: The present invention relates to an amorphous silica-based coating film with a low specific dielectric constant of 2.5 or below and the Young's modulus of 6.0 GPa or more and having excellent hydrophobic property, and to a method of forming the same. A liquid composition containing a silicon compound obtained by hydrolyzing tetraalkyl ortho silicate (TAOS) and specific alkoxysilane (AS) in the presence of tetraalkyl ammonium hydroxide (TAAOH) is prepared. The liquid composition is then applied on a substrate, heated and cured to obtain a coating film. The coating film obtained as described has a smooth surface and also has specific micropores therein.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: June 19, 2007
    Assignees: Catalysts & Chemicals Industries Co., Ltd., Fujitsu Limited
    Inventors: Akira Nakashima, Miki Egami, Michio Komatsu, Yoshihiro Nakata, Ei Yano, Katsumi Suzuki
  • Patent number: 7229934
    Abstract: Oxycarbosilane materials make excellent matrix materials for the formation of porous low-k materials using incorporated pore generators(porogens). The elastic modulus numbers measured for porous samples prepared in this fashion are 3–6 times higher than porous organosilicates prepared using the sacrificial porogen route. The oxycarbosilane materials are used to produce integrated circuits for use in electronics devices.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: June 12, 2007
    Assignee: International Business Machines Corporation
    Inventors: Geraud Dubois, James Hedrick, Ho-Cheol Kim, Victor Lee, Teddie Magbitang, Robert Miller, Eva Simonyi, Willi Volksen
  • Patent number: 7226873
    Abstract: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: June 5, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Sung Yen, Kuei-Shun Chen, Chia-Hsiang Lin, Lawrence Lin, Tsung Hsien Lin
  • Patent number: 7223705
    Abstract: A method of modifying the porosity of a thickness of a layer of porous dielectric material having a surface and formed on a semiconductor substrate is provided by exposing the porous dielectric material to a sufficient temperature in the presence of a first gas to drive moisture particles out of the pores. Modifying also includes, exposing the porous dielectric material to a radio frequency stimulus of sufficient power in the presence of a second gas to densify a thickness of the porous dielectric material to reduce or prohibit subsequent absorption of moisture or reactant gas particles by the thickness or porous dielectric material.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Mandyam A. Sriram, Jennifer O'Loughlin
  • Patent number: 7220684
    Abstract: There is included an inorganic insulating film having a porous structure including a cylindrical vacancy oriented in parallel with the surface of a substrate subjected to a hydrophilic treatment or a hydrophobic treatment.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 22, 2007
    Assignee: ROHM Co., Ltd.
    Inventors: Norikazu Nishiyama, Korekazu Ueyama, Yoshiaki Oku
  • Patent number: 7217600
    Abstract: An embodiment is a cyclic olefin semiconductor package. Further an embodiment is a combination of a cyclic olefin monomer and a ruthenium-based catalyst that is stable at approximately room temperature and humidity for extended storage life and pot life, and that can be screen printed or valve/jet deposited.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: May 15, 2007
    Assignee: Intel Corporation
    Inventor: Stephen E. Lehman, Jr.
  • Patent number: 7192891
    Abstract: A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: March 20, 2007
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Ju-Seon Goo, Eun-Kee Hong, Hong-Gun Kim, Kyu-Tae Na
  • Patent number: 7189664
    Abstract: A method for producing hydrogenated silicon oxycarbide (H:SiOC) films having low dielectric constant. The method comprises using plasma-assisted polymerization to react a cyclic silane compound containing at least one strained silicon bond to produce the films. The resulting films are useful in the formation of semiconductor devices.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: March 13, 2007
    Assignee: Dow Corning Corporation
    Inventors: Mark Jon Loboda, Byung Keun Hwang
  • Patent number: 7179399
    Abstract: A material for forming a protective film comprising an organic solvent and a compound having at least two alicyclic structures.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: February 20, 2007
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Jun Koshiyama, Kazumasa Wakiya
  • Patent number: 7179755
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form at least one pore.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Grant M. Kloster, Vijay Ramachandrarao, Hyun-Mog Park
  • Patent number: 7176143
    Abstract: The present invention provides a method for evaluating a solution for a coating film for semiconductor, which comprises measuring Clogging Degree of a solution for a coating film for semiconductor when the solution is filtrated through a filter having an average pore size of 0.01 to 0.4 ?m, and estimating quality of the coating film formed from the solution, wherein the Clogging Degree is defined by the following formula: Clogging Degree=V2/V1 V1: A value of linear velocity of filtrate (filtrating rate per 1 cm2 of filter (g/(cm2·min)) at initial standard point in the case that a solution is filtrated at a fixed pressure and temperature V2: A value of linear velocity of filtrate at the point the predetermined weight of filtrate discharged from the initial standard point According to the present method, quality of coating films can be figured out without actual formation of the coating films, and solutions for coating films can be evaluated thereby.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: February 13, 2007
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yukio Hanamoto, Satoshi Yamamoto
  • Patent number: 7169637
    Abstract: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: January 30, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Lisa H. Stecker, Bruce D. Ulrich, Sheng Teng Hsu
  • Patent number: 7166546
    Abstract: A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: January 23, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Michael F. Brenner
  • Patent number: 7166531
    Abstract: Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: January 23, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Willibrordus Gerardus Maria van den Hoek, Nerissa S. Draeger, Raashina Humayun, Richard S. Hill, Jianing Sun, Gary William Ray
  • Patent number: 7166545
    Abstract: The invention aims at providing a dielectric film having a low dielectric constant and enhanced mechanical strength. A surfactant and an silica derivative are dissolved into a solvent at a desired mole ratio. The precursor solution is applied over the substrate, and the substrate is exposed to a silica derivative atmosphere before being sintered, thereby supplying a silica derivative. Thus, contraction of the film stemming from hydrolysis is inhibited, and a sturdy mesoporous silica thin film which takes the self-assembly of the surfactant as a mold is obtained while cavities are maintained intact without being fractured. Thus, there is formed an inorganic dielectric film which is formed on the surface of the substrate and has a cyclic porous structure including layered or columnar pores oriented so as to become parallel with the surface of the substrate.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: January 23, 2007
    Assignee: Rohm Co., Ltd.
    Inventors: Norikazu Nishiyama, Korekazu Ueyama, Yoshiaki Oku
  • Patent number: 7153754
    Abstract: Methods for forming porous insulative materials for use in forming dielectric structures of semiconductor devices are disclosed. Each insulative material may include a first, substantially nonporous state and a second, porous state. When in the first state, the insulative materials may be processed or support layers or structures which are being processed. When in the second state, the insulative materials have a reduced dielectric constant and, thus, increased electrical insulation properties. Semiconductor device structures including layers or other features formed from one of the insulative materials are also disclosed. Methods for forming the insulative material and for causing the insulative material to become porous are also disclosed.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Tongbi Jiang
  • Patent number: 7153783
    Abstract: The present invention relates to semiconductor device fabrication and more specifically to a method and material for forming high density shallow trench isolation structures in integrated circuits capable of withstanding wet etch treatments. A silica dielectric film is formed on a substrate. The silica dielectric film has a density of from about 1.0 to about 2.3 g/ml, a SiC:SiO bond ratio of about 0.015 or more, a dielectric constant of about 4.0 or less, a breakdown voltage of about 2 MV/cm or more, and a wet etch resistance in a 100:1 by volume mixture of water and hydrogen fluoride of about 30 ?/minute or less.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: December 26, 2006
    Assignee: Honeywell International Inc.
    Inventors: Victor Lu, Lei Jin, Arlene J. Suedmeyer, Denis H. Endisch, Paul G. Apen, Brian J. Daniels, Deling Zhou, Ananth Naman
  • Patent number: 7150956
    Abstract: The present invention provides a resist composition comprising (A) polyhydroxystyrene in which at least a portion of hydrogen atoms of hydroxyl groups are substituted with an acid-dissociable dissolution inhibiting group, and the solubility in an alkali solution of the polyhydroxystyrene increasing when the acid-dissociable dissolution inhibiting group is eliminated by an action of an acid, and (B) a component capable of generating an acid by irradiation with radiation, wherein a retention rate of the acid-dissociable dissolution inhibiting group of the component (A) after a dissociation test using hydrochloric acid is 40% or less, and also provides a chemical amplification type positive resist composition which contains polyhydroxystyrene in which at least a portion of hydrogen atoms of hydroxyl groups are substituted with a lower alkoxy-alkyl group having a straight-chain or branched alkoxy group, and the solubility in an alkali solution of the polyhydroxystyrene increasing when the lower alkoxy-alkyl group
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: December 19, 2006
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Kazuyuki Nitta, Takeyoshi Mimura, Satoshi Shimatani, Waki Okubo, Tatsuya Matsumi
  • Patent number: 7135418
    Abstract: Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-containing precursors. The methods may involve introducing multiple doses of the silicon-containing precursor for each dose of the metal-containing precursor and/or re-pressurizing the process chamber during exposure to a dose of the silicon-containing precursor. The methods of the present invention are particularly suitable for use in RVD processes.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: November 14, 2006
    Assignee: Novellus Systems, Inc.
    Inventor: George D. Papasouliotis
  • Patent number: 7125793
    Abstract: A method of forming an opening in a disclosed ILD is described. The ILD in one embodiment includes a matrix material and a photosensitive porogen. Hard sidewalls are formed in the ILD allowing a thin barrier layer to be used in a dual damascene copper and porous low-k without pore sealing steps.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Huey-Chiang Liou, Wang Yueh
  • Patent number: 7126208
    Abstract: Provided are a composition for forming porous film which can form a porous film having practical mechanical strength in a simple and low cost process; a porous film and a method for forming the film; and an inexpensive, high-performing and highly reliable semiconductor device comprising the porous film inside. More specifically, provided is a composition for forming porous film, comprising a polymer which is obtainable by hydrolyzing and condensing one or more silane compounds represented by Formula (1), or preferably by hydrolyzing and co-condensing one or more silane compounds represented by Formula (1) and one more silane compounds represented by Formula (2), Formulas (1) and (2) being: (R1)aSi(R2)4-a ??(1) (R3)bSi(R4)4-b ??(2) Also provided is a method for forming porous film comprising a step of applying said composition on a substrate to form film and a step of transforming the film into porous film.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 24, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Motoaki Iwabuchi, Fujio Yagihashi, Yoshitaka Hamada, Hideo Nakagawa, Masaru Sasago
  • Patent number: 7122880
    Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: October 17, 2006
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak
  • Patent number: 7119025
    Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Jon Daley, Yoshiki Hishiro
  • Patent number: 7112615
    Abstract: Methods and systems are disclosed for fabricating ultra-low dielectric constant porous materials. In one aspect of the invention, a method for making porous low-k films is disclosed. The method uses polymer based porogens as sacrificial templates around which a chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) deposited matrix is formed. Upon pyrolysis, the porogens decompose resulting in a porous ultra-low dielectric material. This method can be used, for example, to produce porous organosilicate glass (OSG) materials, ultra-low dielectric nanoporous materials, porous ceramics, porous scaffolds, and/or porous metals. Various uses and embodiments of the methods and systems of this invention are disclosed.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: September 26, 2006
    Assignee: Massachusetts Institute of Technology
    Inventors: Karen K. Gleason, Qingguo Wu, April Ross
  • Patent number: 7109129
    Abstract: Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-containing precursors. The methods may involve introducing multiple doses of the silicon-containing precursor for each dose of the metal-containing precursor and/or re-pressurizing the process chamber during exposure to a dose of the silicon-containing precursor. The methods of the present invention are particularly suitable for use in RVD processes.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: September 19, 2006
    Assignee: Novellus Systems, Inc.
    Inventor: George D. Papasouliotis
  • Patent number: 7105452
    Abstract: The present invention provides a method of planarizing a substrate, the method including, forming, on the substrate, a patterned layer having a first shape associated therewith; and processing the patterned layer, with the first shape compensating for variations in the processing such that upon processing the patterned layer, the patterned layer comprises a substantially planar shape.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: September 12, 2006
    Assignee: Molecular Imprints, Inc.
    Inventor: Sidlgata V. Sreenivasan