Abstract: An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.

Abstract: A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a solution processed device are described.

Abstract: An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over said spin-on-glass material (step 214), patterning the photoresist layer (step 214), and etching trench spaces (step 216).

Abstract: Aspects of the invention can provide an ejection method to form a micro lens efficiently on each of a plurality of semiconductor lasers in a wafer state. So that a distance in an x-axis direction between two mutually adjacent sections subject to ejection and a distance between any two nozzles of a plurality of nozzles arranged in the x-axis direction may be in agreement, the ejection method can include a step of positioning a substrate having the two sections subject to ejection, a step of moving relatively the plurality of nozzles along a y-axis direction intersecting the x-axis direction perpendicularly to the substrate, and a step of ejecting a liquid material respectively from the two nozzles to the two sections subject to ejection if the two nozzles should respectively penetrate areas corresponding to the two sections.

Abstract: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing polysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer, a weight average molecular weight within the range of about 3,300 to 3,700 to form a planar SOG layer. The SOG layer is converted to a silicon oxide layer with a planar surface by curing the SOG layer. Also disclosed is a semiconductor device made by the method.

Abstract: A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution.

Abstract: It is an object of the present invention to improve the surface planarity of a film by uniforming the thickness of an insulating layer. Further, it is another object of the invention to provide a technology for manufacturing an electronic device typified by a high-definition and high-quality display device with high yield at low cost with the use of the insulating layer. In a method for manufacturing a semiconductor device according to the invention, a semiconductor layer is formed; an insulating layer is formed over the semiconductor layer; a wiring layer connected to the semiconductor layer is formed in an opening provided in the insulating layer; and an electrode layer connected to the wiring layer is formed. The insulating layer is formed by spin coating with a composition containing an insulating material, which has a viscosity of from 10 mPa·s to 50 mPa·s.

Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1?v?0.9, 0?w?0.5, 0.01?x?0.9, 0?y?0.7, 0.01?z?0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.

Abstract: A material for forming a silica based film which enables the production of a silica based film with a reduced etching rate relative to hydrofluoric acid. This material includes a solid fraction containing a film forming component capable of generating a silica based film, an organic solvent, and water, and the water content of the material, as determined by gas chromatography measurement, is within a range from 0.1 to 50% by weight.

Abstract: Oxycarbosilane materials make excellent matrix materials for the formation of porous low-k materials using incorporated pore generators(porogens). The elastic modulus numbers measured for porous samples prepared in this fashion are 3–6 times higher than porous organosilicates prepared using the sacrificial porogen route. The oxycarbosilane materials are used to produce integrated circuits for use in electronics devices.

Abstract: A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the activated sites. A metallic conductive material can then be plated on the seed layer to form the gate conductor. Semiconductor devices having a gate conductor plated thereon to a width of between about 1 to about 7 nanometers are also provided.

Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H2 and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C.

Abstract: A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device structure and to impart the material with a substantially planar surface and semiconductor device structures formed thereby. The thickness of the material covering the surface is less than the depth of the recesses. The surface may remain substantially uncovered by the material.

Abstract: In a thin film processing method and system, a film thickness is regulated by using electron beams irradiated from a plurality of electron beam tubes onto a film of varying thickness formed on an object to be processed, wherein the output powers or beam irradiation times of the electron beam tubes are individually controlled according to a distribution of the thickness. In the method and system, electric charges charged in a film of an object to be processed can be removed also.

Abstract: A dielectric deposited on a substrate may be exposed to a salt solution. While exposed to the salt solution, an oxide is deposited on the dielectric.

Abstract: A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

Abstract: An organic field effect transistor (FET) is described with an active dielectric layer comprising a low-temperature cured dielectric film of a liquid-deposited silsesquioxane precursor. The dielectric film comprises a silsesquioxane having a dielectric constant of greater than 2. The silsesquioxane dielectric film is advantageously prepared by curing oligomers having alkyl(methyl) and/or alkyl(methyl) pendant groups. The invention also embraces a process for making an organic FET comprising providing a substrate suitable for an organic FET; applying a liquid-phase solution of silsesquioxane precursors over the surface of the substrate; and curing the solution to form a silsesquioxane active dielectric layer. The organic FET thus produced has a high-dielectric, silsesquioxane film with a dielectric constant of greater than about 2, and advantageously, the substrate comprises an indium-tin oxide coated plastic substrate.

Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

Abstract: A method of manufacturing a structure in which a substrate can be removed easily from a structure that has been formed on the substrate by using a film forming technology. The method of manufacturing a structure includes the steps of (a) forming an intermediate layer on a substrate; (b) forming a structure including a brittle material layer on the intermediate layer by at least using a spray deposition method of spraying material powder toward the substrate, on which the intermediate layer is formed, to deposit the material powder; and (c) removing the substrate from the structure.

Abstract: A method is provided for manufacturing a capacitor including the steps of forming a lower electrode on a substrate, forming an insulation film formed of a perovskite type metal oxide on the lower electrode, and forming an upper electrode on the insulation film. The step of forming the insulation film includes the steps of coating a dispersion liquid in which fine crystal powder of a second metal oxide of a perovskite type in a liquid containing a precursor compound of a first metal oxide of a perovskite type on the lower electrode, and performing a heat treatment of the dispersion liquid after coating.

Abstract: Methods of preparing a low-k dielectric material on a substrate are provided. The methods involve using plasma techniques to remove porogen from a precursor layer comprising porogen and a dielectric matrix and to protect the dielectric matrix with a silanol capping agent, resulting in a low-k dielectric matrix. Porogen removal and silanol capping can occur concurrently or sequentially. If performed sequentially, silanol capping is performed without first exposing the dielectric matrix to moisture or ambient conditions.

Abstract: A method of depositing polymer thin films on a MEMS device having a wafer stack includes depositing one or more protection films on a polymer thin film layer on the wafer stack, fabricating the MEMS device, and removing the one or more protection films.

Abstract: A substrate processing apparatus has a substrate holder for detachably holding a substrate so that a surface, to be processed, of the substrate faces downward, and a sealing ring for sealing a peripheral portion of the surface, to be processed, of the substrate held by the substrate holder. The substrate processing apparatus also has a plurality of ejection nozzles disposed below the substrate holder for ejecting a treatment solution toward the surface, to be processed, of the substrate held by the substrate holder, and a mechanism for rotating and vertically moving the substrate holder and the ejection nozzles relative to each other.

Abstract: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

Abstract: The invention aims at providing a dielectric film having a low dielectric constant and enhanced mechanical strength. A surfactant and an silica derivative are dissolved into a solvent at a desired mole ratio. The precursor solution is applied over the substrate, and the substrate is exposed to a silica derivative atmosphere before being sintered, thereby supplying a silica derivative. Thus, contraction of the film stemming from hydrolysis is inhibited, and a sturdy mesoporous silica thin film which takes the self-assembly of the surfactant as a mold is obtained while cavities are maintained intact without being fractured. Thus, there is formed an inorganic dielectric film which is formed on the surface of the substrate and has a cyclic porous structure including layered or columnar pores oriented so as to become parallel with the surface of the substrate.

Abstract: A method of forming a layer of photoresist 28 over a surface 30 of a semiconductor wafer 10 by forming a layer of pre-wet solvent 52 over the surface 30 and forming the layer of photoresist 28 over the layer of pre-wet solvent 52. Also, a layer of photoresist 28 formed by this method.

Abstract: A process-oriented modulized plant for TFT-LCD fabrication capable of preventing cross contaminations is proposed. A plant includes a plurality of independent fabs and warehouses connected between the fabs. Each independent fab can carry out at least one TFT-LCD processes. The respective process used in the first independent fab produces the first group of contaminants. Another respective processes carried out in the second independent fab are affected by the contaminations from the first group of contaminants and results in deterioration of yield rate of the fabrication. At least one automatic transport-and-storage system for central collection and distribution is located in each warehouse. Each warehouse is connected to the independent fabs via at least one automated material handling system to link up the processes together.

Abstract: The invention provides a method of forming a high-performance thin-film at low cost using a liquid material in safety, an apparatus to form a thin-film, a method of manufacturing a semiconductor device, an electro-optical unit, and an electronic apparatus. An apparatus to form a thin-film includes a coating unit to apply a liquid material containing a thin-film component onto a substrate and also includes heat-treating units to heat the substrate applied with the liquid material. The coating unit and the heat-treating units each include a control device to control the atmosphere in a treating chamber to treat the substrate.

Abstract: Single crystal silicon is grown in a [100] direction to make a bulk. Next, a silicon substrate with a normal of a surface extending in an inclined direction from a [100] direction is cut from the bulk. At this time, when an angle (off-angle) of inclination of the normal is decomposed into a component in a [001] direction and a component in a [010] direction, the component in the [001] direction is made within ±0.2 degrees (excluding 0 degree). An MOS transistor with a moving direction of carriers being the [001] direction is formed on the surface of the silicon substrate. At this time, after steps existing on the surface of the silicon substrate are reconstituted by thermal treatment in a hydrogen atmosphere, a gate insulation film, a gate electrode and the like are formed.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: A drawing device is provided that applies drawing liquid containing a drawing material dissolved or dispersed in a solvent onto a substrate. The drawing device includes a liquid drop emitter having a liquid drop ejection head that ejects the drawing liquid onto the surface of the substrate, a substrate stage having the substrate mounted thereon, moving means for relatively moving the liquid drop ejection head or the substrate stage, and control means for controlling at least one of the liquid drop ejection head and the substrate stage. A wall is disposed on at least one of the liquid drop ejection head and the substrate stage to prevent the solvent from flowing out.

Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.

Abstract: Methods and systems are disclosed for fabricating ultra-low dielectric constant porous materials. In one aspect of the invention, a method for making porous low-k films is disclosed. The method uses polymer based porogens as sacrificial templates around which a chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) deposited matrix is formed. Upon pyrolysis, the porogens decompose resulting in a porous ultra-low dielectric material. This method can be used, for example, to produce porous organosilicate glass (OSG) materials, ultra-low dielectric nanoporous materials, porous ceramics, porous scaffolds, and/or porous metals. Various uses and embodiments of the methods and systems of this invention are disclosed.

Abstract: Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.

Abstract: Provided herein is a substrate processing system, which comprises a cassette load station; a load lock chamber; a centrally located transfer chamber; and one or more process chambers located about the periphery of the transfer chamber. The load lock chamber comprises double dual slot load locks constructed at same location. Such system may be used for processing substrates for semiconductor manufacturing.

Abstract: A method of patterning organic semiconductor layers of electronic devices utilizing reverse printing.

Abstract: A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device structure and to impart the material with a substantially planar surface and semiconductor device structures formed thereby. The thickness of the material covering the surface is less than the depth of the recesses. The surface may remain substantially uncovered by the material.

Abstract: A method of making a film with a high dielectric constant uses a spin-on sol-gel process to deposit the film on a substrate, the film having a composition (SiO2)x(TiO2)1?x, where 0.50<x<0.75. The resulting film is annealed in an oxygen-containing atmosphere at a temperature lying in the range of 500° C. to 700° C.

Abstract: A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.

Abstract: A liquid form adhesive system is provided for spin-coating on wafers and mounting to rigid carrier substrates to support thinning and backside processing. The liquid adhesive comprises about 30–35% of a rosin, between 5–10% of a thermoplastic urethane, a nonionic surfactant present between 1–3%, and a trace of an ultraviolet fluorescing dye. The entire system is dissolved in 50–65%, by weight, of a dual solvent mixture composed of dimethylacetamide and propylene glycol monomethyl ether. When the mixture is made to a specific viscosity, filtered, applied by a spin-coating method to the wafer frontside surface, and cured, the result is a uniform and smooth surface of defined thickness. When the coated wafer is mounted to a rigid substrate, it may be mechanically thinned to thicknesses down to and beyond 25 um, depending upon the wafer composition, diameter, and process.

Abstract: A method of CaO-doped SrCu2O2 spin-on precursor synthesis and low temperature p-type thin film deposition, includes preparing a wafer to receive a spin-coating thereon; selecting metalorganic compounds to form a SrCu2O2 precursor, mixing and refluxing the metalorganic compounds to form a precursor mixture; filtering the precursor mixture to produce a spin-coating precursor; applying the spin-coating precursor to the wafer in a two-step spin coating procedure; baking the spin-coated wafer using a hot-plate bake to evaporate substantially all of the solvents; and annealing the spin-coated wafer to form a CaO-doped SrCu2O2 layer thereon.

Abstract: A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of the coupled wafers, and using a vacuum to aid in the dispersion of the material.

Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.

Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.

Abstract: The resist application method comprises the steps of: thermal processing for evaporating water from the surface of a wafer 10; making the surface of the wafer 10 hydrophobic with a hydrophobic processing material; and applying a resist onto the wafer 10, and the step of thermal processing to the step of making the surface of the wafer 10 hydrophobic are performed in a dehumidified atmosphere.

Abstract: The present invention provides a solid state light-emissive display apparatus of high brightness and efficiency, high reliability, and of thin type, and method of manufacturing the same at low cost. Said apparatus has the luminous thin film made up by laminating or mixing crystal fine particle coated with insulator (5) of nm size and fluorescent fine particles (7) of nm size, and the lower electrode and the transparent upper electrode sandwiching said luminous thin film, wherein the electrons injected from said lower electrode are accelerated in the crystal fine particle coated with insulator layer (6) not being scattered by phonons to become high energy ballistic electrons, and form excitons (13) by colliding excitation of fluorescent fine particles. Since said fluorescent fine particles are of nm size, the exciton concentration is high, and luminescence intensity by extinction of excitons is also high.

Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.

Abstract: In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiO2 thermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.