With Substrate Handling During Coating (e.g., Immersion, Spinning, Etc.) Patents (Class 438/782)
  • Patent number: 7026260
    Abstract: A technique capable of preventing breakage of a semiconductor wafer in a single-wafer RTP apparatus is provided. Open-loop control is made in a temperature rising process, in which the temperature of the semiconductor wafer is 500° C. or lower, and a revolution speed of the semiconductor wafer is relatively reduced to 100 rpm or lower even if the bowing of the semiconductor wafer occurs. Therefore, a centrifugal force exerted on the semiconductor wafer is reduced, whereby it becomes possible to prevent the semiconductor wafer from dropping from a stage of the single-wafer RTP apparatus. Additionally, closed-loop control is made in the temperature rising process, in which the temperature of the semiconductor wafer is higher than 500° C., and in a main treatment process, and further the revolution speed of the semiconductor wafer is relatively increased. By so doing, the almost uniform in-plane temperature of the semiconductor wafer can be achieved and the bowing of the semiconductor wafer can be prevented.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: April 11, 2006
    Assignee: Trecenti Technologies, Inc.
    Inventor: Mikio Shimizu
  • Patent number: 7022541
    Abstract: A wafer-scale fabrication approach for manufacturing single-walled carbon nanotube (SWNT) tips is implemented. Catalyst material is selectively placed (e.g., patterned) onto a plurality of prefabricated elevated structures (e.g., silicon tips) on a wafer. SWNTs are grown protruding from the catalyst on the elevated structures. The resulting SWNT protruding from a tip can be implemented in a variety of applications, such as in atomic force microscopy (AFM). With this approach, nanotube tips can be implemented for a variety of applications, including advanced nanoscale imaging, imaging of solid-state and soft biological systems and for scanning probe lithography.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: April 4, 2006
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Erhan Yenilmez, Hongjie Dai
  • Patent number: 7018943
    Abstract: A method of and an apparatus for coating a substrate with a polymer solution to produce a film of uniform thickness, includes mounting the substrate inside an enclosed housing and passing a control gas, which may be a solvent vapor-bearing gas into the housing through an inlet. The polymer solution is deposited onto the surface of the substrate in the housing and the substrate is then spun. The control gas and any solvent vapor and particulate contaminants suspended in the control gas are exhausted from the housing through an outlet and the solvent vapor concentration is controlled by controlling the temperature of the housing and the solvent from which the solvent vapor-bearing gas is produced. Instead the concentration can be controlled by mixing gases having different solvent concentrations. The humidity of the gas may also be controlled.
    Type: Grant
    Filed: June 30, 2001
    Date of Patent: March 28, 2006
    Assignee: ASML Holding N.V.
    Inventors: Gurer Emir, Tom Zhong, John Lewellen, Edward C. Lee, Robert P. Mandal, James C. Grambow, Ted C. Bettes, Donald R. Sauer, Edmond R. Ward
  • Patent number: 7013555
    Abstract: The present invention discloses a method of providing an integral thermal interface on an interface surface of a heat dissipation device, such as a heat sink. In accordance with the present invention, the phase change material is applied directly onto the interface surface of the heat sink to form an integral interface layer directly on the heat sink during the manufacturing process. This process includes the steps of providing a heat dissipating device having an interface surface, liquefying the phase change material at a controlled temperature so as to decrease the material viscosity to a flowable form, applying the liquefied phase change material directly onto the mating surface of the heat dissipating device either by directly dispensing the material, screen printing or stencil printing and cooling the material causing it to cure on the surface of the heat dissipating device.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: March 21, 2006
    Assignee: Cool Shield, Inc.
    Inventor: Kevin A. McCullough
  • Patent number: 7008884
    Abstract: A transfer robot (5) for thin substrate capable of efficiently detecting the stored state of thin substrates and an inspection method for thin substrate capable of accurately detecting the stored state of thin substrates; the robot (5), comprising an inspection camera (1) for detecting the stored state of the thin substrates (3) in a storage cassette (2), wherein the plurality of thin substrates (3) stored in the storage cassette (2) are carried out from the storage cassette (2) by the robot.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: March 7, 2006
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Hitoshi Wakizako, Kazunari Shiraishi, Yukito Sagasaki, Ken-ichi Motonaga, Kazunori Hino, Hiroki Sanemasa
  • Patent number: 6998216
    Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventors: Jun He, Jihperng Leu
  • Patent number: 6992024
    Abstract: A method of filling a plurality of trenches etched in a substrate. In one embodiment the method includes depositing a layer of spin-on glass material over the substrate and into the plurality of trenches; exposing the layer of spin-on glass material to a solvent; curing the layer of spin-on glass material; and depositing a layer of silica glass over the cured spin-on glass layer using a chemical vapor deposition technique.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: January 31, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, Rick J. Roberts, Michael S. Cox, Jun Zhao
  • Patent number: 6992023
    Abstract: The invention provides methods and apparatus for drying the backside of semiconductor wafers in a spin-coating environment. Solvent is evaporatively dried from a semiconductor wafer held in a spin mechanism. The undried wafer is sprayed with one or more jets of pressurized gas from gas ports disposed about the spin mechanism.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: David C. Hall
  • Patent number: 6987070
    Abstract: Disclosed is a method for forming a low-k dielectric layer of a semiconductor device. The method includes a step providing a semiconductor substrate having a predetermined pattern, a step coating porous powders having a micro size on the semiconductor by spraying the porous powders, and a step performing a heat treatment process with respect to a resultant structure, thereby forming the low-k dielectric layer. After micro-sized porous powders are coated on a semiconductor substrate, a heat treatment process is performed, so that powders are bonded to each other, thereby forming a low-k dielectric layer even if the dielectric layer has a dielectric constant equal to or less than 2.8. A signal delay time is reduced by depositing the low-k dielectric layer on the semiconductor substrate.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: January 17, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Sun Maeng
  • Patent number: 6974776
    Abstract: The invention provides a method of plating an integrated circuit. An activation plate is positioned adjacent to at least one integrated circuit. The integrated circuit includes a plurality of bond pads comprising a bond-pad metal, and the activation plate also comprises the bond-pad metal. A layer of electroless nickel is plated on the bond pads and the activation plate, and a layer of gold is plated over the layer of electroless nickel on the bond pads and the activation plate. An integrated circuit with bond pads plated using the activation plate, and a system for plating an integrated circuit is also disclosed.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: December 13, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Timothy B. Dean, William H. Lytle
  • Patent number: 6974762
    Abstract: A method of silanizing the surface of a low-k interlayer dielectric oxides (carbon doped oxides or organo-silicate glasses) to improve surface adhesion to adjacent thin film layers in damascene integration of microelectronic devices. A low-k interlayer dielectric oxide may be exposed to the vapor of a silane-coupling agent in order to modify its surface energy to improve adhesion with adjacent thin film layers. A low-k interlayer dielectric oxide can also be silanized by dipping the low-k interlayer dielectric oxide in a solution of silane-coupling agent. The silane-coupling agent will cause covalent bonds between the low-k interlayer dielectric oxide and the adjacent thin film thereby improving adhesion.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: David H. Gracias, Vijayakumar S. Ramachandrarao
  • Patent number: 6960540
    Abstract: Relative movement occurs between the in-process substrate and the dropping section. While the substrate is rotated, the dropping section is relatively moved from an approximate center of the substrate toward an outer periphery thereof. While the dropping section relatively moves from the approximate center of the in-process substrate toward the outer periphery, the rotational frequency w for the substrate is decreased so that the solution film should not move due to the centrifugal force applied to a dropped solution film. Concurrently, feed rate v for the liquid from the dropping section is increased to form a solution film on the in-process substrate.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: November 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Ito, Katsuya Okumura
  • Patent number: 6951802
    Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: October 4, 2005
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
  • Patent number: 6946407
    Abstract: A method is provided for more efficient application of a polymeric coating (e.g., die coat) to a substrate (e.g., wafer) surface. One aspect of the method comprises applying an organic liquid (e.g., organic solvent) to the wafer and spinning it to coat the entire wafer surface prior to the application of die coat. This reduces surface tension on the wafer and reduces the amount of die coat required to achieve a high quality film.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: September 20, 2005
    Assignee: Micron Technology, Inc.
    Inventors: John T. Davlin, Douglas S. Schramm, Lorna M. Mitson
  • Patent number: 6943117
    Abstract: A UV nanoimprint lithography process for forming nanostructures on a substrate. The process includes depositing a resist on a substrate; contacting a stamp having formed thereon nanostructures at areas corresponding to where nanostructures on the substrate are to be formed to an upper surface of the resist, and applying a predetermined pressure to the stamp in a direction toward the substrate, the contacting and applying being performed at room temperature and at low pressure; irradiating ultraviolet rays onto the resist; separating the stamp from the resist; and etching an upper surface of the substrate on which the resist is deposited. The stamp is an elementwise embossed stamp that comprises at least two element stamps, and grooves formed between adjacent element stamps and having a depth that is greater than a depth of the nanostructures formed on the element stamps.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: September 13, 2005
    Assignee: Korea Institute of Machinery & Materials
    Inventors: Jun-Ho Jeong, HyonKee Sohn, Young-Suk Sim, Young-Jae Shin, Eung-Sug Lee, Kyung-Hyun Whang
  • Patent number: 6930046
    Abstract: A system and method for processing a workpiece, includes workpiece processors. A robot is moveable within an enclosure to load and unload workpieces into and out of the processors. A processor includes an upper rotor having a central air flow opening. The upper rotor is magnetically driven into engagement with a lower rotor to form a workpiece processing chamber. A moveable drain mechanism aligns different drain paths with the processing chamber so that different processing fluids may be removed from the processing chamber via different drain paths. A moveable nozzle positioned in the air flow opening distributes processing fluid to the workpiece. The processing fluid is distributed across the workpiece surface, via centrifugal force generated by spinning the processing chamber, and removed from the processing chamber via the moveable drain mechanism.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: August 16, 2005
    Assignee: Semitool, Inc.
    Inventors: Kyle M. Hanson, Eric Lund, Coby Grove, Steven L. Peace, Paul Z. Wirth, Scott A. Bruner, Jonathan Kuntz
  • Patent number: 6927181
    Abstract: A transfer robot (5) for thin substrate capable of efficiently detecting the stored state of thin substrates and an inspection method for thin substrate capable of accurately detecting the stored state of thin substrates; the robot (5), comprising an inspection camera (1) for detecting the stored state of the thin substrates (3) in a storage cassette (2), wherein the plurality of thin substrates (3) stored in the storage cassette (2) are carried out from the storage cassette (2) by the robot.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: August 9, 2005
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Hitoshi Wakizako, Kazunari Shiraishi, Yukito Sagasaki, Ken-ichi Motonaga, Kazunori Hino, Hiroki Sanemasa
  • Patent number: 6921621
    Abstract: The present invention provides a resist composition comprising (A) polyhydroxystyrene in which at least a portion of hydrogen atoms of hydroxyl groups are substituted with an acid-dissociable dissolution inhibiting group, and the solubility in an alkali solution of the polyhydroxystyrene increasing when the acid-dissociable dissolution inhibiting group is eliminated by an action of an acid, and (B) a component capable of generating an acid by irradiation with radiation, wherein a retention rate of the acid-dissociable dissolution inhibiting group of the component (A) after a dissociation test using hydrochloric acid is 40% or less, and also provides a chemical amplification type positive resist composition which contains polyhydroxystyrene in which at least a portion of hydrogen atoms of hydroxyl groups are substituted with a lower alkoxy-alkyl group having a straight-chain or branched alkoxy group, and the solubility in an alkali solution of the polyhydroxystyrene increasing when the lower alkoxy-alkyl group
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: July 26, 2005
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Kazuyuki Nitta, Takeyoshi Mimura, Satoshi Shimatani, Waki Okubo, Tatsuya Matsumi
  • Patent number: 6919283
    Abstract: This invention is directed to pure and modified Ta2O5 thin films deposited on suitable substrate and methods for making these Ta2O5 thin films. These Ta2O5 thin films exhibit superior properties for microwave communication, dynamic random access memory and integrated electronic applications. The Ta2O5 thin films perform well in these types of technologies due to the Ta 2O5 thin film component which allows for high dielectric constants, low dielectric loss, and good temperature and frequency stability, thus making them particularly useful in high frequency microwave applications.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: July 19, 2005
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pooran C. Joshi
  • Patent number: 6919277
    Abstract: Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: July 19, 2005
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak
  • Patent number: 6903030
    Abstract: A supply system in a heat-treating apparatus for a semiconductor process has a combustor (12), heating unit (13), and gas distributor (14). The combustor (12) has a combustion chamber (59) disposed outside a process chamber (21). The combustor (12) generates water vapor by reaction of hydrogen gas and oxygen gas in the combustion chamber (59), and supplies it to the process chamber (21). The heating unit (13) has a heating chamber (61) disposed outside the process chamber (21). The heating unit (13) selectively heats a gas not passing through the combustion chamber (59) to a temperature not lower than an activating temperature of the gas, and supplies it to the process chamber (21). The gas distributor (14) selectively supplies the hydrogen gas and oxygen gas to the combustion chamber (59), and selectively supplies a reactive gas and inactive gas to the heating chamber (61).
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: June 7, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Katsutoshi Ishii, Yutaka Takahashi, Harunari Hasegawa
  • Patent number: 6900132
    Abstract: A system for processing semiconductor wafers has process units on a deck of a frame. The process units and the deck have precision locating features, such as tapered pins, for precisely positioning the process units on the deck. Process units can be removed and replacement process units installed on the deck, without the need for recalibrating the load/unload robot. This reduces the time needed to replace process units and restart processing operations. Liquid chemical consumption during processing is reduced by drawing unused liquid out of supply lines and pumping it back to storage.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: May 31, 2005
    Assignee: Semitool, Inc.
    Inventors: Raymon F. Thompson, Jeffry A. Davis, Randy Harris, Dana R. Scranton, Ryan Pfeifle, Steven A. Peace, Brian Aegerter
  • Patent number: 6893805
    Abstract: A substrate processing apparatus provided with: a coating processing section for supplying a coating solution to a substrate; a pressure processing section for pressurizing a coating film formed on the substrate; and a developing processing section for supplying a developing solution to the substrate having the coating film selectively exposed to light with the use of an exposure mask. The pressure processing section may be arranged such that a pressing plate having a flat face is brought into pressure contact with the coating film.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: May 17, 2005
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Izuru Iseki, Tsutomu Ueyama
  • Patent number: 6890595
    Abstract: A method for coating low viscosity materials onto a wafer to form a uniform film. After a wafer is rotated at a first rotation speed, coating solution is dispensed onto the wafer. The wafer is decelerated to a second rotation speed at a first deceleration rate to spread the coating solution. Next, the wafer is slowly decelerated to a third rotation speed at a second deceleration rate considerably lower than the first deceleration rate, so the coating solution reflows to the center of the wafer. The wafer is then quickly accelerated to a fourth rotation speed at a third acceleration rate larger than the first deceleration rate to spread the coating solution again.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: May 10, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Ai-Yi Lee, Wen-Chi Chang
  • Patent number: 6887801
    Abstract: Methods and devices for handling wafers during wafer processing are provided. One embodiment includes an apparatus for holding a wafer. The holding apparatus includes a pocket for receiving a wafer, and may include a mechanism allowing for the wafer to be secured within the pocket. Methods are also included for preparing a wafer for fabrication processes by the use of a wafer holding apparatus. These methods may include applying a layer of photoresist to the surface of a wafer.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: May 3, 2005
    Assignee: Finisar Corporation
    Inventor: Bernard Q. Li
  • Patent number: 6884718
    Abstract: An apparatus and process for depositing a barrier film on a substrate is disclosed. In particular, deposition of the barrier film is carried out on the substrate having an applied pressure. This applied pressure flexes the substrate to reduce in-plane stresses, wherein removal of the applied pressure after deposition of the barrier film modifies the in-film stress for the thin-film. With the above-described arrangement, it is possible to minimize the deterioration of electric characteristics of a semiconductor device and the occurrence of defects, such as film delamination, substrate cracks, and the like.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: April 26, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Cem Basceri
  • Patent number: 6884294
    Abstract: A coating solution is sprayed on a rotating wafer held horizontally from a nozzle provided above the wafer while the nozzle is travelling over the wafer from a wafer center to a wafer outer area, thus spirally spraying the coating solution on the wafer. The nozzle stops when the coating solution has reached the wafer outer area and the coating solution is sprayed in circle on the wafer outer area while the wafer is rotating. A coating solution including a component of a coating film and a solvent may be sprayed on a first area to be coated of the wafer and the coating solution and a solvent for the coating film may be sprayed on a second edge area located outside the first area of the wafer.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: April 26, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Tomohide Minami, Shinichi Sugimoto, Takahiro Kitano, Jun Ookura, Hiroaki Kurishima
  • Patent number: 6884462
    Abstract: A method and apparatus is provided for more efficient application of photoresist to a wafer surface. One aspect of the method comprises applying solvent to the wafer and spinning it to coat the entire wafer surface prior to the application of photoresist. This reduces surface tension on the wafer and reduces the amount of resist required to achieve a high quality film. The apparatus comprises adding a third solenoid and nozzle to the coating unit to accommodate the application of solvent to the center of the wafer surface. The method also describes incorporating a new solvent comprising diacetone alcohol, which is a low-pressure solvent, providing extended process latitudes and reduced material expenditures.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: April 26, 2005
    Assignee: Micron Technology, Inc.
    Inventor: John Whitman
  • Patent number: 6881590
    Abstract: First, a spin-on process is performed for forming a first dielectric layer over a plurality of metal interconnecting wires that are located on a semiconductor wafer. Then, an examining step is performed on the first dielectric layer, and the first dielectric layer is made to conform to a predetermined condition. Thereafter, an etching process is performed for completely removing the first dielectric layer. Subsequently, the semiconductor wafer is cleaned through use of a wet scrubber, and is dried. Finally, the spin-on process is re-performed for forming a second dielectric layer on the semiconductor wafer.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: April 19, 2005
    Assignee: Powerchip Semiconductor Corp.
    Inventor: Ching-Hsiu Wu
  • Patent number: 6878644
    Abstract: A method of filling a plurality of trenches etched in a substrate. In one embodiment the method includes depositing a layer of spin-on glass material over the substrate and into the plurality of trenches; curing the layer of spin-on glass material by exposing the spin-on glass material to electron beam radiation at a first temperature for a first period and subsequently exposing the spin-on glass material to an electron beam at a second temperature for a second period, where the second temperature is greater than the first temperature. The method concludes by depositing a layer of silica glass over the cured spin-on glass layer using a chemical vapor deposition technique.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: April 12, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, Rick J. Roberts, Michael S. Cox, Jun Zhao, Khaled Elsheref, Alexandros T. Demos
  • Patent number: 6878401
    Abstract: A specific amount of a processing solution is supplied on a wafer by spraying the processing solution from a first end (tip) of a nozzle. The solution surface of the processing solution remaining in the nozzle is sucked back to a second end side of the nozzle by aspirating the remaining processing solution to the second end side. The first end of the nozzle is then soaked into a fluid. The processing solution remaining in the nozzle is aspirated to the second end side to aspirate a specific amount of the fluid into the first end of the nozzle for further sucking back the solution surface of the processing solution to the second end side, thus the solution surface of the processing solution being not touching the fluid.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: April 12, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhiro Nishijima, Tsuyoshi Mizuno
  • Patent number: 6875640
    Abstract: A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: April 5, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood
  • Patent number: 6875709
    Abstract: A method and apparatus for curing and modifying a low k dielectric layer in an interconnect structure is disclosed. A spin-on low k dielectric layer which includes an organic silsesquioxane, polyarylether, bisbenzocyclobuene, or SiLK is spin coated on a substrate. The substrate is placed in a process chamber in a supercritical CO2 system and is treated at a temperature between 30° C. and 150° C. and at a pressure from 70 to 700 atmospheres. A co-solvent such as CF3—X or F—X is added that selectively replaces C—CH3 bonds with C—CF3 or C—F bonds. Alternatively, H2O2 is employed as co-solvent to replace a halogen in a C—Z bond where Z=F, Cl, or Br with an hydroxyl group. Two co-solvents may be combined with CO2 for more flexibility. The cured dielectric layer has improved properties that include better adhesion, lower k value, increased hardness, and a higher elastic modulus.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: April 5, 2005
    Assignee: Taiwan Semiconductor Manufacturing Comapny, Ltd.
    Inventors: Chun-Hsien Lin, Henry Lo, Anthony Liu, Yu-Liang Lin
  • Patent number: 6875642
    Abstract: A method for manufacturing thin film and a thin film. The method comprises dipping a substrate in a solution that dries up forming a layer on the surface of the substrate and controlling layer thickness by changing the rate of dipping the substrate in the solution. Before the next dipping after the first dipping, the position of the substrate is changed such that the next dipping will be carried out in a direction which is at an angle to the direction of the previous dipping.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: April 5, 2005
    Assignee: Janesko Oy
    Inventor: Ville Voipio
  • Patent number: 6872598
    Abstract: A semiconductor device wafer 11 is integrated with a supporting board 13 by a double-faced thermally foaming adhesive sheet 12, and this assembly is fixed to a vacuum sucking pedestal 14 under vacuum sucking. A thermally foaming adhesive layer of the adhesive sheet 12 functions as a shock absorber, whereby the wafer 11 hardly cracks during a high-speed grinding operation even if the wafer uses a GaAs substrate which is susceptible to damages. Neither fixing of the wafer 11 using wax nor abrasion using an oil abrasive agent is necessary, so that contamination of wax and oil is prevented and cleaning of the wafer becomes easy. Heating at 130° C. makes the thermally foaming adhesive layer of the adhesive sheet 12 expand so that the wafer 11 is readily separated from the adhesive sheet.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: March 29, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yi Liu
  • Patent number: 6872418
    Abstract: A method for forming a film using a rotating cup application apparatus in which a rotatable inner cup is provided within an outer cup, the upper openings of the inner cup and the outer cup are closed with corresponding lids, and the lid for the inner cup is integrally rotated together with the inner cup, the method comprising the steps of setting a material to be treated, on which wiring layers have been formed, in the rotating cup application apparatus, applying SOG onto the surface of the material to be treated, thereafter closing the upper openings of the inner cup and the outer cup with the lids, rotating the inner cup in this state to thereby uniformly diffusing the SOG, repeating the SOG application and diffusing steps, and thereafter baking the material to be treated in a heat treatment apparatus.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: March 29, 2005
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventor: Hiroki Endo
  • Patent number: 6869894
    Abstract: A liquid form adhesive system is provided for spin-coating on wafers and mounting to rigid carrier substrates to support thinning and backside processing. The liquid adhesive comprises about 30-35% of a rosin, between 5-10% of a thermoplastic urethane, a nonionic surfactant present between 1-3%, and a trace of an ultraviolet fluorescing dye. The entire system is dissolved in 50-65%, by weight, of a dual solvent mixture composed of dimethylacetamide and propylene glycol monomethyl ether. When the mixture is made to a specific viscosity, filtered, applied by a spin-coating method to the wafer frontside surface, and cured, the result is a uniform and smooth surface of defined thickness. When the coated wafer is mounted to a rigid substrate, it may be mechanically thinned to thicknesses down to and beyond 25 um, depending upon the wafer composition, diameter, and process.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: March 22, 2005
    Assignee: General Chemical Corporation
    Inventor: John C. Moore
  • Patent number: 6869640
    Abstract: A coating film is formed by the steps of supplying a mixture of a solvent for dissolving a coating liquid and a volatilization suppressing substance for suppressing the volatilization of the solvent onto the surface of the target substrate W, expanding the mixture onto the entire surface of the target substrate W, and supplying a coating liquid onto substantially the central portion of the target substrate W that has received the mixture while rotating the target substrate W thereby expanding the coating liquid outward in the radial direction of the target substrate W thereby forming a coating film.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: March 22, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Kousuke Yoshihara, Yuichi Terashita
  • Patent number: 6867150
    Abstract: The invention concerns an ozone treatment method and an ozone treatment apparatus for performing a treatment such as the formation and reformation of an oxide film, the removal of a resist film by blowing an ozone gas onto a surface of a substrate such as a semiconductor substrate or liquid crystal substrate. The ozone treatment apparatus 1 includes: a placement table 20 on which the substrate K is placed; a heating unit for heating the substrate K placed on the placement table 20; an opposed plate 40, disposed opposite the substrate K, for discharging the ozone gas through a discharge port 44 formed in a surface facing the substrate K, a gas feeding means 43 for feeding the ozone gas into the discharge port 44; a lifter 30 for moving the placement table 20 up and down; and a control unit 35 for controlling the operation of said lifter 30.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: March 15, 2005
    Assignee: Sumitomo Precision Products Co., Ltd.
    Inventors: Tatsuo Kikuchi, Takeo Yamanaka, Yukitaka Yamaguchi, Tokiko Kanayama
  • Patent number: 6867126
    Abstract: A method of increasing the cracking threshold of a low-k material layer comprising the following steps. A substrate having a low-k material layer formed thereover is provided. The low-k material layer having a cracking threshold. The low-k material layer is plasma treated to increase the low-k material layer cracking threshold. The plasma treatment including a gas that is CO2, He, NH3 or combinations thereof.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: March 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lih-Ping Li, Yung-Chen Lu, Chung-Chi Ko
  • Patent number: 6864561
    Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 8, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Ravi Iyer, Randhir P. S. Thakur, Howard E. Rhodes
  • Patent number: 6864192
    Abstract: A Langmuir-Blodgett film may be utilized as a chemically amplified photoresist layer. Langmuir-Blodgett films have highly vertically oriented structures which may be effective in reducing line edge or line width roughness in chemically amplified photoresists.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: March 8, 2005
    Assignee: Intel Corporation
    Inventors: Huey-Chiang Liou, Hai Deng, Wang Yueh, Hok-Kin Choi
  • Patent number: 6849293
    Abstract: A method for spin coating a polymeric material film upon a wafer rotatably mounted within a spin coater; the wafer having a surface, including the following steps. A first step of rotating the wafer on an axis perpendicular to the wafer surface while applying a predetermined amount of polymeric material while rotating the wafer at a rotational speed of from about 300 to 1200 rpm for from about 2.5 to 5 seconds to spread the polymeric material on the whole surface of the wafer. A second step of increasing the rotational speed of the wafer to about 5500 rpm for about 2.5 seconds. A third step of decreasing the rotational speed of the wafer to about 300 to 1200 rpm for about 2.5 seconds. A fourth step of increasing the rotational speed of the wafer to about 5500 rpm for about 20 seconds to form the polymeric material film having a predetermined thickness over the whole surface of the wafer.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: February 1, 2005
    Assignee: Institute of Microelectronics
    Inventor: Pawan Rawat
  • Patent number: 6849563
    Abstract: The coating thickness and uniformity of spin-on deposition layers on semiconductor wafers is controlled through the in situ control of the viscosity and homogeneity of the mixture of precursor material and solvent material. The thickness of the deposited material is selected and the viscosity required at a given spin rate for the selected thickness is automatically mixed. Sensing and control apparatus are employed to ensure that the uniformity and viscosity required is maintained before dispensing onto said semiconductor wafer. Low-K dielectric materials of selected thickness are deposited in a uniform coating.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: February 1, 2005
    Assignee: International Business Machines Corporation
    Inventors: Edward Barth, John A. Fitzsimmons, Arthur W. Martin, Lee M. Nicholson
  • Patent number: 6846745
    Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of both hydrogen and fluorine as process gases in the reactive mixture of a plasma-containing CVD reactor. The process gas also includes dielectric forming precursors such as silicon and oxygen-containing molecules.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: January 25, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: George D. Papasouliotis, Vishal Gauri, Raihan M. Tarafdar, Vikram Singh
  • Patent number: 6846755
    Abstract: A dielectric material is strengthened by bonding a metal component to the dielectric matrix. The metal component may be a metal oxide or metal oxide precursor. The metal component may be deposited on the substrate with the dielectric material, or sol-gel chemistry may be used and the liquid solution spin-coated on a substrate.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: January 25, 2005
    Assignee: Intel Corporation
    Inventors: Grant M. Kloster, Jihperng Leu
  • Publication number: 20040266216
    Abstract: A method for forming a low k dielectric material block is provided. In one example, the method includes depositing a low k dielectric layer over a semiconductor substrate and curing the deposited low k dielectric layer. The curing may be performed using a remote plasma process in which an excitation gas is excited in a selected region remote from the deposited low k dieletric layer to carry radiation energy and transfer to the low k dielectric layer when the excitation gas contacts the low k dielectric layer.
    Type: Application
    Filed: April 20, 2004
    Publication date: December 30, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lih-Ping Li, Yung-Chen Lu, Syun-Ming Jang
  • Publication number: 20040253833
    Abstract: A substrate processing apparatus and a substrate processing method are provided wherein an oxide film which is thinner than the conventional films can be formed with uniform thickness when forming an oxide film on the front-side surface of a substrate.
    Type: Application
    Filed: March 3, 2004
    Publication date: December 16, 2004
    Inventors: Orii Takehiko, Masaru Amai
  • Publication number: 20040253837
    Abstract: A method for forming a dielectric layer of a semiconductor is described. At first, providing a substrate with a metal-conductive layer having been formed thereon. Next covering the substrate with a membrane having a plurality of micro-holes. Afterward spraying a fluid dielectric on the membrane having a plurality of micro-holes. After waiting a period of time for the gaps among the metal conductors being filled with the fluid dielectric, removing the membrane having a plurality of micro-holes from the substrate. Further baking the substrate to cure the fluid dielectric inside metal-conductive layer. The thickness of the dielectric after curing is approximately equal to the thickness of the metal-conductive layer. At last forming a cap dielectric layer on the substrate.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 16, 2004
    Inventor: Yu-Hao Yang
  • Patent number: 6830623
    Abstract: A plurality of liquids, the flow of each controlled by a volumetric flowrate controller, are mixed in a mixer to form a final precursor that is misted and then deposited on a substrate. A physical property of precursor liquid is adjusted by adjusting the volumetric flowrate controllers, so that when precursor is applied to substrate and treated, the resulting thin film of solid material has a smooth and planar surface. Typically the physical property is the viscosity of the precursor, which is selected to be relatively low, in the range of 1-2 centipoise.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: December 14, 2004
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Larry D. McMillan, Carlos A. Paz de Araujo