Abstract: An apparatus and method for depositing thin films. The apparatus generally comprises a process chamber having one or more walls and a lid and two heat exchangers. A first heat exchanger is coupled to the walls and a second heat exchanger is coupled to the lid. The two heat exchangers are configured to provide separate temperature control of the walls and lid. Separate control of the lid and wall temperatures inhibits reaction of the organosilane within the lid while optimizing a reaction within the chamber. The apparatus implements a method, in which a process gas comprising ozone and an organosilane are admitted through the into a processing while a substrate is heated to form a carbon-doped silicon oxide layer over the substrate. During deposition, the lid is kept cooler than the walls.

Abstract: A metal-organic precursor suitable for use in a chemical vapor deposition formation of dielectric layer is disclosed. The precursor comprises a moiety that includes a first metal atom, an oxygen atom, and a nitrogen atom. The oxygen atom is chemically bonded to the metal atom and to the nitrogen atom. The first metal atom may be a Group III, Group IV, or Group V transition metals such as yttrium, lanthanum, titanium, zirconium, hafnium, niobium, and tantalum or another metal such as aluminum. The precursor may include one or more alkoxy groups bonded to the first metal atom. The precursor may be characterized as a M(OCR3)X−Y−Z(ONR2)Y(OSiR3)Z molecule where Y is an integer from 1 to (X−1), Z is an integer from 0 to X−1, X is an integer from 3 to 5 depending upon the valency of M and (Y+Z) is less than or equal to X. In one embodiment the precursor further includes one or more siloxy or alkyl siloxy groups bonded to the first metal atom.

Abstract: A method of forming an integrated circuit using a fluoro-organosilicate layer is disclosed. The fluoro-organosilicate layer is formed by applying an electric field to a gas mixture comprising a fluoro-organosilane compound and an oxidizing gas. The fluoro-organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the fluoro-organosilicate layer is used as a hardmask. In another integrated circuit fabrication process, the fluoro-organosilicate layer is incorporated into a damascene structure.

Abstract: The present invention provides a method of manufacturing a semiconductor device that reduces pitch dependence which represents a characteristic that the hole diameter decreases with increasing hole pitch. In the surface of a resist (1) where holes (5a-5e) having pitch dependence are formed, Ar+ ions of an inert gas are vertically implanted, for example, at an energy of 50 keV at a dose of 5.0×1015 cm−2. The ion implantation in the resist (1) shrinks the resist (1) and increases the hole diameters of the holes (5a-5e). At this time, since the hole diameters of the holes (5a-5d) of small hole pitches increase by a smaller amount than the hole diameter of the hole (5e) of a great hole pitch, the pitch dependence of the holes (5a-5e) can be reduced.

Abstract: A process for treating silica dielectric film on a substrate, which includes reacting a suitable hydrophilic silica film with an effective amount of a multifunctional surface modification agent. The film is present on a substrate and optionally has a pore structure with hydrophilic pore surfaces, and the reaction is conducted for a period of time sufficient for said surface modification agent to penetrate said pore structure and produce a treated silica film having a dielectric constant of about 3 or less, wherein the surface modification agent is hydrophobic and suitable for silylating or capping silanol moieties on such hydrophilic surfaces. Dielectric films and integrated circuits including such films are also disclosed.

Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.

Abstract: The present invention relates to a semiconductor device manufacturing method for forming a via hole or a contact hole in an interlayer insulating film with a low dielectric constant. The method includes the steps of forming a nitrogen containing insulating film on a substrate, forming a porous insulating film on the nitrogen-containing insulating film, forming an opening in the underlying insulating film and the porous insulating film, and forming a nitrogen containing insulating film on the surface of the porous insulating film and on the surface of the opening by bringing these surfaces into contact with a plasma of any one of an ammonia gas, a nitrogen gas, and an oxygen nitride gas.

Abstract: A method including over a substrate, forming an aggregate comprising a barrier layer between a first dielectric layer comprising nitrogen and a second dielectric layer comprising phosphorous, and after forming the aggregate, thermally treating the substrate. An apparatus including a substrate and an aggregate formed over the substrate including a barrier layer between a first dielectric layer comprising nitrogen and a second dielectric layer comprising phosphorous.

Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.

Abstract: A method for manufacturing a semiconductor device of the present invention includes, forming a first silicon oxide film by HDP-CVD so as to bury a recess portion in a three-dimensional portion formed in a surface region of a semiconductor workpiece to a position lower than an upper surface of the recess portion, and forming a second silicon oxide film by SOG on the first silicon oxide film so as to fill the recess portion.

Abstract: A composite insulating film including three layers is formed on a substrate having a gap. The first layer partially fills the gap and contains a dielectric material having a low dielectric constant, such as halogen-doped silicate glass. The second layer is formed over the first layer, and contains an undoped dielectric material such as silicon oxide, nitride, or oxynitride. The second layer is more stable and integrable, and less susceptible to moisture absorption and outgassing, than the first layer. The second layer is substantially smaller in thickness than the first layer, and at least substantially fills the gap. The third layer is formed over the second layer, and contains a dielectric material having a low dielectric constant, such as halogen-doped silicate glass. In a specific embodiment, the first layer is formed by plasma-enhanced chemical vapor deposition in which reactive species are generated from a process gas mixture by plasma for sputtering the first layer.

Abstract: In accordance with the invention a high-k gate dielectric is formed by the steps of first forming a silicon oxide layer over a silicon substrate and then exposing the silicon oxide to a flux of low energy plasma containing metal ions which, when inserted into silicon oxide, form a high-k dielectric material suitable for use as a high-k gate dielectric. In one embodiment, the silicon oxide is exposed to a first plasma containing a first species of metal ions and then to a plasma of another species of metal ions which, when inserted into the silicon oxide with the metal ions in the first plasma, further increase the dielectric constant of the silicon oxide.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 Hm over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.

Abstract: An intermediary dielectric layer is disposed between two dielectric layers thereby eliminating a flow stabilization step that may produce unwanted deposition that leads to peeling. A wafer is provided having an HDP layer. An undoped silicon glass layer is deposited on top of the HDP layer to improve adherence of a subsequently deposited PSG layer.

Abstract: There is included an inorganic insulating film having a porous structure including a cylindrical vacancy oriented in parallel with the surface of a substrate subjected to a hydrophilic treatment or a hydrophobic treatment.

Abstract: A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution.

Abstract: A method for forming an insulating film, wherein a precursor film of a coating type insulating film having Si—H bonding is coated, the precursor film is calcined in an atmosphere containing at least one of an inert gas and oxygen gas for converting it into a ceramic film as the insulating film, and then the ceramic film is cooled under reduced pressure lower than that for the calcination.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) process is provided for depositing one or more dielectric material layers on a substrate for use in interconnect structures of integrated circuits. The method comprises the steps of depositing a fluorinated amorphous carbon (a-F:C) layer on a substrate by providing a fluorine containing gas, preferably octafluorocyclobutane, and a carbon containing gas, preferably methane, in ratio of approximately 5.6, so as to deposit a a-F:C layer having an internal compressive stress of approximately 28 MPa. After deposition the film is annealed at approximately 400° C. for approximately two hours. An adhesion promoter layer of relatively hydrogen-free hydrogeneated silicon carbide is then deposited on the a-F:C layer using silane (SiH4) and methane (CH4) as the deposition gases.

Abstract: A method for fabricating a boron-contained silicate glass layers, such as borosilicate and borophosphosilicate glass films at low temperature using High Density Plasma CVD with silane derivatives as a source of silicon, boron and phosphorus compounds as a doping compounds, oxygen is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a flow capability of boron-contained silicate glass materials which provide a film with good film integrity and void-free gap-fill within the steps of device structures after low temperature thermal budget anneal conditions.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.

Abstract: A method described for making a semiconductor transistor having a thin gate dielectric layer with a high k-value but without any impurities in a channel in silicon directly below the gate dielectric layer. An apparatus is used which pulses a cathode to create a plasma generating voltage potential between the cathode and an anode provided by a wall of a chamber of the apparatus. The plasma generating voltage generates an ion plasma out of a gas in the chamber. The ion plasma is maintained transient which allows for better control of its energy. A portion of a wafer stand is pulsed with a small voltage which extracts and accelerates ions out of the plasma into a silicon dioxide gate dielectric layer formed on a wafer in the chamber.

Abstract: A technique for controlling the oxidation of silicon is achieved by applying low temperature ammonia prior to the oxidation. The result is that the subsequent oxidation of the silicon is at a slower oxidation rate and higher nitrogen content. The higher nitrogen content is particularly beneficial for a gate dielectric because it acts as somewhat of a boron barrier and provides additional resistance to unwanted oxidation. The result is transistors with improved gate dielectric thickness uniformity across a wafer for a tighter threshold voltage distribution, reduced shift in threshold voltage, and improved time to breakdown.

Abstract: A semiconductor device formed on a substrate includes at least one metal stack formed on the substrate. A fluorosilicate glass layer is formed on the at least one metal stack, where the fluorosilicate glass layer acts as an interlayer dielectric for the semiconductor device. The fluorosilicate glass layer includes a fluorine-depleted layer at a top portion of the fluorosilicate glass layer that is further away from the substrate. The fluorine-depleted layer is formed by treating the fluorosilicate glass layer with a hydrogen plasma, such as an H2/N2 plasma. The fluorine-depleted layer lessens a likelihood of fluorine atoms in the fluorosilicate glass layer from moving into and thereby corrupting a conducting layer formed above the fluorosilicate glass layer.

Abstract: A method of forming a pre-metal dielectric film having good as deposited gapfill characteristics, as well as good mobile-ion gettering capability. The method involves first depositing a layer of high-ozone undoped silicon dioxide film having a high ozone/TEOS volume ratio. Then, a low-ozone doped BPSG film is deposited over the high-ozone undoped silicon dioxide layer. The film layers are heat treated to densify the film, and then the top layer is planarized using known planarization techniques to a thickness that allows for adequate mobile-ion gettering.

Abstract: A method of densifying a superficial layer on a low dielectric constant film. A substrate is provided. A low dielectric constant material layer is formed over the substrate. An inert gas plasma treatment of the low dielectric constant material layer is conducted so that a superficial layer of the low dielectric constant material layer is densified into a protective layer. The protective layer protects the low dielectric constant material layer against attacks by plasma and chemicals during subsequent processes and prevents any deterioration of electrical properties.

Abstract: A method and apparatus for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

Abstract: A process and system for forming a low dielectric film in a semiconductor fabrication process are disclosed. Initially, a carbon-doped silicon oxide film is deposited on a semiconductor wafer. Light energy, such as ultraviolet (UV) energy, is then applied to the deposited film to cure the film. In one embodiment, at least 30% of the light energy is at a frequency greater than that of visible light. In the preferred embodiment, the application of the light energy to the wafer does not significantly heat the wafer. The invention further contemplates a cluster tool or system suitable for forming and curing the dielectric film. The cluster tool includes a first chamber coupled to an organosilane source, a second chamber configured to apply light energy to a wafer received in the second chamber, and a robotic section suitable for controlling movement of wafers between the first chamber and the second chamber.

Abstract: A method of manufacturing a low-k semiconductor structure including the steps of forming a low-k dielectric layer, forming a sacrificial etch stop layer adjacent the low-k dielectric layer, and applying energy to the sacrificial etch stop layer to diffuse a component of the sacrificial etch stop layer into the adjacent low-k dielectric layer. This diffusion of the component lowers the dielectric constant of the adjacent low-k dielectric layer.

Abstract: A method of forming a low dielectric constant silicate material for use in integrated circuit fabrication processes is disclosed. The low dielectric constant silicate material is formed by reacting by reacting a gas mixture comprising an organosilane compound, an oxygen source, and an inert gas. Thereafter, a silicon carbide cap layer is formed on the silicate material by reacting a gas mixture comprising a silicon source and a carbon source. The silicon carbide cap layer protects the underlying organosilicate layer from cracking and peeling when it is hardened during a subsequent annealing step.

Abstract: Gap-fill and damascene methods are disclosed for depositing an insulating thin film of nitrofluorinated silicate glass on a substrate in a process chamber. A high-density plasma, generated from a gaseous mixture of silicon-, fluorine-, oxygen-, and nitrogen-containing gases, deposits a layer of nitrofluorinated silicate glass onto the substrate. For gap-fill applications, the substrate is biased with a bias power density between 4.8 and 11.2 W/cm2 and the ratio of flow rate for the oxygen-containing gas to the combined flow rate for all silicon-containing gases in the process chamber is between 1.0 and 1.8, preferably between 1.2 and 1.4. For damascene applications, the bias power density is less than 3.2 W/cm2, preferably 1.6 W/cm2, and the flow rate ratio is between 1.2 and 3.0. Using optimized parameters, the thin film has a lower dielectric constant and better adhesion properties than fluorosilicate glass.

Abstract: A structure and method of manufacturing a CMOS device where the Coplanar wave guide (CPW) lines are formed above the top metal lines. Also other insulating layers are provided that reduce the e-field from the signal line to the substrate. There are four embodiments. In the first embodiment, the following layers are formed over the semiconductor structure: the passivation layer, a shielding layer, a first insulator layer, a high K dielectric layer, a CPW and a second insulator layer. In the second embodiment, no shielding layer is used and the high k dielectric layer is thicker than in the first embodiment. In the third embodiment, a thick shielding layer is used and no high k dielectric layer. In the fourth embodiment, the top metal layer is used as a shielding layer and no high k dielectric layer is used.

Abstract: A method for reducing a capacitance formed on a silicon substrate includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method includes the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen includes forming hydrogen atoms in the surface with concentrations of 1017 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are introduced by baking in hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr. A trench capacitor DRAM cell is provided wherein the hydrogen provides a passivation layer to increase the effective capacitance around a collar region and thereby reduce unwanted transistor action.

Abstract: A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800° C. and about 1000° C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: Embodiments of the present invention provide nitrogen doping of a fluorinated silicate glass (FSG) layer to improve adhesion between the nitrogen-containing FSG layer and other layers such as barrier layers. In some embodiments, a nitrogen-containing FSG layer is deposited on a substrate in a process chamber by supplying a gaseous mixture to the process chamber. The gaseous mixture comprises a silicon-containing gas, a fluorine-containing gas, an oxygen-containing gas, and a nitrogen-containing gas. Energy is provided to the gaseous mixture to deposit the nitrogen-containing FSG layer onto the substrate. A plasma may be formed from the gaseous mixture to deposit the layer. In some embodiments, an FSG film that has been formed is doped with nitrogen by a plasma treatment using a nitrogen-containing chemistry. For example, nitrogen ashing in a damascene process may introduce nitrogen dopants into the surface of the FSG layer.

Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

Abstract: A method for producing a semiconductor device including formation of an interlayer insulating film having a fluorine-doped silicon oxide layer on a substrate. The method comprising the steps of forming the fluorine-doped silicon oxide layer in a process chamber, and forming a silicon oxide layer on the fluorine-doped silicon oxide layer in the same process chamber subsequent to the formation of the fluorine-doped silicon oxide layer. The silicon oxide layer is formed at a temperature higher than a film forming temperature of the fluorine-doped silicon oxide layer thereby forming the interlayer insulating film comprising the fluorine-doped silicon oxide layer and the silicon oxide layer formed thereon on the substrate.

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Oxide base film on a substrate, and then annealing the substrate in ammonia. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract: Methods for depositing a low-k dielectric film on the surfaces of semiconductors and integrated circuits are disclosed. A Si—O—C-in-ring cyclic siloxane precursor compound is applied to the surface by chemical vapor deposition where it will react with the surface and form a film having a dielectric constant, k, less than 2.5. The compound generally has the formula (—O—R1—O—)SiR2R3 or the formula (—R1—O—)SiR2R3.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) process is provided for depositing one or more dielectric material layers on a substrate for use in interconnect structures of integrated circuits. The method comprises the steps of depositing a fluorinated amorphous carbon (a-F:C) layer on a substrate by providing a fluorine containing gas, preferably octafluorocyclobutane, and a carbon containing gas, preferably methane, in ratio of approximately 5.6, so as to deposit a a-F:C layer having an internal compressive stress of approximately 28 MPa After deposition the film is annealed at approximately 400° C. for approximately two hours. An adhesion promoter layer of relatively hydrogen-free hydrogeneated silicon carbide is then deposited on the a-F:C layer using silane (SiH4) and methane (CH4) as the deposition gases.

Abstract: Multi-metallization level semiconductor devices are formed without degrading a low k dielectric gap fill material due to multiple pre-metallization degassing/outgassing heat treatments. Degradation of the low k material is substantially reduced or eliminated by employing time intervals for heat treatment which are not longer than the longest metal deposition step and temperatures below that which the dielectric material decomposes.

Abstract: In forming various types of insulating films in manufacture of a semiconductor device, carbon is gasified into CHx, COH etc. during film formation by adding active hydrogen and nitrogen oxide to reduce the carbon content during the film formation, and the effect of blocking impurities such as alkali metals is improved.

Abstract: A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).

Abstract: A method of forming a bond pad area for an integrated circuit provides FSG in the dielectric layer while at the same time minimizes bond pad lift off. The method includes forming a first dielectric layer of fluorinated silicon glass (FSG) on a substrate, then forming an FSG barrier layer on the first dielectric layer. A second, non-FSG dielectric layer is formed on the FSG barrier layer. A barrier metal layer is then formed on the second dielectric layer. Finally, a metal layer is formed on the barrier metal layer. This metal layer provides the surface for adhesion to the bonding wire. The FSG barrier layer absorbs the atoms of fluorine diffused from the first dielectric layer. In this manner, fluorine is prevented from penetrating the second dielectric layer, thereby minimizing bond pad lift off between the second dielectric layer and the barrier metal layer. In one embodiment, the FSG barrier layer includes titanium and/or aluminum.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: A method of manufacturing a semiconductor device is provided. A TEOS film (1) is formed, and then an FSG film (2) is formed on the TEOS film (1) by a CVD or PVD process. The CVD or PVD of the FSG film (2) is continued so that noble gas atoms are introduced into the FSG film (2) to form a noble gas atom containing layer (3). Next, using a photoresist (4) formed on the noble gas atom containing layer (3) as a mask, the noble gas atom containing layer (3) and the FSG film (2) are etched in the order named. After the photoresist (4) is removed, a barrier metal (6) and a copper film (7) are formed on an entire surface of a resultant structure. The copper film (7) and the barrier metal (6) are polished away in the order named by a CMP process until an upper surface of the noble gas atom containing layer (3) is exposed. Parts of the copper film (7) which are left unpolished become copper interconnect lines (9) filling trenches (5). The method can reduce a wiring capacitance between the adjacent interconnect lines.

Abstract: A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.

Abstract: A method is provided for reducing elevated boron concentrations (denoted as “boron spikes”) in an insulating layer containing silicon, boron and other elements where the layer interfaces with surfaces of a semiconductor device. The method includes the steps of: seasoning a reaction chamber by flowing into it a mixture of gasses containing silicon, boron, ozone and other elements in predetermined proportions under set conditions of time, pressure, temperature and flow rates to deposit on inner walls and surfaces of the chamber a thin seasoning coating, and placing a semiconductor device in the chamber and covering it with an insulating layer having a composition similar to the seasoning coating. Subsequent etching of selected portions of the insulating layer has been found not to expose conductive surfaces of the device.

Abstract: It is an object to provide an insulating film which enables not only to obtain a good film quality but to achieve an excellent filling property, thick film formation and planarization simultaneously, and to provide an insulating film forming coating solution for forming the insulating film, and to provide a method of manufacturing the insulating film. An insulating film forming coating solution containing as a main component a solution of a polymer obtained by co-hydrolysis of trialkoxysilane expressed by a general formula, SiH(OR)3, methyltrialkoxysilane expressed by a general formula, SiCH3(OR)3, and tetraalkoxysilane expressed by a general formula, Si(OR)4 is coated on a semiconductor substrate (1) having a step portion, and after it is heated and dried in an inert gas atmosphere, an insulating film (6) which is composed of a silane-derived compound expressed by a general formula, SiHx(CH3)yO2−(x+y)/2, where, 0<x<1, 0<y<1, x+y≦1 is formed.