Abstract: A method for fabricating a MTJ cell of a magnetic random access memory (MRAM) using a semiconductor film as a tunnel barrier layer is disclosed. The method comprises the steps of: forming a pinned ferromagnetic layer on a connection layer; forming a tunnel barrier layer using a semiconductor film on the pinned ferromagnetic layer; and forming a free ferromagnetic layer on the tunnel barrier layer.

Abstract: A dielectric material is strengthened by bonding a metal component to the dielectric matrix. The metal component may be a metal oxide or metal oxide precursor. The metal component may be deposited on the substrate with the dielectric material, or sol-gel chemistry may be used and the liquid solution spin-coated on a substrate.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of both hydrogen and fluorine as process gases in the reactive mixture of a plasma-containing CVD reactor. The process gas also includes dielectric forming precursors such as silicon and oxygen-containing molecules.

Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.

Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

Abstract: A fabrication method of a semiconductor device improved in the polishing rate of an insulation film and less likely to generate a defect during polishing is obtained. In this fabrication of a semiconductor device, impurities are introduced into a first insulation film, and then planarization is effected by polishing the surface of the first insulation film. Thus, the polishing rate of the portion of the first insulation film in which impurities are introduced is improved. Also a defect is not easily generated therein.

Abstract: An insulating film which enables not only to obtain a good film quality but to achieve an excellent filling property, thick film formation and planarization simultaneously, an insulating film forming coating solution for forming the insulating film, and a method of manufacturing the insulating film are set forth. An insulating film forming coating solution containing as a main component a solution of a polymer obtained by co-hydrolysis of trialkoxysilane expressed by a general formula, SiH(OR)3—, methyltrialkoxysilane expressed by a general formula, SiCH3(OR)3—, and tetraalkoxysilane expressed by a general formula, Si(OR)4 is coated on a semiconductor substrate (1) having a step portion, and after it is heated and dried in an inert gas atmosphere, an insulating film (6) which is composed of a silane-derived compound expressed by a general formula, SiHx(CH3)yO2−(x+y)/2, where, 0<x<1, 0<y<1, x+y≦1 is formed.

Abstract: A semiconductor device including an insulation film superior in both planarization and water resistance is obtained. In this semiconductor device, a first insulation film including impurities is formed on a conductive layer. A film is formed between the first insulation film and the conductive layer for substantially preventing impurities from entering the conductive layer. Water resistance of the first insulation film is improved since impurities are included in the first insulation film. By using an insulation film superior in planarization as the first insulation film, a first insulation film superior in both planarization and water resistance can be obtained. The film provided between the first insulation film and the conductive layer prevents the impurities of the first insulation film from entering the conductive layer. Therefore, reduction in the reliability of the conductive layer can be prevented.

Abstract: A method for manufacturing a modular electrical circuit includes the steps of pre-manufacturing a plurality of components having fine features such as resistors, capacitors, inductances, and conductors formed on a dielectric substrate. The pre-manufactured components are laminated each to the other in a predetermined order. Each pre-manufactured component includes one or more electrical elements of the same type coupled each to the other by conducting lines. Each dielectric substrate includes through vias filled with the conductive material which serve for cross-coupling of the elements of neighboring components. Position of the passive elements, as well as conductive lines and through vias, are pre-designed to allow precise coordination between the elements of different components in the multi-layered modular electrical circuit.

Abstract: A method of forming a gate dielectric includes the steps of forming a gate oxide layer on a substrate, forming a buffer layer over the gate oxide layer and incorporating nitrogen into the gate oxide layer through the buffer layer. A semiconductor device having a gate structure is also provided. The gate includes a nitrogen enriched gate oxide layer formed on a substrate, a silicon nitride or poly-silicon buffer layer formed on the gate oxide layer and a gate electrode formed over the buffer layer.

Abstract: A system and method for analyzing sheet resistivity of a layer on a wafer employing electrical methods and for controlling rapid thermal annealing (RTA) of the layer is provided. The system includes components for performing RTA on the layer and components for analyzing the sheet resistivity of one or more portions of the layer upon which RTA was performed. The system further includes a feedback generator adapted to accept sheet resistivity data and to produce feedback information that can be used to control the RTA components. The system further includes a data store that can be employed in machine learning and/or to facilitate generating feedback information that can be employed to control RTA and a monitoring application that can be employed to schedule maintenance on the various components in the system.

Abstract: A method for reducing contaminants in a processing chamber having an inner wall by seasoning the walls. The method comprising the following steps. A first USG film is formed over the processing chamber inner wall. An FSG film is formed over the first USG film. A second USG film is formed over the FSG film. A nitrogen-containing film is formed over the second USG film wherein the first USG film, the FSG film, the second USG film and the nitrogen-containing film comprise a UFUN season film.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

Abstract: A method for rapidly depositing a borosilicate glass film on a semiconductor wafer includes controlling the pressure within the chamber, introducing oxygen into the chamber, introducing a carrier gas into the chamber, injecting triethyl borate (“TEB”) and tetraethyl orthosilicate (“TEOS”) into the chamber, stabilizing the injection of TEB and TEOS, adjustably spacing a heater relative to the chamber, introducing ozone gas into the chamber, and depositing borosilicate glass film at a rate of at least about 4,500 angstroms per minute.

Abstract: Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.

Abstract: A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two different time periods and under conditions effective to deposit a doped silicon dioxide layer on the substrate. The time periods and conditions are characterized by some period of time when one of said gaseous precursors comprising said dopant is flowed to the chamber in the substantial absence of flowing any of said oxidizer precursor. In one implementation, the time periods and conditions are effective to at least initially deposit a greater quantity of doped silicon dioxide within at least some gaps on the substrate as compared to any doped silicon dioxide deposited atop substrate structure which define said gaps.

Abstract: A novel visible light curable composition for forming a thermally conductive interface and a method of using the same is provided. The composition is used to promote the transfer of heat from a source of heat such as an electronic device to a heat dissipation device such as a heat sink. The composition includes an elastomeric base matrix containing a light curable catalyst, loaded with a thermally conductive filler material such as boron nitride grains or ceramic filler. After the compound is prepared, it is screen or stencil printed onto the desired surface and cured by exposure to visible light. The thermal interface is bonded to the desired surface and has sufficient compressibility to allow it to overcome the voids in the mating surface to which the assembly is mounted.

Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas is disclosed. The nitridation process can be carried out at lower temperatures and pressures than a conventional nitrous oxide anneal while still achieving acceptable levels of nitridation. The nitridation process can be conducted at atmospheric or sub-atmospheric pressures. As a result, the nitridation process can be used to form nitrided gate oxide layers in-situ in a CVD furnace. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

Abstract: The invention concerns a method comprising evaporating silicon and/or SiOx, wherein said evaporating is further defined as occurring in the presenceof oxygen if silicon or SiOx with x less than two is being evaporated, to form a silicon oxide film at the surface of a substrate and in bombarding said silicon film, while it is being formed, with a beam of positive ions derived from both a polyfluorocarbon compound and a rare gas. The invention is useful for producing low-index antiglare films.

Abstract: A semiconductor device superior in reliability and suitable for microminiaturization is provided. An organic SOG film is formed on a silicon oxide film. Boron ions are implanted into the organic SOG film. By introducing boron ions into the organic SOG film, the organic components in the film are decomposed. Also, the moisture and hydroxyl group included in the film are reduced. After a metal interconnection is embedded in a modified SOG film by the Damascene method, a modified SOG film is formed thereon. Then, contact holes are formed. After a contact hole interconnection is embedded in the contact holes, a modified SOG film and an upper metal interconnection are formed by the Damascene method.

Abstract: A dielectric film containing lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric film is formed by ion assisted electron beam evaporation of TiO2 and electron beam evaporation of a lanthanide selected from a group consisting of Nd, Tb, and Dy. The growth rate is controlled to provide a dielectric film having a lanthanide content ranging from about ten to about thirty percent of the dielectric film. These dielectric films containing lanthanide doped TiOx are amorphous and thermodynamically stable such that the lanthanide doped TiOx will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: Methods of forming dielectric layers and methods of forming capacitors are described. In one embodiment, a substrate is placed within a chemical vapor deposition reactor. In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate and comprises fluorine from the activated fluorine. In another embodiment, a fluorine-comprising material is formed over at least a portion of an internal surface of the reactor. Subsequently, a dielectric layer is chemical vapor deposited over the substrate. During deposition, at least some of the fluorine-comprising material is dislodged from the surface portion and incorporated in the dielectric layer. In another embodiment, the internal surface of the reactor is treated with a gas plasma generated from a source gas comprising fluorine, sufficient to leave some residual fluorine thereover.

Abstract: The present invention relates to a manufacturing method of a thin-film structural body which is formed by using a semiconductor processing technique, and an object thereof is to provide a manufacturing method of a thin-film structural body, capable of reducing a stress difference exerted between a sacrifice film and a substrate upon thermal shrinkage. In order to achieve this object, a sacrifice film (51), which is formed on a substrate (1), is formed by using a PSG film in which the concentration of phosphorus is set to a value which is greater than 3 mol %, and also smaller than 4 mol %. After a thin-film layer (53) has been formed thereon and after the thin-film layer (53) has been patterned, the sacrifice film (51) is removed by an etching process.

Abstract: A method for producing hydrogenated silicon oxycarbide (H:SiOC) films having low dielectric constant. The method comprises using plasma-assisted polymerization to react a cyclic silane compound containing at least one strained silicon bond to produce the films. The resulting films are useful in the formation of semiconductor devices.

Abstract: A method of filling a gap which is defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate, providing a flow of an oxidizing processing gas to the chamber, and providing a flow of a phosphorous-containing processing gas to the chamber. The method also includes depositing a first portion of a P-doped silicon oxide film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas, the phosphorous-containing processing gas, and the oxidizing processing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas plus phosphorous-containing processing gas):(oxidizing processing gas) and maintaining the temperature of the substrate below about 500° C. throughout deposition of the conformal layer. The method also includes depositing a second portion of the P-doped silicon oxide film as a bulk layer.

Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely-spaced regions and a second thickness over the widely-spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely-spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely-spaced regions.

Abstract: To provide a method and an apparatus for forming a film capable of forming a boron-carbon-nitrogen film.

Abstract: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract: The present invention is directed to a semiconductor structure including a semiconductor substrate having at least one overlying layer formed thereon. The at least one overlying layer including at least one layer of dielectric material. The at least one layer of dielectric material including a protected region having a first dielectric constant and another porous region having a second dielectric constant wherein the value for the second dielectric constant is less than the first dielectric constant. The porous region having been formed by the implantation of a porosity inducing material into the porous region and subsequent annealing. A method for forming such structures is also included.

Abstract: A process for forming a thermally stable low-dielectric constant material is provided. A gas mixture is prepared to form a fluorinated amorphous carbon (a-C:F) material. The gas mixture is mixed with a boron-containing gas.

Abstract: A method for controlling bow in wafers which utilize doped layers is described. The method includes depositing a silicon-germanium layer onto a substrate, depositing an undoped buffer layer onto the silicon-germanium layer, and depositing a silicon-baron layer onto the undoped layer.

Abstract: A touch-sensitive semiconductor chip having a physical interface to the environment, where the surface of the physical interface is coated with a fluorocarbon polymer. The polymer is highly scratch resistant and has a characteristic low dielectric constant for providing a low attenuation to electric fields. The polymer can be used instead of conventional passivation layers, thereby allowing a thin, low dielectric constant layer between the object touching the physical interface, and the capacitive sensing circuits underlying the polymer.

Abstract: A method of reducing plasma induced damage in semiconductor devices and fluorine damage to a metal containing layer including providing a semiconductor wafer including semiconductor devices including a gate oxide and a process surface including metal lines; carrying out a first high density plasma chemical vapor deposition (HDP-CVD) process to controllably produce a silicon rich oxide (SRO) layer including a relatively increased thickness at a center portion of the process surface compared to a peripheral portion of the process surface; and, carrying out a second HDP-CVD process in-situ to deposit a fluorine doped silicon dioxide layer over the SRO layer to fill a space between the metal lines.

Abstract: A method for making a semiconductor device having a pattern of highly doped regions located some distance apart in a semiconductor substrate and regions of low doping located between the highly doped regions. A diffusion barrier material is applied to the semiconductor substrate at the location of the regions of low doping by imprinting with the barrier material in the pattern of the regions of low doping. The doping material is applied after or before imprinting with barrier material so that the highly doped regions are formed essentially between the barrier material in the substrate.

Abstract: In a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode including the quantum dot, a first layer including a first material is deposited on the substrate. The first material has first atoms that are superbundant and bound with the weak bonding energy in the first layer. A second layer is deposited on the first layer. The second layer comprises a second material including second atoms that are capable of migrating into the first atoms. The first atoms are migrated into the second layer and the second atoms are migrated into the first layer, so that the second atoms are arranged in the first layer. Each of the second atoms in the first layer is formed into a quantum dot. An electrode layer is formed on the first layer after partially etching the second layer, and then a gate electrode is formed by patterning the electrode layer.

Abstract: A thermal activated SACVD method for depositing a phosphorus oxide layer onto a silicon oxide wafer comprising the steps of: loading an SACVD device with a silicon oxide wafer; depositing a phosphorus doped oxide (PSG) layer on the USG layer using pure oxygen and a phosphorus and silicon source; purging the SACVD device; and depositing a boron and phosphorus doped oxide (BPSG) layer on the PSG layer.

Abstract: One aspect of the present invention relates to a system and method for improving memory retention in flash memory devices. Retention characteristics may be enhanced by nitridating the bottom silicon dioxide layer of the ONO dielectric. To further mitigate charge leakage within the memory cell, the charge retention layer, or silicon nitride layer of the ONO dielectric, may be passivated via a hydrogen anneal process in order to reduce the number of charge traps, and thus, the amount of charge loss. The present invention also provides a monitoring and feedback-relay system to automatically control ONO formation such that a desired ONO dielectric stack is obtained. The present invention may be accomplished in part by employing a measurement system to measure properties and characteristics of the ONO stack during the critical formation steps of the bottom silicon dioxide layer and a silicon nitride layer.

Abstract: A dielectric material having a high dielectric constant includes a Group III metal oxide and a Group V element. The incorporation of the Group V element in the Group III metal oxide material reduces the number of structural defects in the dielectric material, and reduces both the fixed charge density and the conduction current of the dielectric material.

Abstract: A method for forming a composite dielectric layer within a microelectronic product provides a first dielectric layer formed over a substrate of a fluorosilicate glass (FSG) dielectric material deposited employing a high density plasma chemical vapor deposition (HDP-CVD) method. The method also provides a second dielectric layer formed over the first dielectric layer and formed of an undoped silicate glass (USG) dielectric material deposited employing a HDP-CVD source radio frequency power only method employing a source radio frequency power of from about 1000 to about 5000 watts absent a bias power. The composite dielectric layer is formed with inhibited cracking.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A dielectric layer is made porous by treating the dielectric material after metal interconnects are formed in or through that layer. The porosity lowers the dielectric constant of the dielectric material. The dielectric material may be subjected to an electron beam or a sonication bath to create the pores. The structure has smooth sidewalls for metal interconnects extending through the dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes forming a buried insulator layer of a semiconductor-on-insulator (SOI) wafer with a dopant material, such as boron, therein. The insulator material with the dopant material may be formed by a number of methods, for example by thermal oxidation of a semiconductor wafer in the presence of an atmosphere containing the dopant material, by co-deposition of the insulator material and the dopant material, or by co-implantation of an insulator material and the dopant material. The dopant material may be the same as a dopant material in at least a region (e.g., a source, drain, or channel region) of a semiconductor material layer which overlies the insulator layer. The dopant material in the buried insulator layer may advantageously reduce the tendency of dopant material to migrate from the overlying material to the insulator layer, such as during manufacturing operations involving heating.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an oxidizing gas flow rate, (b) flowing a first carrier gas at a first carrier gas flow rate while carrying a first impurity including boron flowing at a first impurity flow rate, (c) flowing a second carrier gas at a second carrier gas flow rate while carrying a second impurity including phosphorus flowing at a second impurity flow rate, and (d) flowing a silicon source material at a silicon source flow rate. The second carrier gas flow rate is greater than the first carrier gas flow rate.

Abstract: Processing of applying ultraviolet rays to a front face of an insulating film material formed on a wafer W is performed, whereby a contact angle of the front face thereof becomes smaller. Accordingly, when an insulating film material is applied on the aforesaid front face, the material smoothly spreads, and projections and depressions never occur on a front face of an upper layer insulating film material. Thereby, it is possible to form the insulating film thick and flatter on a substrate.

Abstract: A semiconductor device is produced by forming a gate oxide film on a silicon substrate, forming a gate electrode on the gate oxide film, forming a nitrogen-containing oxide film on the silicon substrate and gate electrode in an N2O gas or an NO gas, forming a BPSG film on the nitrogen-containing oxide film, and carrying out a reflow process on the BPSG film in a water vapor atmosphere. During the reflow process, the nitrogen-containing oxide film that has no hydrogen atoms prevents the penetration and diffusion of oxygen and hydrogen atoms into the silicon substrate and gate electrode, thereby preventing the oxidization of the silicon substrate and gate electrode. No hydrogen atoms diffuse into the gate oxide film, and therefore, the reliability of the gate oxide film is secured.

Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

Abstract: Porous insulation films 28, 40, 50 are formed of an insulation forming material including a silicon compound having a skeleton containing C—C bonds, a pore forming compound which is decomposed or evaporated by a heat treatment, and a solvent which dissolves the silicon compound with the pore forming compound, whereby the porous insulation film can have good mechanical strength and low dielectric constant.