Abstract: A thin-film forming apparatus of the present invention is capable of reducing variation of film formation rate and forming thin films of a stable thickness. The thin-film forming apparatus can prevent decrease of the film formation rate due to raise of temperatures of an RF electrode and an inner wall of a reaction chamber, by supplying a pressure control gas of a predetermined pressure into the reaction chamber also in non-film formation time to keep a gas pressure in the reaction chamber constant. Thereby, thickness of a film grown on a substrate can be controlled to a constant thickness. Further, by heating the pressure control gas to raise its temperature to a value approximately equal to a temperature of a material gas, variation of the pressure of the gas in the reaction chamber is controlled and the temperatures of the inner wall of the reaction chamber and the RF electrode are kept constant.

Abstract: A method of converting a hydrophobic surface of a dielectric layer to a hydrophilic surface is described. That method comprises forming on a substrate a dielectric layer that has a hydrophobic surface, then coupling a hydrophilic component to the surface of the dielectric layer. Also described is a method for making a semiconductor device that employs this technique after polishing a conductive layer, which may comprise copper.

Abstract: Improved processes for depositing dielectric layers by HDP (High Density Plasma) CVD (Chemical Vapor Deposition) are described. One method controls the RF power applied to the side source RF power to be less than about 2500 Watts during dielectric deposition. A second method controls the thickness of the HDP-CVD deposited dielectric layer to be less than between about 2000 and 3000 Angstroms. These methods of HDP-CVD deposition of dielectric layers result in elimination or suppression of plasma induced damage to MOSFET devices and improved gate oxide integrity of MOSFET devices following deposition of dielectric layers by HDP-CVD.

Abstract: Adhesion between silicon nitride etch-stop layers and carbon doped oxide films may be improved by using plasma argon densification treatments of the carbon doped oxide films. The resulting surface layer of the carbon doped oxide films may be carbon-depleted and may include a relatively rough interface to improve the adhesion of deposited silicon nitride films.

Abstract: In a case where a CF film is used as an interlayer dielectric film for a semiconductor device, when a wiring of tungsten is formed, the CF film is heated to a temperature of, e.g., about 400 to 450° C. At this time, a F gas is released from the CF film, so that there are various disadvantages due to the corrosion of the wiring and the decrease of film thickness. In order to prevent this, thermostability is enhanced. A compound gas of C and F, e.g., C4F8 gas, and a hydrocarbon gas, e.g., C2H4 gas, are used as thin film deposition gases. These gases are activated as plasma to deposit a CF film on a semiconductor wafer 10 using active species thereof. Then, a hydrogen plasma producing gas, e.g., H2 gas, is introduced to be activated as plasma, and the CF film deposited on the wafer 10 is irradiated with the H plasma.

Abstract: A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.

Abstract: A semiconductor device including an insulation film superior in insulation characteristic is obtained. Boron ions are introduced by ion implantation into an organic SOG film with a silicon nitride film formed on the organic SOG film. By this boron implantation, the property of the organic SOG film is modified. The moisture and hydroxyl group included in the film are greatly reduced irrespective of the amount of dose of ions. By using such a layered film of a modified SOG film and a silicon nitride film thereupon as an interlayer insulation film or a passivation film, the water resistance of a semiconductor device can be improved sufficiently.

Abstract: A method for decreasing brittleness of single crystals, semiconductor wafers and fragile elements of structures and devices is invented. The method is based on applying to the crystal surface a hard amorphous stabilized carbon low-stress coating possessing adhesion to the substrate that is equal to or exceeding the tensile strength of the protected crystalline material. The carbon coating is stabilized with at least two alloying elements: the first alloying element is selected from the group consisting of O, H, N, or their combinations; the second alloying element is selected from the group consisting of Si, B, transition metals, or their combinations. According to the invented method, the most effective structure of Si—O-stabilized hard amorphous carbon is graphite-like—diamond-like composite of atomic scale named QUASAM.

Abstract: A method for carbon doped oxide (CDO) deposition is described. One method of deposition includes providing a substrate and introducing oxygen to a carbon doped oxide precursor in the presence of the substrate. A carbon doped oxide film is formed on the substrate. In another method the substrate is placed on a susceptor of a chemical vapor deposition apparatus. A background gas is introduced along with the carbon doped oxide precursor and oxygen to form the carbon doped oxide film on the substrate.

Abstract: A method for fabricating a region of low dielectric constant between metal layers of a substrate, such as an integrated circuit, that eliminate or minimize the problems associated with the existing and future low-k materials and processes. The method utilizes a sacrificial layer or an ultra low-k layer to form a major, but not entire, portion of the dielectric layer between the metal layers, using innovative integration schemes and CMP processes.

Abstract: A method is provided for forming a fluorinated silicate glass layer with HDP-CVD having a lower dielectric constant without compromising the mechanical properties of hardness and compressive stress. A gaseous mixture comprising a silicon-containing gas, an oxygen-containing gas, and a fluorine-containing gas is provided to a process chamber. The ratio of the flow rate of the fluorine-containing gas to the flow rate of the silicon-containing gas is greater than 0.65. A high-density plasma is generated from the gaseous mixture by applying a source RF power having a power density less than 12 W/cm2. A bias is applied to a substrate in the process chamber at a bias power density greater than 0.8 W/cm2 and less than 2.4 W/cm2. The fluorinated silicate glass layer is deposited onto the substrate using the high-density plasma.

Abstract: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

Abstract: According to one aspect of the invention, a method is provided of processing a substrate, including locating the substrate in a processing chamber, creating a nitrogen plasma in the chamber, the plasma having an ion density of at least 1010 cm−3, and a potential of less than 20 V, and exposing a layer on the substrate to the plasma to incorporate nitrogen of the plasma into the layer.

Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10W to about 200W or a pulsed RF power level from about 20W to about 500W. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract: A method of enhancing adhesion strength of a boro-silicate glass (BSG) film to a silicon nitride film is provided. A semiconductor substrate with a silicon nitride film formed thereon is provided. The silicon nitride film is then exposed to oxygen-containing plasma such as ozone plasma. A thick BSG film is then deposited onto the treated surface of the silicon nitride film. By pre-treating the silicon nitride film with ozone plasma for about 60 seconds, an increase of near 50% of Kapp of the BSG film is obtained.

Abstract: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur.

Abstract: The present invention relates to low dielectric materials essential for a semiconductor having high density and high performance of the next generation, particularly to a process for preparing a porous interlayer insulating film having low dielectric constant containing pores with a size of a few nanometers or less.

Abstract: A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an organo-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.

Abstract: A method of forming a carbon-doped silicon oxide layer is disclosed. The carbon-doped silicon oxide layer is formed by applying an electric field to a gas mixture comprising an organosilane compound and an oxidizing gas. The carbon-doped silicon oxide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the carbon-doped silicon oxide layer is used as an intermetal dielectric layer. In another integrated circuit fabrication process, the carbon-doped silicon oxide layer is incorporated into a damascene structure.

Abstract: A substrate is prepared whose surface has a partial area exposing an insulating material containing fluorine and at least a partial area in the other area exposing a conductive material containing copper as a main composition. The surface of the substrate is exposed to hydrogen plasma to clean the surface. A first insulating film made of insulating material is formed on the cleaned surface. It is possible to form a lamination structure having a fluorine-doped interlayer insulating film hard to be peeled off.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.

Abstract: A hydrogenation method that utilizes plasma directly exposes a crystalline semiconductor film to the plasma, and therefore involves the problem that the crystalline semiconductor film is damaged by the ions generated simultaneously in the plasma. If a substrate is heated to 400° C. or above to recover this damage, hydrogen is re-emitted from the crystalline semiconductor film.

Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Abstract: First of all, a semiconductor substrate is provided. Then a gate oxide layer having an uniform thickness is formed on the semiconductor substrate by way of using thermal oxidation. Subsequently, a doping layer is formed on the gate oxide layer by a plasma doped process. Next, forming a poly-layer on the doping layer of the gate oxide layer, wherein the poly-layer has an ions-distribution. Afterward, defining the poly-layer to form a poly-gate. The P-type ions are then implanted into the poly-gate and the substrate by way of using a self-aligned process. Finally, performing a thermal annealing process to form a uniform ion-implanting region and a poly-gate having a lower contact-resistance.

Abstract: A method for providing a dielectric film having a low dielectric constant. The deposited film is particularly useful as an intermetal or premetal dielectric layer in an integrated circuit. The low dielectric constant film is a carbon-doped silicon oxide layer deposited from a thermal, as opposed to plasma, CVD process. The layer is deposited from a process gas of ozone and an organosilane precursor having at least one silicon-carbon (Si—C) bond. During the deposition process the wafer is heated to a temperature less than 250° C. and preferably to a temperature between 100-200° C. Enhancements to the process include adding Boron and/or Phosphorus dopants, two step deposition, and capping the post cured layer.

Abstract: A process for fabricating an interconnect for contact holes includes forming contact holes in an insulation layer leading to a first interconnect layer, cleaning the hole surface, forming a barrier layer on the hole surface, forming an AlGeCu-containing second interconnect layer on the insulation surface by a low-temperature PVD process to fill up the contact holes, forming and patterning a mask layer, and patterning the second interconnect layer by an anisotropic etching process using the mask layer. Due to the relatively small grain sizes and precipitations that are formed in the process, the layer can be patterned directly in a subsequent patterning step, resulting in an extremely reliable and inexpensive interconnect that is easy to integrate in existing process sequences.

Abstract: A new control wafer configuration and method allows for the earlier detection of processing problems and resulting striations, localized high concentrations of phosphorous, in product wafers as compared to the standard control wafer configuration currently being used. By increasing the thickness of a phosphorus doped silicate glass (PSG) layer in a film stack from about 1500 Å in the standard control wafer to a thickness greater than about 2500 Å, preferably a thickness in the range between about 3000 Å to about 4000 Å, any localized high concentration phosphorus striations are consistently found within the PSG layer during testing. As a result, the PSG layer in the control wafer accurately represents potential defects in the product wafers. If there is a problem on the production line, the striations are detected in the control wafer before mass production of product wafers continues.

Abstract: The memory element of the present invention utilizes a substrate, a first conductive connection, a second conductive connection, and an ionic layer. The substrate includes a source region, a drain region, and a channel region, which is disposed between the source region and the drain region. The ionic layer includes ions and is coupled to the substrate. The first connection is coupled to the source region, and the second connection is coupled to the drain region. An electrical field is applied through said ionic layer such that the ions in the ionic layer move. When the memory element is to exhibit a logical high state, the polarity of the electrical field causes the ions to move toward the channel region. This pulls the electrons in the source and drain regions into the channel region making the channel region conductive. When the memory element is to exhibit a logical low state, the polarity of the electrical field causes the ions to move away from the channel region.

Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.

Abstract: Semiconductor devices with improved transistor performance are fabricated by ion-implanting a dopant into the oxide liner to prevent or substantially reduce dopant out-diffusion from the shallow source/drain extensions. Embodiments include ion implanting a P-type dopant, such as B or BF2, using the gate electrode as a mask, to form shallow source/drain extensions, depositing a conformal oxide liner, and ion implanting the P-type impurity into the oxide liner at substantially the same dopant concentration as in the shallow source/drain extensions. Subsequent processing includes depositing a spacer layer, etching to form sidewall spacers, ion implanting to form deep moderate or heavy source/drain implants and activation annealing.

Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or organic or inorganic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in a reactor chamber. A key feature of the invention's process is a mole ratio of gas additive to source of silicon, which is maintained in the range of about 0.3-20 depending on the compound used and the deposition process conditions. As a gas additive, one of the group including halide-containing organic compounds having the general formula CxHyRz, and chemical compounds with the double carbon-carbon bonds having the general formula CnH2n, is used.

Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Abstract: A plurality of metal wire layers consisting of a first metal wire layer and a second metal wire layer are formed on a semiconductor substrate. A fluorinated silicate glass film serving as an interlayer metal dielectric film is formed between the first and second metal wire layers. A silicon nitride film serving as a protective insulation film is formed on the fluorinated silicate glass film layer. An adhesive layer made of, for example, a P—SiO film, P—SiON film, or PE—SiO film, is formed between the fluorinated silicate glass film and the silicon nitride film.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2. And then, an aluminum oxide layer is formed on top of the semiconductor substrate with doping a dopant in situ. A conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure. The dopant is a material selected from a group consisting of Si, Zr, Hf, Nb or the like.

Abstract: This invention includes: a plasma-making step of making into plasma a film-forming gas including a compound of carbon and fluorine and an etching gas which can etch a film of fluorine-added carbon; and a film-forming step of forming a film of fluorine-added carbon onto an object to be processed by means of the plasma made in the plasma-making step. For example, the film-forming gas including a compound of carbon and fluorine includes a gas of a compound having a benzene ring. For example, the etching gas which can etch a film of fluorine-added carbon is a gas including fluorine. According to the invention, a concave portion can be satisfactory filled up with the CF film.

Abstract: In fabricating a semiconductor device, a hydrogen-containing first insulating film is formed over a semiconductor layer, a gate insulating film and a gate electrode, and a first heat-treatment in a hydrogen atmosphere is performed. A second insulating film can be formed on the first insulating film, and a second heat-treatment in a hydrogen atmosphere performed. A hydrogen-containing third insulating film can be formed on the second insulating film, and a third heat-treatment in an atmosphere containing hydrogen or nitrogen performed. By these methods, damages to a semiconductor layer caused by hydrogenation can be avoided.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device includes a semiconductor substrate and an indium doped dielectric layer located over the semiconductor substrate.

Abstract: An insulating layer having a BPSG layer, a semiconductor device and methods for fabricating them. After preparing an oxidizing atmosphere using an oxygen gas, a first seed layer is formed with a tetraethylorthosilicate (TEOS) and the oxygen gas. Thereafter, a second seed layer, used to form an insulating layer capable of controlling an amount of a boron, is formed by means of using a triethylborate (TEB), the TEOS and the oxygen gas. Then, the insulating layer having a BPSG layer is formed using the TEB, a triethylphosphate, the TEOS and an ozone gas. About 5.25 to 5.75% by weight of the boron and about 2.75 to 4.25% by weight of the phosphorous are added to the insulating layer.

Abstract: A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.

Abstract: A method of converting a hydrophobic surface of a dielectric layer to a hydrophilic surface is described. That method comprises forming a dielectric layer on a substrate, then operating a PECVD reactor to generate a plasma that converts the surface of that layer from a hydrophobic surface to a hydrophilic surface. Also described is a method for making a semiconductor device that employs this technique.

Abstract: The present invention provides a novel visible light curable composition for forming a thermally conductive interface and a method of using the same. The composition is used to promote the transfer of heat from a source of heat such as an electronic device to a heat dissipation device such as a heat sink. The composition includes an elastomeric base matrix containing a light curable catalyst, loaded with a thermally conductive filler material such as boron nitride grains or ceramic filler. After the compound is prepared, it is screen or stencil printed onto the desired surface and cured by exposure to visible light. The present invention provides a thermal interface that is bonded to the surface of the desired surface and has sufficient compressibility to allow it to overcome the voids in the mating surface to which the assembly is mounted.

Abstract: A first layer metal wire, an SiOF film and an F diffusion prevention film are formed on a surface of a base layer including a substrate, elements formed on the substrate and an insulator layer formed to cover the substrate and the elements. The F diffusion prevention film may be prepared from a silicon oxynitride film or a silicon oxide film containing Si—H bonds. A spacer film is formed on a surface of the F diffusion prevention film and its surface is flattened. A second layer metal wire is formed on a surface of the spacer film. Thus implemented is a semiconductor device comprising an F diffusion prevention film preventing F atoms contained in an SiOF film from diffusing into an upper metal wire with the F diffusion prevention film not etched in formation of the upper metal wire and a method of manufacturing a semiconductor device not directly polishing an SiOF film by CMP.

Abstract: In the fabrication of integrated circuits containing multilevel structures of FSG (F-doped SiO2) dielectric layers and aluminum-copper-TiN layers, superior adhesion between the FSG and aluminum-copper-TiN is achieved by subjecting the aluminum-copper-TiN layer to a plasma containing N2 and H2 or N2 and NH3 prior to deposition of the FSG layer. It is believed that the plasma treatment converts unreacted Ti within the TiN layer to TiN and, also, stuffs grain boundaries within the TiN layer with N2. The result is a void-free TiN layer which is impervious to F atoms residing in the FSG layer.

Abstract: A new method is provided of measuring actual temperatures across the surface of a semiconductor wafer. The thickness of a layer of Sub-Atmospheric TEOS Undoped Silicon Glass (SAUSG) is used to monitor the temperature distribution across the surface of a silicon substrate.

Abstract: A capping layer of an insulator such as silicon nitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon nitride caps on the metal lines. After the formation of such low k silicon oxide dielectric material between the closely spaced apart metal lines and the over silicon nitride caps thereon, a second layer of silicon nitride is deposited over the layer of low k silicon oxide dielectric material.

Abstract: A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: A disclosed embodiment comprises patterning a conductor in a dielectric in a semiconductor die. The dielectric can be, for example, silicon oxide or a low-k dielectric while the conductor can comprise aluminum, copper, or a copper-aluminum alloy. Thereafter, a blanket of high permeability layer is deposited over the dielectric. The high permeability layer can comprise high permeability materials such as nickel, iron, nickel-iron alloy, or a magnetic oxide. The blanket deposition of the high permeability layer can be accomplished by, for example, a sputtering technique. After depositing the high permeability layer, a portion of the atoms or molecules in the high permeability layer is driven into the underlying dielectric to increase the permeability of the dielectric. As an example, an ion implanter using heavy ions such as silicon ions or germanium ions can be used to drive some of the atoms or molecules in the high permeability layer into the underlying dielectric.

Abstract: A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.