Abstract: A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

Abstract: The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some of the evaporated aluminum oxide and silicon monoxide is deposited on a substrate to form the silicon-doped aluminum oxide on the substrate. The invention also encompasses methods of forming transistors and flash memory devices.

Abstract: Provided herein is a substrate processing system, which comprises a cassette load station; a load lock chamber; a centrally located transfer chamber; and one or more process chambers located about the periphery of the transfer chamber. The load lock chamber comprises double dual slot load locks constructed at same location. Such system may be used for processing substrates for semiconductor manufacturing.

Abstract: A system and method is disclosed for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition. A via in a semiconductor device is formed by placing a metal layer on a substrate and placing a layer of anti-reflective coating (ARC) titanium nitride (TiN) over the metal layer. A layer of dielectric material is placed over the ARC TiN layer and a via passage is etched through the dielectric and partially through the ARC TiN layer. A titanium layer is then deposited and subjected to a nitrogen plasma process. The nitrogen plasma converts the titanium layer to a first layer of titanium nitride. The first layer of titanium nitride does not react with fluorine to form a high resistance compound. Therefore the electrical resistance of the first layer of titanium nitride does not significantly increase during subsequent thermal cycles.

Abstract: Disclosed is a method for forming a heat sink laminate and a heat sink laminate formed by the method. In the method a particle mixture is formed from a metal, an alloy or mixtures thereof with a ceramic or mixture of ceramics. The mixture is kinetically sprayed onto a first side of a dielectric material to form a metal matrix composite layer. The second side of the dielectric material is thermally coupled to a heat sink baseplate, thereby forming the heat sink laminate.

Abstract: A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure.

Abstract: A method for depositing a doped silicon dioxide layer is provided that allows the dopant concentration in the silicon dioxide layer to be controlled throughout the layer. By controlling the dopant concentration throughout the layer the etch profile of contact holes etched into the layer can be controlled and footing can be prevented or eliminated. During the deposition of the silicon dioxide, the amount of dopant is increased as the temperature of the wafer is increased and held constant while the temperature of the wafer is constant.

Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula: R1xSi(OR2)4-x (where R1 is a phenyl group or a vinyl group; R2 is an alkyl group; and x is an integer of 1 to 3) is caused to undergo plasma polymerization or react with an oxidizing agent to form an interlayer insulating film composed of a silicon oxide film containing an organic component. As the organic silicon compound where R1 is a phenyl group, there can be listed phenyltrimethoxysilane or diphenyldimethoxysilane. As the organic silicon compound where R1 is a vinyl group, there can be listed vinyltrimethoxysilane or divinyldimethoxysilane.

Abstract: A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching conditions, the gap may be substantially 100% filled. Such filling is achieved by adjusting the flow rates of the precursor gases such that the deposition to sputtering ratio during the deposition phases is within certain predetermined limits.

Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.

Abstract: A method and system for forming a low defect oxide in a plasma processing chamber. By pulsing at least one of an RF power source and a processing gas, the growth of the oxide can be regulated. During periods in which the processing gas is not injected, an inert gas is injected to keep a substantially constant flow rate.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.13 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen and a phosphorus dopant precursor as process gasses in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.

Abstract: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur.

Abstract: A method of forming a semiconductor structure comprises forming an etch-stop layer comprising nitride, on a stack. The stack is on a semiconductor substrate, and the stack comprises (i) a gate layer. The forming is by CVD with a gas comprising a first compound which is SixL2x, and a second compound comprising nitrogen and deuterium, L is an amino group, and X is 1 or 2.

Abstract: A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two different time periods and under conditions effective to deposit a doped silicon dioxide layer on the substrate. The time periods and conditions are characterized by some period of time when one of said gaseous precursors comprising said dopant is flowed to the chamber in the substantial absence of flowing any of said oxidizer precursor. In one implementation, the time periods and conditions are effective to at least initially deposit a greater quantity of doped silicon dioxide within at least some gaps on the substrate as compared to any doped silicon dioxide deposited atop substrate structure which define said gaps.

Abstract: A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

Abstract: A thermal activated SACVD method for depositing a phosphorus oxide layer onto a silicon oxide wafer comprising the steps of: loading an SACVD device with a silicon oxide wafer; depositing a phosphorus doped oxide (PSG) layer on the USG layer using pure oxygen and a phosphorus and silicon source; purging the SACVD device; and depositing a boron and phosphorus doped oxide (BPSG) layer on the PSG layer.

Abstract: The present invention provides a packaged semiconductor device that includes two semiconductor die. The first semiconductor die is attached to a package substrate using adhesive. A first set of wire bonds electrically connect the first semiconductor die to the package substrate. A first layer of encapsulant extends over the first semiconductor die and over the first set of wire bonds. A second semiconductor die is attached to the first layer of encapsulant using adhesive. A second set of wire bonds electrically connect the second semiconductor die to the package substrate. A second layer of encapsulant extends over the second semiconductor die and over the second set of wire bonds.

Abstract: A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.

Abstract: The present invention provides a deposition method and deposition apparatus capable of forming a fluorine-containing silicon inorganic insulating film of stable film properties and a method of manufacturing a semiconductor device. Deposition apparatus 10 comprises parallel plate type electrodes 16, 22 arranged within reaction chamber 12, gas supply sources 20, 32, 34 for feeding process gas containing SiH4, SiF4 and oxygen source substance into reaction chamber 12, valves 36, 38, 40, gas mixing chamber 28 and power source 44 that supplies RF power for generating the plasma of the process gas. In this deposition apparatus 10, power source 44 is capable of supplying RF power of at least 1000 Watts to parallel plate type electrodes 16, 22. In this apparatus 10, fluorine-containing silicon oxide film is deposited on wafer 14 by generating the plasma of process gas containing SiH4, SiF4 and N2O.

Abstract: Methods of manufacturing flash memory cells. During a cleaning process after an etching process for forming a control gate is performed, polymer remains at the sidewall of a tungsten silicide layer. Therefore, the sidewall of the tungsten silicide layer is protected from a subsequent a self-aligned etching process. In addition, upon a self-aligned etching process, the etch selective ratio of the tungsten silicide layer to a polysilicon layer is sufficiently obtained using a mixed gas of HBr/O2. Therefore, etching damage to the sidewall of the tungsten silicide layer can be prevented. As a result, reliability of the process and an electrical characteristic of the resulting device are improved.

Abstract: A method of forming an essentially uniform doped insulating layer is disclosed. Variations in a substrate temperature that may result in a dopant gradient within a doped insulating layer can be compensated for by varying a dopant supply rate in a deposition process. One particular embodiment discloses a method of forming a high density plasma phosphosilicate glass having a phosphorous concentration of 8% or greater by weight that varies by no more than about 1% by weight throughout.

Abstract: A fabrication method of a semiconductor device improved in the polishing rate of an insulation film and less likely to generate a defect during polishing is obtained. In this fabrication of a semiconductor device, impurities are introduced into a first insulation film, and then planarization is effected by polishing the surface of the first insulation film. Thus, the polishing rate of the portion of the first insulation film in which impurities are introduced is improved. Also a defect is not easily generated therein.

Abstract: A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).

Abstract: A method of modifying the porosity of a thickness of a layer of porous dielectric material having a surface and formed on a semiconductor substrate is provided by exposing the porous dielectric material to a sufficient temperature in the presence of a first gas to drive moisture particles out of the pores. Modifying also includes, exposing the porous dielectric material to a radio frequency stimulus of sufficient power in the presence of a second gas to densify a thickness of the porous dielectric material to reduce or prohibit subsequent absorption of moisture or reactant gas particles by the thickness or porous dielectric material.

Abstract: A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.

Abstract: Embodiments of the present invention provide nitrogen doping of a fluorinated silicate glass (FSG) layer to improve adhesion between the nitrogen-containing FSG layer and other layers such as barrier layers. In some embodiments, a nitrogen-containing FSG layer is deposited on a substrate in a process chamber by supplying a gaseous mixture to the process chamber. The gaseous mixture comprises a silicon-containing gas, a fluorine-containing gas, an oxygen-containing gas, and a nitrogen-containing gas. Energy is provided to the gaseous mixture to deposit the nitrogen-containing FSG layer onto the substrate. A plasma may be formed from the gaseous mixture to deposit the layer. In some embodiments, an FSG film that has been formed is doped with nitrogen by a plasma treatment using a nitrogen-containing chemistry. For example, nitrogen ashing in a damascene process may introduce nitrogen dopants into the surface of the FSG layer.

Abstract: Methods of forming dielectric layers and methods of forming capacitors are described. In one embodiment, a substrate is placed within a chemical vapor deposition reactor. In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate and comprises fluorine from the activated fluorine. In another embodiment, a fluorine-comprising material is formed over at least a portion of an internal surface of the reactor. Subsequently, a dielectric layer is chemical vapor deposited over the substrate. During deposition, at least some of the fluorine-comprising material is dislodged from the surface portion and incorporated in the dielectric layer. In another embodiment, the internal surface of the reactor is treated with a gas plasma generated from a source gas comprising fluorine, sufficient to leave some residual fluorine thereover.

Abstract: A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.

Abstract: In one embodiment of the present inventions, an exhaust outlet in a vacuum processing chamber includes a nonsealing flow restrictor which can facilitate rapid opening and closing of the flow restrictor in some applications. Because the flow restrictor is a nonsealing flow restrictor, the conductance of the flow restrictor in the closed position may not be zero. However, the flow restrictor can restrict the flow of an exhaust gas from the chamber to permit the retention of sufficient processing gas in the chamber to deposit a film on the substrate or otherwise react with the substrate. After a film has been deposited, typically in a thin atomic layer, the exhaust flow restrictor may be opened such that the flow restrictor conductance is significantly increased to a second, higher flow rate to facilitate exhausting residue gas from the chamber. The nonsealing flow restrictor may be closed again to deposit a second layer, typically of a different material onto the substrate.

Abstract: In a case where a CF film is used as an interlayer dielectric file for a semiconductor device, when a wiring of tungsten is formed, the CF film is heated to a temperature of, e g., about 400 to 450° C. At this time, F containing gases are emitted from the CF film, so that there are various disadvantages due to the corrosion of the wiring and the decrease of film thickness. In order to prevent this, it is required to enhance thermostability. A compound gas of C and F, e.g., C4F8 gas, a hydrocarbon gas, e.g., C2H4 gas, and CO gas are used as thin film deposition gases. These gases are activated to deposit a CF film on a semiconductor wafer 10 at a process temperature of 400° C. using active species thereof. Since the number of diamond-like bonds are greater than the number of graphite-like bonds by the addition of CO gas, the bonds are strengthened and difficult to be cut even at a high temperature, so that thermostability is enhanced.

Abstract: On a given substrate are successively formed electrode patterns constituting electrode wirings for measuring points, respectively. Then, an insulating layer and an underlayer covering the electrode patterns are etched and removed to expose the substrate, which suffers from anisotropic etching using a given etching solution, to fabricate a multipoint minute electrode with a sharpened probe and a supporter for the probe.

Abstract: A thermal activated SACVD method for depositing a phosphorus oxide layer onto a silicon oxide wafer comprising the steps of: loading an SACVD device with a silicon oxide wafer; depositing a phosphorus doped oxide (PSG) layer on the USG layer using pure oxygen and a phosphorus and silicon source; purging the SACVD device; and depositing a boron and phosphorus doped oxide (BPSG) layer on the PSG layer.

Abstract: An apparatus and method for enhancing uniformity in the spread of a process chemical such as a liquid strip chemical or solvent over the surface of a wafer to enhance contact of all areas of the wafer with the chemical, such as during the removal or stripping of photoresist from the wafer. The apparatus includes a wafer chuck having a heater for heating the wafer chuck and a wafer supported on the chuck. The wafer chuck and wafer are initially heated to a desired target temperature which is substantially the same as the temperature of the process chemical, after which the process chemical is dispensed onto the surface of the rotating wafer.

Abstract: A passivation layer is deposited onto the surface of a substrate followed by deposition of a polymer layer, through the application of a plasma enhanced chemical vapor deposition process, in which the substrate is placed on a chuck within a reaction chamber and fluorocarbon gas is introduced into the reaction chamber under the influence of at least one plasma source. The fluorocarbon gas can be a CFX gas. The at least one plasma source can include a first plasma source that ionizes the fluorocarbon gas by applying RF plasma energy, and a second plasma source that applies a near-zero self-bias to the substrate at an RF frequency during deposition of the passivation layer and a greater bias during deposition of the polymer layer. The passivation layer is deposited prior to the polymer layer to protect the surface of the substrate from damage during the deposition of the polymer layer.

Abstract: A method for fabricating a semiconductor device comprises the step of depositing an insulation film 32a with a first pressure set in a deposition chamber; the step of gradually decreasing the pressure in the deposition chamber to a second pressure which is lower than the first pressure; and the step of further depositing the insulation film 32b with the second pressure set in the deposition chamber. The insulation film is deposited with the first pressure a little lower than a second pressure set in a deposition chamber, and the insulation film is further deposited with the second pressure lower than the first pressure set in the deposition chamber. Furthermore, the insulation film is not deposited in the state where the pressure in the deposition chamber is extremely low, and an atmosphere in the deposition chamber is unstable. Thus, a semiconductor device having the insulation film with a sufficiently flat surface can be fabricating without using reflow process.

Abstract: A method of manufacturing a semiconductor device includes forming a buried insulator layer of a semiconductor-on-insulator (SOI) wafer with a dopant material, such as boron, therein. The insulator material with the dopant material may be formed by a number of methods, for example by thermal oxidation of a semiconductor wafer in the presence of an atmosphere containing the dopant material, by co-deposition of the insulator material and the dopant material, or by co-implantation of an insulator material and the dopant material. The dopant material may be the same as a dopant material in at least a region (e.g., a source, drain, or channel region) of a semiconductor material layer which overlies the insulator layer. The dopant material in the buried insulator layer may advantageously reduce the tendency of dopant material to migrate from the overlying material to the insulator layer, such as during manufacturing operations involving heating.

Abstract: A method of forming phoslon (PNO) comprising the following steps. A CVD reaction chamber having a reaction temperature of from about 300 to 600° C. is provided. From about 10 to 200 sccm PH3 gas, from about 50 to 4000 sccm N2 gas and from about 50 to 1000 sccm NH3 gas are introduced into the CVD reaction chamber. Either from about 10 to 200 sccm O2 gas or from about 50 to 1000 sccm N2O gas is introduced into the CVD reaction chamber. An HFRF power of from about 0 watts to 4 kilowatts is also employed. An LFRF power of from about 0 to 5000 watts may also be employed. Employing a phoslon etch stop layer in a borderless contact fabrication. Employing a phoslon lower etch stop layer and/or a phoslon middle etch stop layer in a dual damascene fabrication.

Abstract: The present invention discloses a method of fabricating a thin film in a chamber where a heater and a suscepter are located. The method includes the steps of disposing an object on the susceptor so as to form the thin film thereon; heating the object; a first sub-step of introducing a first gaseous reactant into the first chamber such that the first gaseous reactant is absorbed on the object to form an absorption layer; a second sub-step of introducing a second gaseous reactant into the first chamber such that the second gaseous reactant reacts with the absorption layer absorbed on the object; and a third sub-step of introducing a reducing gas into the first camber such that the reducing gas reduces by-products and impurities of the first and second gaseous reactants.

Abstract: A thin-film forming apparatus of the present invention is capable of reducing variation of film formation rate and forming thin films of a stable thickness. The thin-film forming apparatus can prevent decrease of the film formation rate due to raise of temperatures of an RF electrode and an inner wall of a reaction chamber, by supplying a pressure control gas of a predetermined pressure into the reaction chamber also in non-film formation time to keep a gas pressure in the reaction chamber constant. Thereby, thickness of a film grown on a substrate can be controlled to a constant thickness. Further, by heating the pressure control gas to raise its temperature to a value approximately equal to a temperature of a material gas, variation of the pressure of the gas in the reaction chamber is controlled and the temperatures of the inner wall of the reaction chamber and the RF electrode are kept constant.

Abstract: Organofluorosilicate glass films contain both organic species and inorganic fluorines, exclusive of significant amounts of fluorocarbon species. Preferred films are represented by the formula SivOwCxHyFz, where v+w+x+y+z=100%, v is from 10 to 35 atomic %, w is from 10 to 65 atomic % y is from 10 to 50 atomic %, x is from 1 to 30 atomic %, z is from 0.1 to 15 atomic %, and x/z is optionally greater than 0.25, wherein substantially none of the fluorine is bonded to the carbon. A CVD method includes: (a) providing a substrate within a vacuum chamber; (b) introducing into the vacuum chamber gaseous reagents including a fluorine-providing gas, an oxygen-providing gas and at least one precursor gas selected from an organosilane and an organosiloxane; and (c) applying energy to the gaseous reagents in the chamber to induce reaction of the gaseous reagents and to form the film on the substrate.

Abstract: A wafer W is placed on a lower electrode 108 provided inside a processing chamber 102 of a CVD apparatus 100 and is heated to achieve a temperature equal to or greater than 350° C. and lower than 450° C. SiH4 and SiF4 with both their flow rates set at 20 sccm, B2H6 with its flow rate set at 7 sccm, O2 with its flow rate set at 200 sccm and Ar with its flow rate set at 400 sccm are introduced into the processing chamber 102, and a pressure within the range of 0.01 Torr˜10 Torr is set. 20 W/cm2 power at a frequency of 27.12 MHz and 10 W/cm2 power at a frequency of 400 kHz are respectively applied to an upper electrode 116 and the lower electrode 108 to generate plasma, and a layer insulating film 204 constituted of an SiOB film containing F is formed on the wafer W.

Abstract: Aspects of the invention generally provide a method for polishing a material layer using electrochemical deposition techniques, electrochemical dissolution techniques, polishing techniques, and/or combinations thereof. In one aspect of the invention, the polishing method comprises applying a separate electrical bias, such as a voltage, to each of a plurality of zones of an electrode. Determining the separate biases comprises determining a time that at least one portion of the material layer is associated with each of the zones of the counter-electrode.

Abstract: Disclosed is a method for fabricating a capacitor in a semiconductor device. A semiconductor substrate is provided. A bottom electrode is formed on the substrate by sequentially depositing Ru through a PECVD process and Ru through a LPCVD process on the semiconductor substrate. A Ta2O5 dielectric layer is formed on the bottom electrode and forming a top electrode on the Ta2O5 dielectric layer.

Abstract: A method for carbon doped oxide (CDO) deposition is described. One method of deposition includes providing a substrate and introducing oxygen to a carbon doped oxide precursor in the presence of the substrate. A carbon doped oxide film is formed on the substrate. In another method the substrate is placed on a susceptor of a chemical vapor deposition apparatus. A background gas is introduced along with the carbon doped oxide precursor and oxygen to form the carbon doped oxide film on the substrate.

Abstract: In a semiconductor device having a built-in contact-type sensor, a height of a surrounding part of a sensor part from the exposed surface of the sensor part is reduced. The semiconductor device has a semiconductor element having a built-in sensor. The semiconductor element has a circuit forming surface and a back surface opposite to the circuit forming surface. The contact-type sensor and electrodes are formed on the circuit forming surface. Back electrodes are formed on the back surface. Conductive members extend through the semiconductor device from the electrodes to the back electrodes. A protective film covers the circuit forming surface in a state where the surface of the contact-type sensor is exposed. External connection terminals are electrically connected to the back electrodes.

Abstract: A method for forming a deposited film, comprising generating plasma in a plurality of successive vacuum containers and continuously forming a deposited film on a belt-like substrate while continuously moving the substrate in its longitudinal direction, wherein an opening of a discharge container is adjusted with an opening adjusting plate having a shape set so as to reduce ununiformity of a deposited film thickness in a width direction of the substrate on the basis of a measurement of a deposition rate distribution. Accordingly, there is provided a method and an apparatus for forming a deposited film which are capable of producing a photovoltaic element without ununiformity in characteristics by depositing semiconductor layers without ununiformity in thickness and quality.

Abstract: A substrate with a metal oxide film deposited thereon is annealed, and then the surface of the metal oxide film is exposed to a plasma, after which the metal oxide film is removed by wet-etching.

Abstract: A method of coating a low dielectric constant material layer wherein the wafer surface is pre-wetted using a solvent to prevent or reduce coating defects is described. A semiconductor substrate is provided wherein a top surface of the semiconductor substrate may have surface defects. A solvent is coated overlying the top surface of the semiconductor substrate. A low dielectric constant material layer is coated overlying the solvent wherein the solvent covers the surface defects thereby preventing defects in the low dielectric constant material layer.

Abstract: A method is provided for forming a fluorinated silicate glass layer with HDP-CVD having a lower dielectric constant without compromising the mechanical properties of hardness and compressive stress. A gaseous mixture comprising a silicon-containing gas, an oxygen-containing gas, and a fluorine-containing gas is provided to a process chamber. The ratio of the flow rate of the fluorine-containing gas to the flow rate of the silicon-containing gas is greater than 0.65. A high-density plasma is generated from the gaseous mixture by applying a source RF power having a power density less than 12 W/cm2. A bias is applied to a substrate in the process chamber at a bias power density greater than 0.8 W/cm2 and less than 2.4 W/cm2. The fluorinated silicate glass layer is deposited onto the substrate using the high-density plasma.