Abstract: A method is provided that conditions the chamber walls of a HDP CVD reactor by forming a layer of doped material prior to depositing dielectric layers of the doped material onto wafers. A consistent deposition rate can be maintained during subsequent deposition. When deposition is halted, the chamber is cleaned and a thin layer of the doped material is formed on the walls. Consequently, the chamber is kept at equilibrium even during periods of idle, thereby allowing the deposition rates to be consistent even after deposition resumes after the idle periods. For prolonged idle times, the chamber is re-cleaned and the doped material is re-deposited periodically, such as every 12 hours.

Abstract: A method for controlling a deposition process, includes providing a wafer in a chamber of a deposition tool, the deposition tool being adapted to operate in accordance with a recipe; providing reactant gases to the chamber, the reactant gases reacting to form a layer on the wafer; allowing exhaust gases to exit the chamber; measuring characteristics of exhaust gases; and changing the recipe based on the characteristics of the exhaust gases. A deposition tool includes a chamber, a gas supply line, a gas exhaust line, a gas analyzer, and a controller. The chamber is adapted to receive a wafer. The gas supply line is coupled to the chamber for providing reactive gases. The gas exhaust line is coupled to the chamber for receiving exhaust gases. The gas analyzer is coupled to the gas exhaust line and adapted to determine characteristics of the exhaust gases. The controller is adapted to control the processing of the wafer in the chamber based on the characteristics of the exhaust gases.

Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

Abstract: A method of patterning a metal surface by electro-mechanical polishing is disclosed. A metal surface is placed in fluid communication with an abrasive surface of a pad. The two surfaces are moved relative to each other, in acidic fluid which contains abrasive particles. An electrical circuit is formed between the metal surface and abrasive pad and a current is supplied to the circuit. The patterned surface then is processed into a useful feature such as a bottom electrode for a DRAM capacitor.

Abstract: A method for making an anisotropic dielectric layer includes the steps of: forming a fluid layer comprising a plurality of magnetizable particles, for example, in a fluid capable of solidifying to fix the configuration of the magnetizable particles in a dielectric matrix; aligning the magnetizable particles of the fluid layer in a predetermined configuration by applying a magnetic field thereto; and fixing the aligned magnetizable particles in the predetermined configuration within the dielectric matrix by solidifying the fluid. In one particularly advantageous application, the fluid layer is coated onto a surface portion of an integrated circuit, such as a fingerprint sensor, to provide mechanical protection without effecting the image resolution.

Abstract: A low dielectric constant insulating film on a substrate is formed by introducing a process gas comprising a silicon source, a fluorine source, and oxygen into a chamber. The process gas is formed into a plasma to deposit at least a first portion of the insulating film over the substrate. The wafer and the first portion of the insulating film are then heated to a temperature of about 100-500° C. for a period of time. The film may include several separate portions, the deposition of each of which is followed by a heating step. The film has a low dielectric constant and good gas-fill and stability due to the lack of free fluorine in the film.

Abstract: A fabrication method for an inter-metal dielectric layer is applicable to multi-level interconnects. A substrate is provided with metal lines formed thereon. A first (fluorinated silicon glass) FSG layer with low fluorine content is then formed on the substrate, followed by forming a biased-clamped FSG layer on the first FSG layer. A second FSG layer with low fluorine content is formed on the biased-clamped layer, prior to forming an oxide cap layer on the second FSG layer. The oxide cap layer is planarized until the oxide cap layer is level with the second FSG layer.

Abstract: The present invention provides a manufacturing method of a semiconductor device which does not give rise to peeling of a metal film caused by oxygen held in a interlayer insulating film even when the wafer is subjected to a heat treatment after the metal film is formed on the interlayer insulating film. After the formation of the interlayer insulating film, oxygen held in the interlayer insulating film is removed from the interlayer insulating film, then a metal film on the interlayer insulating film.

Abstract: An exposure apparatus that selects an exposure method that matches exposure conditions, from among a plurality of exposure methods includes an exposure method determining unit for switching between exposure methods and determining an exposure method taking into account at least two of a plurality of evaluation item values calculated based on the exposure conditions, and the exposure method determining unit switches among constant speed scanning exposure method, accelerated/decelerated scanning exposure method and static exposure method.

Abstract: In the fabrication of EDRAM/SDRAM silicon chips with ground rules beyond 0.18 microns, a Si3N4 barrier layer is deposited onto the patterned structure during the borderless polysilicon contact fabrication. It is required that this layer be conformal and has a high hydrogen atom content to prevent junction leakage. These objectives are met with the method of the present invention. In a first embodiment, the Si3N4 layer is deposited in a Rapid Thermal Chemical Vapor Deposition (RTCVD) reactor using a NH3/SiH4 chemistry at a temperature and a pressure in the 600-950° C. and 50-200 Torr ranges respectively. In a second embodiment, it is deposited in a Low Pressure Chemical Vapor Deposition (LPCVD) furnace using a NH3/SiH2Cl2 chemistry (preferred ratio 1:1) at a temperature and a pressure in the 640-700° C. and 0.2-0.8 Torr ranges respectively.

Abstract: A method for cleaning bonding pads on a semiconductor device, as disclosed herein, includes treating the bonding pads with a CF4 and water vapor combination. In the process, the water vapor breaks up and the hydrogen from the water vapor couples to fluorine residue on the bonding pad surface creating a volatile HF vapor. In addition, fluorine from the CF4 exchanges with the titanium in the metallic polymer residue making the polymer more soluble for the organic strip operation which follows. Next, the resist is ashed and then an organic resist stripper is applied to the bonding pad area, thereby creating a clean bonding pad surface. Thereafter, a reliable bond wire connection can be made to the bonding pad.

Abstract: A composite containing nano magnetic particles is provided. The composite includes nano magnetic particles in a dielectric matrix. The matrix is made of an inorganic material such as silica, alumina or hydrosilsesquioxane, or an organic material such as polyimide, polymethyl methacrylate (PMMA) or methyl silsesquioxane. The nano magnetic particles consist of (y-Fe2O3), chromium oxide (CrO2), europium oxide (EuO), NiZn-ferrite, MnZn-ferrite, Yittrium-iron garnet or indium (In).

Abstract: The present invention concerns a method to produce a porous oxygen-silicon insulating layer comprising following steps:

Abstract: A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching conditions, the gap may be substantially 100% filled. Such filling is achieved by adjusting the flow rates of the precursor gases such that the deposition to sputtering ratio during the deposition phases is within certain predetermined limits.

Abstract: A liquid processing apparatus comprises a liquid processing section for applying a liquid processing to wafers W, a carrier delivery section for delivering the carrier housing the wafers W, a carrier stock section capable of storing a plurality of carriers, an interface section for transferring the wafers W between the carrier stock section and the liquid processing section, a carrier transfer device for transferring the carrier, a wafer inspecting device for inspecting the wafers W within the carrier, and a carrier transfer device control section for controlling the carrier transfer device. The carrier transfer device control section controls the carrier transfer device such that the carrier, which has been judged to be capable of a liquid processing on the basis of the result of the inspection of the wafers W, is stored in the carrier stock section, and the liquid processing is started after completion of the inspection of a predetermined number of carriers.

Abstract: A method of forming an arsenic doped oxide layer in a process chamber is disclosed. The method comprises the steps of: setting the process chamber to a temperature of approximately 400-500° C. and a pressure of about 40-250 torr; flowing tetraethylorthosilicate (TEOS) into the process chamber; flowing triethylarsenate (TEAS or TEASAT) into the process chamber; and flowing ozone into the process chamber.

Abstract: Disclosed is a non-solvent method for reducing a dielectric constant of a dielectric film. The dielectric film, which can be formed on a substrate by a spin-on coating or a chemical vapor deposition (CVD), is placed in an atmosphere of an inert gas at a high pressure or in a supercritical fluid state, and then the pressure of the atmosphere is rapidly released to form nanopores on the surface of the dielectric film, whereby the dielectric constant thereof is reduced.

Abstract: Methods of forming dielectric layers and methods of forming capacitors are described. In one embodiment, a substrate is placed within a chemical vapor deposition reactor. In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate and comprises fluorine from the activated fluorine. In another embodiment, a fluorine-comprising material is formed over at least a portion of an internal surface of the reactor. Subsequently, a dielectric layer is chemical vapor deposited over the substrate. During deposition, at least some of the fluorine-comprising material is dislodged from the surface portion and incorporated in the dielectric layer. In another embodiment, the internal surface of the reactor is treated with a gas plasma generated from a source gas comprising fluorine, sufficient to leave some residual fluorine thereover.

Abstract: A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.

Abstract: A method of forming a fluorinated silicon oxide layer or an FSG film having a dielectric constant less than 3.2 is disclosed. The method includes introducing a fluorine-rich gas into a reacting chamber, introducing an oxygen-rich gas into the reacting chamber, creating a plasma environment in the reacting chamber to deposit the FSG film, and adjusting the flow rate of the oxygen-rich gas till the ratio of the flow rate of the oxygen-rich gas to the total flow rate of the fluorine-rich gas and silicon-rich gas is less than or equal to a pre-selected value to form the FSG film. The refraction index (RI) of the fluorinated silicon oxide layer must be greater than or equal to 1.46.

Abstract: At least one strippable film on a surface of a thin film to be patterned is formed, then the at least one strippable film and the thin film to be patterned is patterned by using FIB, and thereafter the at least one strippable film is removed.

Abstract: A method for the in situ cleaning of a semiconductor deposition chamber utilized for the deposition of a semiconductor material such as titanium or titanium nitride comprising, between wafers, introducing chlorine gas into the chamber at elevated temperature, purging the chamber with an inert gas and evacuating it before introduction of the next wafer. A two-stage between wafer cleaning process is carried out by introducing chlorine into the chamber at elevated temperature, thereafter initiating a plasma without removing the chlorine, purging the chamber with an inert gas and evacuating it before introduction of the next wafer. In a preferred embodiment, a thin protective film of titanium is deposited on the inner surfaces of the chamber prior to utilizing the chamber for the deposition of such material. The protective layer is replenished following each two-stage cleaning.

Abstract: The present invention is directed to semiconductor processing operations, and, more particularly, to a method and system for adjusting the thickness of process layers based upon the planarization efficiency of polishing operations. In one embodiment, the invention comprises determining the planarization efficiency of polishing operations, and adjusting the manufactured thickness of a process layer based upon the determined planarization efficiency.

Abstract: A chemical vapor deposition apparatus for forming a semiconductor film, which includes a lateral reaction tube including a susceptor for placing a substrate thereon; a round-shaped heater for heating the substrate; and a gas inlet for introducing a gas containing at least one source gas, the inlet being provided so as to be substantially parallel to the substrate, wherein the heating density of an upstream portion, with respect to the flow of the gas, of the round-shaped heater is higher than that of the remaining portion of the heater. A chemical vapor deposition process employing the chemical vapor deposition apparatus is also disclosed.

Abstract: A process for planarization of a silicon wafer is described together with apparatus for implementing it. The process planarizes by directing a high-energy, pulsed laser beam in a direction parallel to the wafer surface while the wafer is rotating. The height of the beam relative to the wafer is carefully controlled thereby enabling the removal of all material above the lower edge of the beam to be removed from the wafer through laser ablation. The method works equally well for removal of metal (as in planarization of damascene wiring) or dielectric (as in planarization of conventional wiring). Once all excess material has been removed (typically requiring about 60 seconds) additional operation of the process does no harm so neither end point detection nor precise control of process time are required.

Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

Abstract: A structure to enable damascene copper semiconductor fabrication is disclosed. There is a silicon nitride film for providing a diffusion barrier for Cu as well as an etch stop for the duel damascene process. Directly above the silicon nitride film is a silicon oxynitride film. The silicon oxynitride film is graded, to form a gradual change in composition of nitrogen and oxygen within the film. Directly above the silicon oxynitride film is silicon oxide. The silicon oxide serves as an insulator for metal lines. Preferably, the film stack of silicon nitride, silicon oxynitride and silicon oxide is all formed in sequence, within the same plasma-processing chamber, by modifying the composition of film-forming gases for forming each film.

Abstract: The invention provides semiconductor processing methods of depositing SiO2 on a substrate. In a preferred aspect, the invention provides methods of reducing the formation of undesired reaction intermediates in a chemical vapor deposition (CVD) decomposition reaction. In one implementation, the method is performed by feeding at least one of H2O and H2O2 into a reactor with an organic silicon precursor. For example, in one exemplary implementation, such components are, in gaseous form, fed separately into the reactor. In another exemplary implementation, such components are combined in liquid form prior to introduction into the reactor, and thereafter rendered into a gaseous form for provision into the reactor. The invention can be practiced with or in both hot wall and cold wall CVD systems.

Abstract: A method of making a resist pattern is provided, which decreases or eliminates the fluctuation of deformation of original openings of a resist layer which is induced by the change of their density (i.e., the count of the original openings within a unit area) or by their location in the reflowing process. The method comprises the steps of (a) forming a resist layer on a target layer; (b) patterning the resist layer to form original openings and at least one slit in the resist layer; the slit surrounding the original openings and having a specific width; and (c) reflowing the resist layer patterned in the step (b) under heat to cause deformation in the original openings and the at least one slit, thereby contracting the original openings and eliminating the at least one slit; the original openings thus contracted serving as resultant openings for forming desired contact/via holes in the target layer; the resist layer having the resultant openings constituting a resist pattern.

Abstract: A method for improving the reflow characteristics of a BPSG film. According to the method, a fluorine- or other halogen-doped BPSG layer is deposited over a substrate and reflowed using a rapid thermal pulse (RTP) method. The use of such an RTP reflow method results in superior reflow characteristics as compared to a 20-40 minute conventional furnace reflow process. The inventors discovered that reflowing FBPSG films in a conventional furnace may result in the highly mobile fluorine atoms diffusing from the film prior to completion of the anneal. Thus, the FBPSG layer loses the improved reflow characteristics provided by the incorporation of fluorine into the film. The RTP reflow reflows the film in a minimal amount of time (e.g., 10-90 seconds depending on the temperature used to reflow the layer and the degree of planarization required among other factors).

Abstract: Resist film patterns are formed on a light shielding film formed on a surface of the glass substrate. The resist film patterns cover regions A and B of the surface of the substrate. Then, using the resist film patterns as a mask, the light shielding film is patterned to form the light shielding film pattern in the regions A and B. The light shielding film pattern formed in region B is used as a dummy pattern. Then, a further resist film is formed over the light shielding film patterns of the regions A and B. The resist film is patterned to provide only a resist film pattern covering the region A. Thereafter, an etching processing is applied for removing the light shielding film pattern in the region B using the resist film pattern as a mask. In this method, the presence of the dummy pattern is an important feature.

Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, O—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.

Abstract: High rate silicon dioxide deposition at low pressures, including a method of depositing silicon dioxide providing a high rate of deposition at a low process chamber pressure, yielding a film with excellent uniformity and with an absence of moisture inclusion and gas phase nucleation. According to the method, a wafer is placed in a reaction chamber wherein a reactant gas flow of silane and oxygen is directed in parallel with the wafer via a plurality of temperature-controlled gas injectors, and confined to a narrow region above the wafer. The gas is injected at a high velocity resulting in the deposition rate being limited only by the rate of delivery of unreacted gas to the wafer surface and the rate of removal of by-products. The high velocity gas stream passing across the wafer has the effect of thinning the layer adjacent the wafer surface containing reaction by-products, known as the “boundary layer,” which results in faster delivery of the desired reactant gas to the wafer surface.

Abstract: A method of forming an interlayer film on a substrate with a plurality of patterns formed thereon wherein the interlayer film is deposited on the substrate by a process comprising a plurality of steps in each of which a portion of the film is deposited so as to have different fluidity with the same source material.

Abstract: A low dielectric constant insulating film on a substrate is formed by introducing a process gas comprising a silicon source, a fluorine source, and oxygen into a chamber. The process gas is formed into a plasma to deposit at least a first portion of the insulating film over the substrate. The wafer and the first portion of the insulating film are then heated to a temperature of about 100-500° C. for a period of time. The film may include several separate portions, the deposition of each of which is followed by a heating step. The film has a low dielectric constant and good gap-fill and stability due to the lack of free fluorine in the film.

Abstract: Disclosed is a film formation method of an interlayer insulating film which is flattened to cover a wiring layer of a semiconductor integrated circuit device, in which a film-forming gas is activated by converting the film-forming gas into a plasma, the film-forming gas being composed of either a mixed gas containing a phosphorus-containing compound containing trivalent phosphorus, which takes a Si—O—P structure, and a silicon-containing compound containing at most one oxygen atom or an additional mixed gas prepared by adding an oxidative gas to said mixed gas; and a silicon-containing insulating film containing P2O5 is formed on a substrate.

Abstract: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. A fluorinated silicate glass (FSG) layer is formed on the liner layer by using high density plasma chemical vapor deposition (HDPCVD). A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.

Abstract: The method of the present invention is directed to the formation of an arsenic silicon glass (ASG) film onto a silicon structure and finds a valuable application in the buried plate region formation process in the manufacture of deep trench cell capacitors in EDO and SDRAM memory chips. The starting structure is state-of-the-art and consists of a silicon substrate coated by a patterned SiO2/Si3N4 pad layer which defines deep trenches formed therein by etching. At the beginning of the conventional buried plate region formation, the interior side walls of deep trenches are coated with an arsenic doped silicon glass (ASG) film resulting from the co-pyrolysis of TEOS and TEASAT in a vertical hot dual wall LPCVD reactor as standard. According to the present invention, a flow of O2 is added which makes this co-pyrolysis of TEOS and TEASAT no longer interactive. As a consequence, the improved process is much better controlled than the conventional one.

Abstract: A gas pipe system for a process reactor is described, which may be, for example, a vertical oven for depositing an As-doped SiO2 layer onto wafers. The gas pipe system has a TEAS bubbler which is connected on the input side to a carrier gas source and, on the output side, is connected via at least one heated pipe to the process reactor. Furthermore, a TEOS evaporator is provided, which is connected on the input side to a gas source and, on the output side, is connected via at least one heated pipe to the process reactor. Furthermore, a vertical oven and a method for deposition of an As-doped SiO2 layer onto wafers are described, with the gas pipe system being used in each case.

Abstract: A method is shown for manufacturing a semiconductor device in which a silicon oxide film acts as an insulating film for electrically isolating conductive layers included in the semiconductor device. An oxynitride silicon-oxide-like film is formed containing fluorine, carbon and nitrogen and having a given dielectric constant by CVD method using a source gas which contains at least silicon, nitrogen, carbon, oxygen and fluorine contributors. By controlling the ratio of nitrogen to oxygen in the source gas as used in the CVD method, the ultimate nitrogen, carbon and fluorine concentrations in the film can be controlled and hence the dielectric constant of the film so produced.

Abstract: A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.

Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

Abstract: A semiconductor manufacturing process with improved gap fill capabilities is provided by a three step process of FSG deposition/etchback/FSG deposition. A first layer of FSG is partially deposited over a metal layer. An argon sputter etchback step is then carried out to etch out excess deposition material. Finally, a second layer of FSG is deposited to complete the gap fill process.

Abstract: A method of depositing a dielectric film on a substrate in a process chamber of an inductively coupled plasma-enhanced chemical vapor deposition reactor. Gap filling between electrically conductive lines on a semiconductor substrate and depositing a cap layer are achieved. Films having significantly improved physical characteristics including reduced film stress are produced by heating the substrate holder on which the substrate is positioned in the process chamber.

Abstract: A method has been provided to counteract the inherent tension in a deposited film. A wafer substrate is fixed to a wafer chuck having a curved surface. When the chuck surface is convex, a tensile stress is implanted in a deposited film. Upon release from the chuck, the deposited film develops a compressive stress. When the chuck surface is concave, a compressive stress is implanted in the deposited film. Upon release from the chuck, the deposited film develops a tensile stress. Loading a film with a compressive stress is helpful in making films having an inherently tensile stress become thermal stable. Stress loading is also used to improve adhesion between films, and to prevent warping of a film during annealing. A product-by-process using the above-described method is also provided.

Abstract: A method for forming a fluorosilicate glass (FSG) layer. There is first provided a substrate. There is then formed over the substrate a fluorosilicate glass (FSG) layer. Finally, there is then removed, while employing a plasma etch method, a surface layer of the fluorosilicate glass (FSG) layer to form an etched fluorosilicate glass (FSG) layer. Within the method, the surface layer of the fluorosilicate glass (FSG) layer has a higher moisture content than the remaining etched fluorosilicate glass (FSG) layer. The method is particularly applicable for removing hydrated surface layers of chemical mechanical polish (CMP) planarized fluorosilicate glass (FSG) layers to provide non-hydrated underlying remainder layers of chemical mechanical polish (CMP) planarized fluorosilicate glass (FSG) layers which are stabilized with respect to hydrolysis involving loosely bound mobile fluorine atoms.

Abstract: A process for making flexible circuits wherein the etching of a polymeric film is accomplished by dissolving portions thereof with concentrated aqueous base using a UV-curable 100% active liquid photoresist as a mask, comprising the steps of laminating the resist on a polymeric film, exposing a pattern into the resist, developing the resist with a dilute aqueous solution until desired image is obtained, etching portions of the polymeric film not covered by the crosslinked resist with a concentrated base at a temperature of from about 50° C. to about 120° C., and then stripping the resist off the polymeric film.

Abstract: A method for bringing up lower level metal nodes of multi-layered IC devices (200) includes a step of boring a passage (210) down through the obstructing or non-target metal layers (220) exposing these layers, through the Inter Layer Dielectric layers (230), stopping at the target metal layer (240), and a step of depositing Gallium implanted insulator (250, 260) forming a node structure (280) with a conductive core (250) and an insulative sheath (260). The conductive core (250) brings up the target metal node or layer (240) and the insulative sheath (260) isolates the exposed non-target metal nodes or layers (220) from the target metal node (240) and the conductive core (250).

Abstract: An SiOF layer is formed by using as raw material an organic Si compound having Si—F bonds. Since an organic Si compound is used as raw material, an intermediate product being formed during the formation of an SiOF layer is liable to polymerize and has fluidity. Moreover, since the organic Si compound has Si—F bonds, low in bond energy, and is thus capable of easily getting only Si—F bonds separated, the SiOF layer is prevented from getting contaminated by reaction by-products and fluorine can be introduced into the SiOF layer in stable fashion. Therefore, an insulator layer, low in dielectric constant, low in hygroscopicity and excellent in step coverage, can be formed by using a low powered apparatus.

Abstract: The present invention discloses a method for planarizing a semiconductor device used in an integrated circuit. According to the method, a semiconductor substrate on which a patterned layer having topology is formed, is loaded into a reactor chamber. Afterwards, an interlevel insulating layer is formed on the semiconductor substrate. Thereafter, a layer for the planarization containing a dopant is formed on the interlevel insulating layer. The dopant contained in the layer for the planarization, is diffused outwards from the surface of the layer. The dopant diffused outwards from the layer for the planarization is pumped out to the outside of the reactor chamber without introducing an inert gas to the reactor chamber. Finally, the layer for the planarization is flowed.