Abstract: A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO.sub.2) above the fluorinated layer. The fill layer is substantially free of materials formed in part with fluorine. A top surface of the fill layer can be planarized. Surface treatments and oxide caps can be applied to the planarized surface to form fluorine barriers if part of the fluorinated layer is exposed to higher layers. Such a method, and a semiconductor device or integrated circuit manufactured according to the method, allow the dielectric constant of an inter-layer dielectric ("ILD") to be lowered while also minimizing the complexity and expense of the manufacturing process.

Abstract: The present invention pertains to films comprising silicon and oxygen that are doped with carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

Abstract: A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750.degree. C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.

Abstract: This invention provides a method and apparatus for depositing a two-layer structure, including an antireflective coating and a dielectric layer, without any intervening process steps, such as a cleaning step. The invention is capable of providing more accurate and easier fabrication of structures by reducing inaccuracies caused by the reflection and refraction of incident radiant energy within a photoresist layer used in the patterning of the dielectric layer. Additionally, the antireflective coating of the present invention may also serve as an etch stop layer during the patterning of a layer formed over the antireflective coating.

Abstract: Methods of forming dielectric layers and methods of forming capacitors are described. In one embodiment, a substrate is placed within a chemical vapor deposition reactor. In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate and comprises fluorine from the activated fluorine. In another embodiment, a fluorine-comprising material is formed over at least a portion of an internal surface of the reactor. Subsequently, a dielectric layer is chemical vapor deposited over the substrate. During deposition, at least some of the fluorine-comprising material is dislodged from the surface portion and incorporated in the dielectric layer. In another embodiment, the internal surface of the reactor is treated with a gas plasma generated from a source gas comprising fluorine, sufficient to leave some residual fluorine thereover.

Abstract: On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions.

Abstract: An insulating film with a low dielectric constant is more quickly formed on a substrate by reducing the co-etch rate as the film is deposited. The process gas is formed into a plasma from silicon-containing and fluorine-containing gases. The plasma is biased with an RF field to enhance deposition of the film. Deposition and etching occur simultaneously. The relative rate of deposition to etching is increased in the latter portion of the deposition process by decreasing the bias RF power, which decreases the surface temperature of the substrate and decreases sputtering and etching activities. Processing time is reduced compared to processes with fixed RF power levels. Film stability, retention of water by the film, and corrosion of structures on the substrate are all improved. The film has a relatively uniform and low dielectric constant and may fill trenches with aspect ratios of at least 4:1 and gaps less than 0.5 .mu.m.

Abstract: A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Abstract: A method and apparatus for forming a halogen-doped silicon oxide film, preferably a fluorinated silicon glass (FSG) film, having compressive stress less than about -5.times.10.sup.8 dynes/cm.sup.2. In a specific embodiment, the FSG film is formed by a sub-atmospheric CVD thermal process at a pressure of between about 60-650 torr. The relatively thin film, besides having a low dielectric constant and good gap fill capability, has low compressive stress, and is particularly suitable for use as an intermetal (IMD) layer.

Abstract: The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

Abstract: The present invention relates to a film forming method for forming a planarized interlayer insulating film to cover wiring layers, etc. of a semiconductor integrated circuit device. The method includes the steps of forming on a substrate 206, a phosphorus-containing insulating film 45a containing P.sub.2 O.sub.3 by using a film forming gas in which an oxidizing.

Abstract: A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method.

Abstract: A method for preventing bubble defects in borophosphosilicate glass (BPSG) film is provided. A wafer for depositing borophosphosilicate glass (BPSG) film is loaded in deposition chamber. After the wafer is properly positioned, the wafer is heated to a predetermined temperature. A process gas is introduced from the gas distribution system to the deposition chamber. A selected pressure of the deposition chamber is set and maintained throughout deposition process. After deposition of the BPSG film, the wafer is loaded out the chamber. Subsequently, helium gas is introduced to purge the liquid injection valve and delivery path. After pumping out the purge gas, the another wafer is then loaded in the chamber for depositing BPSG film.

Abstract: A method for conditioning a dielectric material on a semiconductor substrate structure during a semiconductor fabrication process, comprising the steps of: irradiating the dielectric material using ultraviolet light irradiation while in a ambient exhibiting the properties of self-limiting oxidation, during a first annealing period; following the first annealing period by exposing the dielectric material to an oxygen ambient during a second annealing period. This method may be applied to the conditioning of a capacitor dielectric on a capacitor structure, or to the conditioning of a field effect transistor gate dielectric on a field effect transistor gate structure or to the conditioning of insulative spacers about the sidewalls of a field effect transistor gate structure.

Abstract: A method of manufacturing a semiconductor device with increasing threshold voltage for parasitic transistor by forming a low power-low pressure phosphosilicate glass layer on the active regions and the field oxide regions.

Abstract: Void formation is avoided without thermal treatment by a gap filling between electrically conductive elements such as stacked gates which are formed atop of isolation regions, with an oxide layer using a HDP technique. The oxide layer is doped with phosphorus to getter mobile ionic contaminants.

Abstract: A silicon oxide film is deposited on a substrate by first introducing a process gas into a chamber. The process gas includes a gaseous source of silicon (such as silane), a gaseous source of fluorine (such as SiF.sub.4), a gaseous source of oxygen (such as nitrous oxide), and a gaseous source of nitrogen (such as N.sub.2). A plasma is formed from the process gas by applying a RF power component. Deposition is carried out at a rate of at least about 1.5 .mu.m/min. The resulting FSG film is stable and has a low dielectric constant.

Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

Abstract: A method is provided for forming tantalum adhesion/barrier layers on semiconductor channels or in vias in low dielectric constant, fluorinated dielectric layers. The dielectric layers are defluorinated using hydrogen, ammonia, methane, or silane plasma and a subsequent tantalum deposition forms a less fluorine reactive tantalum carbide or tantalum silicide. Tantalum or tantalum nitride is then deposited over the less reactive form of tantalum to form the adhesion/barrier for deposition of a subsequent seed layer and a conductive material to form the vias and channels.

Abstract: A method of employing an ambient diffusion barrier to isolate a first dielectric on a silicon substrate against further growth during formation of a second dielectric on the silicon substrate. Subsequent to formation of the diffusion barrier, an exposed surface area of the silicon substrate is subjected to a dielectric forming ambient. The dielectric forming ambient reacts with the exposed silicon surface to form the second dielectric. However, since the first dielectric is isolated, the dielectric forming ambient cannot diffuse therethrough and react with the silicon underlying the first dielectric thereby precluding any further growth in the first dielectric. Using this method, the first and second dielectrics can be formed with differing cross-sectional thicknesses or differing materials.

Abstract: A method of forming an interlayer film on a substrate with a plurality of patterns formed thereon wherein the interlayer film is deposited on the substrate by a process comprising a plurality of steps in each of which a portion of the film is deposited so as to have different fluidity with the same source material.

Abstract: The method for forming an insulating film having a low dielectric constant, which is suitable for intermetal insulating film applications, by plasma enhanced chemical vapor deposition (PECVD) includes the step of supplying a first source gas containing fluorine and carbon to a dual-frequency, high density plasma reactor. The method also includes the step of supplying a second source gas containing silicon dioxide to the reactor. In this manner a fluorocarbon/silicon dioxide film is formed on a substrate in the reactor.

Abstract: The invention provides a semiconductor device in which interlayer insulative layers are composed of amorphous carbon film. The amorphous carbon film may include fluorine (F) therein. The invention further provides a method of fabricating a semiconductor device including an interlayer insulative layer composed of amorphous carbon film including fluorine (F), the method having the step of carrying out plasma-enhanced chemical vapor deposition (PCVD) using a mixture gas including (a) at least one of CF.sub.4, C.sub.2 F.sub.6, C.sub.3 F.sub.8, C.sub.4 F.sub.8 and CHF.sub.3, and (b) at least one of N.sub.2, NO, NO.sub.2, NH.sub.3 and NF.sub.3. The method provides amorphous carbon film having superior heat resistance and etching characteristics. By composing interlayer insulative layers of a semiconductor device of the amorphous carbon film, the semiconductor device can operate at higher speed.

Abstract: The present invention is to a chemical vapor deposition process for depositing a substantially planar, highly reflective layer on a substrate, and is particularly useful for filling high aspect ratio holes in the substrate with metal-containing material. The substrate is placed in a process zone, and successive seeding and oriented crystal growth stages are performed on the substrate. In the seeding stage, the substrate is heated to temperatures T.sub.s, within a first lower range of temperatures .DELTA. T.sub.s, and a seeding gas is introduced into the process zone. The seeding gas deposits a substantially continuous, non-granular, and planar seeding layer on the substrate. Thereafter, in an oriented crystal growth stage, the substrate is maintained at deposition temperatures T.sub.d, within a second higher range of temperatures .DELTA. T.sub.D, and deposition gas is introduced into the process zone.

Abstract: An apparatus and methods for forming a dielectric layer, such as PSG, that exhibits low moisture content, good gap fill capability, good gettering capability, and compatibility with planarization techniques. The PSG film deposited using the apparatus and methods of the present invention are particularly suitable for use as a PMD layer. According to one embodiment, the present invention provides a process for depositing a film on a substrate disposed on a pedestal in a processing chamber. The process includes introducing a process gas into said processing chamber, where the process gas includes SiH.sub.4, PH.sub.3, O.sub.2, and argon. The process also includes controlling the temperature of the pedestal to between about 400-650.degree. C. during a first time period, maintaining a pressure ranging between about 1-10 millitorr in the processing chamber during the first time period.

Abstract: A process for creating BPSG filled, shallow trench isolation regions, in a semiconductor substrate, has been developed. The process features the use of a BPSG layer with about 4 to 4.5 weight percent B.sub.2 O.sub.3, and about 4 to 4.5 weight percent P.sub.2 O.sub.5, in silicon oxide. This BPSG composition, when subjected to a high temperature anneal procedure, results in softening, or reflowing, of the BPSG layer, eliminating seams or voids, in the BPSG layer, that may have been present after BPSG deposition. The removal rate of BPSG, is lower than the removal rate of silicon oxide layer, in buffered HF solutions, thus allowing several buffered HF procedures to be performed without recessing of BPSG in the shallow trench. In addition this composition of BPSG performs as a gettering material for mobile ions, thus contributing to yield and reliability improvements, when used at the isolation region for MOSFET devices.

Abstract: A method and apparatus for improving film stability of a halogen-doped silicon oxide layer. The method includes the step of introducing helium along with the process gas that includes silicon, oxygen and a halogen element. Helium is introduced at an increased rate to stabilize the deposited layer. In a preferred embodiment, the halogen-doped film is a fluorosilicate glass film and TEOS is employed as a source of silicon in the process gas. In still another preferred embodiment, SiF.sub.4 is employed as the fluorine source for the FSG film.

Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO.sub.2 skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH.sub.3 SiH.sub.3, increasing the flow of SiH.sub.4 and keeping the flow of H.sub.2 O.sub.2 constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO.sub.2 skin.

Abstract: A method for making a semiconductor device includes:a step for preparing a substrate;a step for forming a wiring layer on the substrate;a step for loading the substrate onto a substrate supporting unit in a reaction chamber;a step for supplying a material gas essentially consisting of a silane gas, an oxidizing gas and a chalcogen fluoride gas into the reaction chamber; anda step for forming a silicon oxide insulating film containing fluorine on the substrate by a plasma CVD process.

Abstract: A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate. This layer is much less likely to form a haze or bubbles in the layer, and is less likely to desorb water vapor during subsequent processing steps than other FSG layers. An undoped silicon glass (USG) liner protects the substrate from corrosive attack. The USG liner and FSG layers are deposited on a relatively hot wafer surface and can fill trenches on the substrate as narrow as 0.8 .mu.m with an aspect ratio of up to 4.5:1.

Abstract: A substrate for forming a compound semiconductor device is placed in a reaction chamber. An MOCVD method or a GS-MBE method is used to grow compound semiconductor layers on the substrate. The grown layers include, for example, a GaN buffer layer, an n-GaN layer, an InGaN active layer, a p-AlGaN layer, and a p.sup.+ -GaN contact layer. After the growth of the layers, the substrate is kept in the reaction chamber, and a passivation film of, for example, SiNx, SiO2, or SiON is formed on top of the grown layers according to a CVD or GS-MBE method. Since the top of the grown layers is not exposed to air outside the reaction chamber, no oxidization or contamination occurs on the top of the grown layers. The compound semiconductor device is manufactured through simpler processes compared with a prior art that needs separate apparatuses for growing and forming the layers and passivation film.

Abstract: A film forming method is provided for forming a planarized interlayer insulating film for covering interconnection layers, etc. of a semiconductor integrated circuit device. While supplying a reaction gas including a phosphorus containing compound which has III valence phosphorus and at least one bond of phosphorus to oxygen, a silicon containing insulating film including P.sub.2 O.sub.3 is formed on a deposition substrate, thereby greatly reducing fluidization temperature for planarization.

Abstract: A planarized passivation layer is described. A planarized passivation layer of the present invention preferably includes a fluorosilicate glass (FSG) layer and a silicon nitride layer. The FSG layer is preferably deposited using triethoxyfluorosilane (TEFS) and tetraethoxyorthosilicate (TEOS). The inclusion of fluorine in the process chemistry provides good gap-fill characteristics in the film thus formed. The TEFS-based process employed by the present invention employs a low deposition rate, on the order of less than about 4500 .ANG./min, and preferably above 3000 .ANG./min, when depositing the FSG layer. The use of low deposition rate results in a positively sloped profile, preventing the formation of voids during the deposition of the FSG layer and the silicon nitride layer.

Abstract: A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 ohms and non-uniformity values of 5 percent. Resistance values were measured using the four-point probe method with probe spacings of 0.10 cm. After a polysilicon layer has been formed upon a surface of a silicon wafer, a dopant-rich oxide layer is deposited upon the polysilicon layer at reduced pressure. The dopant-rich oxide layer is deposited, and serves as a source of dopant atoms during the subsequent diffusion process. The dopant-rich oxide layer is a phosphosilicate glass (PSG) including phosphorus pentoxide (P.sub.2 O.sub.5) and phosphorus trioxide (P.sub.2 O.sub.3) and deposited using a PECVD technique.

Abstract: A method of forming an interlayer film on a substrate with a plurality of wiring patterns is provided. The interlayer film is deposited on the substrate in a multi step process. A portion of the interlayer film is first deposited in a layer having relatively reduced fluidity so that the film is formed with an almost uniform thickness regardless of any pattern width present on a substrate. Thereafter, a second portion or layer of the intelayer film is deposited in a layer having relatively increased fluidity so that the second layer material fills up any troughs formed between wiring patterns. In a preferred embodiment, an undercoating film may be formed in advance which is then rendered hydrophobic so that the first portion of the interlayer film deposited thereon has reduced fluidity such that the first portion is uniformly deposited regardless of any pattern width.

Abstract: A method of planarizing an inter-layer dielectric layer includes using a high density plasma chemical vapor deposition method to deposit an undoped dielectric, which increases the polishing efficiency in a subsequent chemical-mechanical polishing operation, and eliminates the need for a high temperature densifying treatment for planarization. A chemical-mechanical polishing operation is used to planarize the inter-layer dielectric.

Abstract: A method for forming a UV transmission passivation coating on an integrated circuit, such as EPROM, after completion of the active device and metal routing circuitry comprises depositing a first barrier dielectric layer over the integrated circuit; smoothing out underlying features by applying a layer of flowable dielectric over the first dielectric layer; and depositing a second dielectric layer over the flowable dielectric. Next a photoresist pattern is made over the second dielectric coating, having an opening layer over the at least one conductive pad. A wet etch process is used to remove portions of the second dielectric layer exposed by the opening. A dry etch process is used to remove portions of the remaining layers exposed through the opening, including the remaining portions of the second dielectric layer, the flowable dielectric layer and the first dielectric layer, down to the conductive pad. Finally, the photoresist is removed.

Abstract: An Si--O--F insulating film having a low dielectric constant is deposited on a substrate by thermally reacting disassociated SiF.sub.4 radicals and ozone or oxygen gas in a vacuum chamber. The SiF.sub.4 radicals are formed remotely from the chamber and interact thermally with the ozone or oxygen without requiring plasma enhancement. The deposited Si--O--F film has good gap-filling properties and is suitable for forming IMD layers over high aspect ratio 0.25 micron geometries.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location.

Abstract: A method of forming a BPSG dielectric layer on a wafer without delamination in the fabrication of an integrated circuit device wherein a BPSG deposition chamber is used is described. Semiconductor device structures are provided in and on a semiconductor substrate. The BPSG deposition chamber is cleaned according to the following steps. The deposition chamber is cleaned using a fluorine-containing gas. The fluorine-containing gas is pumped out of the deposition chamber wherein residual fluorine-containing gas remains within the deposition chamber. A plasma is flowed into the deposition chamber wherein the plasma consumes all of the residual fluorine-containing gas. The plasma is purged from the deposition chamber to complete the cleaning of the BPSG deposition chamber. Thereafter, a layer of BPSG is deposited over the semiconductor device structures wherein the BPSG layer is deposited while the wafer is within the BPSG deposition chamber.

Abstract: A silicon oxide film is formed to cover an island non-monocrystalline silicon region by plasma CVD using an organic silane having ethoxy groups (e.g., TEOS) and oxygen as raw materials, while hydrogen chloride or a chlorine-containing hydrocarbon (e.g., trichloroethylene) of a fluorine-containing gas is added to the plasma CVD atmosphere, preferably in an amount of from 0.01 to 1 mol % of the atmosphere so as to reduce the alkali elements from the silicon oxide film formed and to improve the reliability of the film. Prior to forming the silicon oxide film, the silicon region may be treated in a plasma atmosphere containing oxygen and hydrogen chloride or a chlorine-containing hydrocarbon. The silicon oxide film is obtained at low temperatures and this has high reliability usable as a gate-insulating film in a semiconductor device.

Abstract: A method and apparatus for improving film stability of a halogen-doped silicon oxide layer. The method includes the step of introducing a process gas including a first halogen source and a second halogen source, different from the first halogen source, into a deposition chamber along with silicon and oxygen sources. A plasma is then formed from the process gas to deposit a halogen-doped layer over a substrate disposed in the chamber. It is believed that the introduction of the additional halogen source enhances the etching effect of the film. The enhanced etching component of the film deposition improves the film's gap-fill capabilities and helps stabilizes the film. In a preferred embodiment, the halogen-doped film is a fluorosilicate glass film, SiF.sub.4 is employed as the first halogen source, TEOS is employed as a source of silicon and the second halogen source is either F.sub.2 or NF.sub.3.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first layer interconnect pattern overlying a substrate, forming consecutively a thin silicon oxide film and a thick silicon fluoride oxide film, selectively etching the silicon fluoride oxide film to expose a part of the silicon oxide film by using a first gas of a low fluorine content, and etching the exposed silicon oxide film by using a second gas of a high fluorine content to form a via-hole reaching the first layer interconnect pattern The silicon oxide film has a thickness from 50 to 200 nm while the silicon fluoride oxide film has a thickness of 1 .mu.m or higher. The thin silicon oxide film provides a reduced amount of an over-etch while thick silicon fluoride oxide film provides a low capacitance for the interconnect to achieve a higher operation of the LSI.

Abstract: A method for forming a planarized interlevel dielectric layer without degradation due to microloading effect is described. A first conformal layer of silicon dioxide is deposited overlying a conducting layer over an insulating layer on a semiconductor substrate. A second silicon dioxide layer is deposited overlying the first conformal silicon dioxide layer. A doped glass layer is deposited overlying the second silicon dioxide layer. The doped glass layer is coated with a spin-on-glass layer. The spin-on-glass layer is etched back until the interlevel dielectric layer is planarized. The microloading effects from the etching back of the spin-on-glass layer of the interlevel dielectric layer are lower than microloading effects in a conventional interlevel dielectric layer.

Abstract: A method and apparatus for ramping down the deposition pressure in a SACVD process. The present invention also provides a method and apparatus for subsequently ramping up the pressure for a PECVD process in such a manner as to prevent unwanted reactions which could form a weak interlayer interface. In particular, the deposition pressure in the SACVD process is ramped down by stopping the flow of the silicon containing gas (preferably TEOS) and/or the carrier gas (preferably helium), while diluting the flow of ozone with oxygen. A ramp down of the pressure starts at the same time. The diluting of the ozone with oxygen, limits reactions with undesired reactants at the end of a process.

Abstract: A new method for planarization of shallow trench isolation is disclosed by the wet etching and plasma etching, due to the surface sensitivity of SACVD O.sub.3 -TEOS that depends on substrate. The method described herein includes a pad oxide layer, a silicon nitride layer, and a doped polysilicon oxide layer formed on a silicon substrate. A shallow trench is formed by photolithography and dry etching process to etch the doped polysilicon oxide layer, the silicon nitride layer, the pad oxide layer, and the silicon substrate. A SACVD O.sub.3 -TEOS layer is subsequently formed on the on the doped polysilicon oxide layer and filling into the trench, the deposition rate of the ozone-TEOS layer on the doped polysilicon oxide layer is slower than the deposition rate of the ozone-TEOS layer on the silicon wafer, the wet etching rate of the ozone-TEOS layer on the doped polysilicon oxide layer is faster than the etching rate of the ozone-TEOS layer on the silicon wafer.

Abstract: A method and apparatus for forming a multi-constituent device layer on a wafer surface are disclosed. The multi-constituent device layer is formed by flowing a first chemistry comprising a first constituent and a second chemistry comprising a second constituent via a segmented delivery system into a reaction chamber. The reaction chamber comprises a susceptor for supporting and rotating the wafers. The segmented delivery system comprises alternating first and second segments into which the first and second chemistries, respectively, are flowed. The first segments comprise an area that is greater than an area of the second segments by an amount sufficient to effectively reduce the diffusion path of the first constituent. Reducing the diffusion path of the first constituent results in a more uniform distribution of the first constituent within the device layer.

Abstract: An improved sandwich layer of silicon dioxide layers for gap filling between metal lines. This is accomplished using a first layer formed in a PECVD process using TEOS and a fluorine-containing compound to give a barrier layer with a dielectric constant of less than 4.0, preferably approximately 3.5. Subsequently, an SACVD process is used with TEOS to form a gap filling layer. By appropriately choosing the thickness of the respective layers, one can adjust the dielectric to a value which is a combination of the dielectric constants of the two different layers, preferably giving a dielectric constant of approximately 3.6-3.7.

Abstract: A method of fabricating an integrated circuit on a semiconductor substrate is provided including the steps of forming a tungsten silicide conductor structure having a nitride encapsulating layer on the substrate and disposing a doped nonconducting layer over the conductor structure. A self-aligned contact etch is performed wherein the etch is a selective etch of the conductor structure and the nonconducting layer. The selective etch preferentially removes material forming the nonconducting layer rather than material forming the conductor structure. The semiconductor layer is preferably doped with germanium but may also be doped with phosphorous or other known dopants. A germanium concentration of 5% to 25% provides the preferred increased selectivity of the etch. The nonconducting layer can be formed of SG, BPSG, BSG, PSG and TEOS.