Abstract: A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.

Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.

Abstract: Provided are methods for the deposition of films comprising Si(C)N via atomic layer deposition processes. The methods include exposure of a substrate surface to a silicon precursor and a co-reagent comprising a compound selected from the group consisting of N?N?N—R, R2N—NR2, and (R3Si)qNH3-q, wherein q has a value of between 1 and 3, and each R is independently selected from organosilicons, C1-C6 substituted or un-substituted alkanes, branched or un-branched alkanes, substituted or un-substituted alkenes, branched or un-branched alkenes, substituted or un-substituted alkynes, branched or un-branched alkynes or substituted or un-substituted aromatics.

Abstract: The present invention relates to a method of manufacturing a capacitive micro- machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on the first dielectric film (20), the sacrificial layer (30) being removable for forming a cavity (35) of the transducer, depositing a second dielectric film (40) on the sacrificial layer (30), depositing a second electrode layer (50) on the second dielectric film (40), and patterning at least one of the deposited layers and films (10, 20, 30, 40, 50), wherein the depositing steps are performed by Atomic Layer Deposition. The present invention further relates to a capacitive micro-machined transducer (100), in particular a CMUT, manufactured by such method.

Abstract: The present invention provides an electrocatalytic material and a method for making an electrocatalytic material. There is also provided an electrocatalytic material comprising amorphous metal or mixed metal oxides. There is also provided methods of forming an electrocatalyst, comprising an amorphous metal oxide film.

Abstract: The disclosure provides a method of manufacturing a thin film transistor on a base substrate by patterning an active layer comprising a metal oxynitride, and treating the active layer with a plasma comprising oxygen.

Abstract: A method of protecting a perovskite halide film from moisture and temperature includes positioning the perovskite halide film in a chamber. The chamber is maintained at a temperature of less than 200 degrees Celsius. An organo-metal compound is inserted into the chamber. A non-hydrolytic oxygen source is subsequently inserted into the chamber. The inserting of the organo-metal compound and subsequent inserting of the non-hydrolytic oxygen source into the chamber is repeated for a predetermined number of cycles. The non-hydrolytic oxygen source and the organo-metal compound interact in the chamber to deposit a non-hydrolytic metal oxide film on perovskite halide film. The non-hydrolytic metal oxide film protects the perovskite halide film from relative humidity of greater than 35% and a temperature of greater than 150 degrees Celsius, respectively.

Abstract: A method of forming a semiconductor structure includes growing a second III-V compound layer over a first III-V compound layer, wherein the second III-V compound layer has a different band gap from the first III-V compound layer. The method further includes forming a source feature and a drain feature over the second III-V compound layer. The method further includes forming a gate dielectric layer over the second III-V compound layer, the source feature and the drain feature. The method further includes implanting at least one fluorine-containing compound into a portion of the gate dielectric layer. The method further includes forming a gate electrode over the portion of the gate dielectric layer.

Abstract: A method for measuring the changes of the electrical performance of an FDSOI transistor between a first and a second state of the transistor after an operating period t1, including the following steps: measurement of the transistor's capacities C1 and C2 respectively in the first and second states, according to a voltage VFG applied between the gate and the source and drain areas, determination, in relation to characteristic C1(VFG) varying between a maximum value Cmax and a minimum value Cmin, with three inflection points, of an ordinate value Cplat of C1(VFG) at the second inflection point of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) according to equations VUpper(0)=C1?1((Cmax+Cplat)/2) and VLower(0)=C1?1((Cmin+Cplat)/2), determination, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) according to equations VUpper(t1)=C2?1((Cmax+Cplat)/2) and VLower(t1)=C2?1((Cmin+Cplat)/2), determination of variations of defect densities ?Dit1, ?Dit2 b

Abstract: A semiconductor device includes a semiconductor-on-insulator substrate having an insulator layer, and at least one silicon germanium (SiGe) fin having a superlattice structure. The SiGe fin is formed on an upper surface of the insulator layer. A gate stack is formed on an upper surface of the at least one silicon germanium fin. The gate stack includes first and second opposing spacers defining a gate length therebetween. First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a silicon germanium gate channel beneath the gate stack.

Abstract: Processes for controlling the growth and thickness of two-dimensional transition metal dichalcogenides are provided. The process modifies an insulator substrate surface with an electron or ion beam to create charged areas on the substrate surface. The treated surface allows for hydroxylation of the charged species which serves as nucleation sites for the seed particles during chemical vapor deposition that promotes growth of thin layers of transition metal dichalcogenides.

Abstract: A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

Abstract: A semiconductor device includes a dielectric layer on a substrate, a P-type transistor having a first gate stack embedded in the dielectric layer, and an N-type transistor having a second gate stack embedded in the dielectric layer. The first gate stack includes a first metal gate electrode, a first gate dielectric layer underlying the first metal gate electrode, and a first cap layer between the first gate dielectric layer and the first metal gate electrode. The second gate stack includes a second metal gate electrode, a second gate dielectric layer underlying the second metal gate electrode, and a second cap layer between the second gate dielectric layer and the second metal gate electrode. The first and second gate stacks are adjacent, and the first and second metal gate electrodes are separated from each other by the first and second cap layers.

Abstract: Provided are methods of fabricating memory cells such as resistive random access memory (ReRAM) cells. A method involves forming a first layer including two high-k dielectric materials such that one material has a higher dielectric constant than the other material. In some embodiments, hafnium oxide and titanium oxide form the first layer. The higher-k material may be present at a lower concentration. In some embodiments, a concentration ratio of these two high-k materials is between about 3 and 7. The first layer may be formed using atomic layer deposition. The first layer is then annealed in an oxygen-containing environment. The method may proceed with forming a second layer including a low-k dielectric material, such as silicon oxide, and forming an electrode. After forming the electrode, the memory cell is annealed in a nitrogen containing environment. The nitrogen anneal may be performed at a higher temperature than the oxygen anneal.

Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.

Abstract: First, a product to be inspected is prepared. The product to be inspected includes a substrate and a first film formed on the substrate. TDS is performed while the temperature of the product to be inspected is raised to 1,000° C. or higher, and the quality of the product to be inspected is determined by checking for the presence or absence of a peak at 1,000° C. or higher. Meanwhile, the substrate is, for example, a semiconductor substrate such as a silicon substrate. In addition, the rate of temperature rise is, for example, equal to or higher than 40° C./min and equal to or lower than 80° C./min. The upper limit of the temperature of TDS is, for example, 1,300° C.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: Provided are resistive random access memory (ReRAM) cells having switching layers that include hafnium, aluminum, oxygen, and nitrogen. The composition of such layers is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. In some embodiments, the concentration of nitrogen in a switching layer is between about 1 and 20 atomic percent or, more specifically, between about 2 and 5 atomic percent. Addition of nitrogen helps to control concentration and distribution of defects in the switching layer. Also, nitrogen as well as a combination of two metals helps with maintaining this layer in an amorphous state. Excessive amounts of nitrogen reduce defects in the layer such that switching characteristics may be completely lost. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD).

Abstract: An embodiment fin field effect transistor (FinFET) device and method of forming the same. An embodiment method of forming a fin field effect transistor (FinFET) includes forming fins from a semiconductor substrate, forming a field oxide between the fins, forming a sacrificial gate over a channel region of the fins projecting from the field oxide, and implanting ions through the sacrificial gate to provide the channel region of the fins with a uniform doping profile.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: Disclosed are hafnium-containing and zirconium-containing precursors and methods of synthesizing the same. The compounds may be used to deposit hafnium, zirconium, hafnium oxide, and zirconium oxide containing layers using vapor deposition methods such as chemical vapor deposition or atomic layer deposition.

Abstract: According to example embodiments, a method of forming a layer includes: forming a dielectric layer using a metal precursor expressed by one of R3yM(NR1R2)x-y and M(OR1R2) and using a silicon precursor expressed by HzSi(NR4R5)4-z. Each of “R1”, “R2”, “R3”, “R4”, and “R5” are hydrogen or hydrocarbon; “R3” is different than “R1” and “R2”; “x” is in the range of 3 to 5; “y” is in the range of 1 to 4; “z” is in the range of 2 to 3; and “M” is a metal. The dielectric layer is a metal silicate layer or a metal nitride layer doped with silicon.

Abstract: A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

Abstract: A semiconductor manufacturing equipment includes a buffer chamber, a load port, a first chamber, and a second chamber respectively connected with the buffer chamber at a different side. The semiconductor manufacturing equipment also has a third chamber in the buffer chamber, the third chamber configured for cooling a wafer, and a single blade robot in the buffer chamber. Moreover, the semiconductor manufacturing equipment has a controller including a program, wherein the program elevates a wafer transfer priority for the first chamber and the second chamber higher than a wafer transfer priority for the third chamber.

Abstract: Methods and apparatus for forming a dielectric layer for use as a gate dielectric are provided. A high-k layer is formed with first ALD process using a halogen-based precursor. The metal in the halogen-based precursor may be at least one of hafnium, zirconium, or titanium. The halogen in the halogen-based precursor may be at least one of fluorine, chlorine, or iodine. In some embodiments, the halogen-based metal precursor includes hafnium chloride. The remainder of the high-k layer is formed with second ALD process using a metal organic-based precursor. The metal in the metal organic-based precursor may be at least one of hafnium, zirconium, or titanium. The organic ligands in the metal organic-based precursor may be at least one of ?-diketonate precursors, alkoxide precursors, amino precursors. In some embodiments, the metal organic-based precursor includes amino precursors.

Abstract: A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region.

Abstract: A wafer processing method of dividing a wafer along a plurality of crossing streets formed on the wafer to obtain individual chips. The wafer processing method includes a modified layer forming step of applying a laser beam having a transmission wavelength to the wafer along each street to thereby form a modified layer inside the wafer and a dividing step of applying an external force to the wafer to thereby divide the wafer into the individual chips along each street with the modified layer functioning as a division start point. In the modified layer forming step, the modified layer is formed at each intersection of the crossing streets at a height where cracking can be avoided on the corner edges of each chip obtained by dividing the wafer.

Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.

Abstract: A method of depositing a material on a substrate using an atomic layer deposition process, wherein the deposition process comprises a first deposition step, a second deposition step subsequent to the first deposition step, and a delay of at least one minute between the first deposition step and the second deposition step. Each deposition step comprises a plurality of deposition cycles. The delay is introduced to the deposition process by prolonging a period of time for which a purge gas is supplied to a process chamber housing the substrate at the end of a selected one of the deposition cycles.

Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Abstract: With a stage kept in an as-heated state, a semiconductor wafer is placed over the stage. Then, with the elapse of a first time, a controller causes a pressure inside a vacuum chamber to rise to a second pressure higher than a first pressure (step S40). After the semiconductor wafer is placed over the stage, a pressure difference between a pressure inside the vacuum chamber and a pressure inside an adsorption port is set to a minimum value at which the semiconductor wafer is not allowed to slide over protrusions. Further, in step S40 as well, the pressure difference is kept at the minimum value at which the semiconductor wafer is not allowed to slide over the protrusions.

Abstract: High performance thin-film, transistors are entirely processed at temperatures not exceeding 150° C., using amorphous multi component dielectrics based on the mixture of high band gap and high dielectric constant (K) materials. The sputtered or ink jet printed mixed dielectric materials such as Ta2O5 with SiO2 or Al2O3 or HfO2 with SiO2 or Al2O3 are used. These multicomponent dielectrics allow producing amorphous dielectrics to be introduced in high stable electronic devices with low leakage currents, while preserving a high dielectric constant. This results in producing thin film transistors with remarkable electrical properties, such as the ones produced based on Ga—In—Zn oxide as channel layers and where the dielectric was the combination of the mixture Ta2O5:SiO2, exhibiting field-effect mobility exceeding 35 cm2 V?1 s?1, close to 0 V turn-on voltage, on/off ratio higher than 106 and subthreshold slope below 0.24 V dec?1.

Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.

Abstract: The present invention is directed to a method for forming a magnetic tunnel junction (MTJ) memory element comprising the steps of providing a substrate having a bottom electrode layer thereon; depositing an MTJ layer stack on top of the bottom electrode layer; forming a composite hard mask comprising a bottom conducting mask disposed on top of the MTJ layer stack and a top conducting mask with a dielectric mask interposed therebetween; etching the MTJ layer stack with the composite hard mask thereon to form a patterned MTJ while consuming the top conducting mask, thereby exposing the dielectric mask on top; and trimming the patterned MTJ with the bottom conducting mask and the dielectric mask thereon by ion beam etching to remove redeposited material and damaged material from surface of the patterned MTJ while consuming most of the dielectric mask.

Abstract: Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer.

Abstract: A method for forming a resistive random access memory (RRAM) device is disclosed. The method comprises forming a first electrode, forming a resistive switching oxide layer comprising a metal oxide by thermal atomic layer deposition (ALD) and forming a second electrode by thermal atomic layer deposition (ALD), where the resistive switching layer is interposed between the first electrode and the second electrode. Forming the resistive switching oxide may be performed without exposing a surface of the switching oxide layer to a surface-modifying plasma treatment after depositing the metal oxide.

Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Abstract: Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.

Abstract: The present invention relates to novel 4B group metalorganic compounds represented by following formula I and the preparation thereof. Specifically, the present invention relates to a thermally and chemically stable 4B group organo-metallic compound utilized in chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the preparation thereof. A 4B group metalorganic compound prepared according to the present invention volatiles easily and is stable at high temperature, and can be used effectively in manufacturing 4B group metal oxide thin films. wherein M represents Ti, Zr or Hf, R1 represents C1˜C4 alkyl, R2 and R3 represent independently C1˜C6 alkyl.

Abstract: Provided are methods of surface treatment of nanocrystal quantum dots after film deposition so as to exchange the native ligands of the quantum dots for exchange ligands that result in improvement in charge extraction from the nanocrystals.

Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes: housing a substrate into a processing chamber; and forming a metal nitride film on the substrate by supplying a source gas containing a metal element, a nitrogen-containing gas and a hydrogen-containing gas into the processing chamber; wherein in forming the metal nitride film, the source gas and the nitrogen-containing gas are intermittently supplied into the processing chamber, or the source gas and the nitrogen-containing gas are intermittently and alternately supplied into the processing chamber, or the source gas is intermittently supplied into the processing chamber in a state that supply of the nitrogen-containing gas into the processing chamber is continued, and the hydrogen-containing gas is supplied into the processing chamber during at least supply of the nitrogen-containing gas into the processing chamber.

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract: Methods of forming rutile titanium dioxide comprise exposing a transition metal (such as V, Cr, W, Mn, Ru, Os, Rh, Ir, Pt, Ge, Sn, or Pb) to an atmosphere consisting of oxygen gas (O2) to produce an oxidized transition metal over an unoxidized portion of the transition metal. Rutile titanium dioxide is formed over the oxidized transition metal by atomic layer deposition. The oxidized transition metal is sequentially exposed to a titanium halide precursor and an oxidizer. Other methods include oxidizing a portion of a ruthenium material to ruthenium(IV) oxide using an atmosphere consisting of O2, nitric oxide (NO), or nitrous oxide (N2O); and introducing a gaseous titanium halide precursor and water vapor to the ruthenium(IV) oxide to form rutile titanium dioxide on the ruthenium(IV) oxide by atomic layer deposition. Some methods include exposing transition metal to an atmosphere consisting essentially of O2, NO, and N2O.

Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.

Abstract: A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second layer of the metal-oxide dielectric on the refractory metal silicon nitride. Depositing the first layer may include depositing a metal-oxide dielectric, such as HfO2, using atomic layer deposition. Forming the refractory metal silicon nitride film may include forming a film of tantalum silicon nitride using a physical vapor deposition process. Annealing the gate dielectric stack may include annealing the gate dielectric stack in an oxygen-bearing ambient at approximately 750 C for 10 minutes or less. In one embodiment, annealing the dielectric stack includes annealing the dielectric stack for approximately 60 seconds at a temperature of approximately 500 C.

Abstract: [Object] To provide a composition for forming a tungsten oxide film from an aqueous solution, and also to provide a pattern formation method employing that composition. [Means] The present invention provides a tungsten oxide film-forming composition comprising: water, a water-soluble metatungstate, and at least one additive selected from the group consisting of anionic polymers, nonionic polymers, anionic surfactants, and tertiary amino group-containing nonionic surfactants. For forming a pattern, this composition can be employed in place of a silicon dioxide film-forming composition in a pattern formation process using an image reversal trilayer structure, a resist undercoat layer or a resist top protective film.

Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.