Insulative Material Is Compound Of Refractory Group Metal (i.e., Titanium (ti), Zirconium (zr), Hafnium (hf), Vanadium (v), Niobium (nb), Tantalum (ta), Chromium (cr), Molybdenum (mo), Tungsten (w), Or Alloy Thereof) Patents (Class 438/785)
  • Patent number: 8691710
    Abstract: Metal-containing complexes with general formula (1) (R1nPyr)(R2nPyr)ML1L2; or (2) [(R8XR9)(R1nPyr)(R2nPyr)]ML1L2 are disclosed; wherein M is a Group IV metal, Pyr is pyrrolyl ligand, n=1, 2 and 3, L1 and L2 are independently selected from alkoxide, amide or alkyl, L1 and L2 can be linked together, R1 and R2 can be same or different organic groups substituted at 2,3,4-positions of the pyrrole ring and are selected from the group consisting of linear and branched C1-6 alkyls, R8 and R9 are independently selected from the linear or branched chain alkylene group having 2-6 carbon atoms, and X is CH2 or oxygen. Methods of using the metal complexes as precursors to deposit metal or metal oxide films used for various devices in semi-conductor industries are also discussed.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 8, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Wade Hampton Bailey, III, Sergei Vladimirovich Ivanov, Xinjian Lei, Moo-Sung Kim
  • Patent number: 8685815
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8685866
    Abstract: A method of manufacturing a semiconductor device including alternately repeating a process of forming a first metal oxide film including a first metal element and a process of forming a second metal oxide film including a second metal element on a substrate accommodated in a processing chamber, so as to form a third metal oxide film including the first and second metal elements with a predetermined composition ratio on the substrate. One of the first and second metal elements of the third metal oxide film has a concentration higher than a concentration of the other, and one of the first and second metal oxide films including the higher-concentration metal element is formed in a chemical vapor deposition (CVD) mode or an atomic layer deposition (ALD) saturation mode, and the other of the first and second metal oxide films is formed in an ALD unsaturation mode.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 1, 2014
    Assignees: Hitachi Kokusai Electric, Inc., Renesas Electronics Corp.
    Inventors: Sadayoshi Horii, Atsushi Sano, Masahito Kitamura, Yoshitake Kato
  • Patent number: 8685787
    Abstract: One object is to have stable electrical characteristics and high reliability and to manufacture a semiconductor device including a semi-conductive oxide film. Film formation is performed by a sputtering method using a target in which gallium oxide is added to a material that is easy to volatilize compared to gallium when the material is heated at 400° C. to 700° C. like zinc, and a formed film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film and the oxide is crystallized. Further, a semi-conductive oxide film is deposited thereover, whereby a semi-conductive oxide having a crystal which succeeds a crystal structure of the oxide that is crystallized by heat treatment is formed.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8679913
    Abstract: A film is formed so that the atomic numbers ratio of Sr to Ti, i.e., Sr/Ti, in the film is not less than 1.2 and not more than 3. The film is then annealed in an atmosphere containing not less than 0.001% and not more than 80% of O2 at 500° C. or above. An SrO film forming step or a TiO film forming step are repeated a plurality of times so that a sequence, in which a plurality of SrO film forming steps or/and a plurality of TiO film forming steps are performed continuously, is included. When Sr is oxidized after the adsorption of Sr, O3 and H2O are used as an oxidizing agent.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: March 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Yumiko Kawano, Susumu Arima, Akinobu Kakimoto, Toshiyuki Hirota, Takakazu Kiyomura
  • Patent number: 8679988
    Abstract: In some embodiments, the present invention discloses plasma processing at interfaces of an ALD metal oxide film with top and bottom electrodes to improve the ReRAM device characteristics. The interface processing can comprise an oxygen inhibitor step with a bottom polysilicon electrode to prevent oxidation of the polysilicon layer, enhancing the electrical contact of the metal oxide film with the polysilicon electrode. The interface processing can comprise an oxygen enrichment step with a top metal electrode to increase the resistivity of the metal oxide layer, providing an integrated current limiter layer.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 25, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Chi-I Lang
  • Patent number: 8679952
    Abstract: A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T1 for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: March 25, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuyuki Tomita, Kenichi Hamano, Masayoshi Tarutani, Yoichiro Mitani, Takeharu Kuroiwa, Masayuki Imaizumi, Hiroaki Sumitani, Kenichi Ohtsuka, Tomoaki Furusho, Takao Sawada, Yuji Abe
  • Publication number: 20140080320
    Abstract: A method for using a system, which includes a film formation apparatus for forming a high-dielectric constant thin film on target substrates together and a gas supply apparatus for supplying a process gas. The method includes a preparatory stage of determining a set pressure range of pressure inside a vaporizing chamber for a liquid material cooled at a set temperature. The preparatory stage includes obtaining a first limit value of pressure at which vaporization of the liquid material starts being inhibited due to an increase in the pressure, obtaining a second limit value of pressure at which vaporization of the liquid material starts being unstable and the pressure starts pulsating movement due to a decrease in the pressure, and determining the set pressure range to be defined by an upper limit lower than the first limit value and a lower limit higher than the second limit value.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 20, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tsuneyuki OKABE, Hitoshi Katoh, Junya Hiraka, Hiroyuki Kikuchi
  • Patent number: 8669131
    Abstract: Gas sensor materials and methods are disclosed for preparing and using the same to produce gas sensor structures. Also disclosed are gas sensor structures and systems that employ these disclosed materials. A gas sense-enhancing metal such as platinum may be added to a gas sensitive metal oxide material in a manner that more highly disperses the added platinum than conventional methods so as to more effectively utilize the platinum at a lower concentration, thus achieving a more cost effective solution. An ink vehicle may also be used for deposition of a gas sensitive material (e.g. on the surface of integrated circuit) that is formulated to allow “burn-out” of ink vehicle components at relatively low temperatures as compared to conventional ink vehicles.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 11, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Peter Smith, Jane Blake, Leon Cavanagh, Raymond Speer
  • Patent number: 8658501
    Abstract: In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Supratik Guha, Vijay Narayanan, Vamsi K. Paruchuri
  • Patent number: 8658546
    Abstract: A solution composition for forming an oxide thin film may include a first compound including zinc, a second compound including indium, and a third compound including magnesium or hafnium, and an electronic device may include an oxide semiconductor including zinc, indium, and magnesium. The zinc and hafnium may be included at an atomic ratio of about 1:0.01 to about 1:1.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: February 25, 2014
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation
    Inventors: Jong-Baek Seon, Hyun-Jae Kim, Sang-Yoon Lee, Myung-Kwan Ryu, Hyun-Soo Shin, Kyung-Bae Park, Woong-Hee Jeong, Gun-hee Kim, Byung-Du Ahn
  • Patent number: 8652957
    Abstract: A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8633119
    Abstract: Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: January 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya E. Sato, Maitreyee Mahajani
  • Patent number: 8633534
    Abstract: An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 21, 2014
    Assignee: Intel Corporation
    Inventors: Michael G. Haverty, Sadasivan Shankar
  • Publication number: 20140017907
    Abstract: A method is provided for forming a nitrided high-k film in an atomic layer deposition process (ALD) process. The method includes receiving a substrate in a process chamber, maintaining the substrate at a temperature sufficient for ALD of a nitrided high-k film, and depositing the nitrided high-k film on the substrate by exposing the substrate to a gas pulse sequence that includes, in any order: a) exposing the substrate to a gas pulse comprising a metal-containing precursor, b) exposing the substrate to a gas pulse comprising an oxygen-containing gas, and c) exposing the substrate to a gas pulse comprising trisilylamine gas, where the exposing the substrate to the trisilylamine gas yields the nitrided high-k film that includes nitrogen and that is substantially free of silicon, and repeating the gas pulse sequence. A trisilylamine gas exposure may also be used to nitride a deposited high-k film.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 16, 2014
    Inventors: Steven P. Consiglio, Robert D. Clark, Christian Dussarrat, Vincent Omarjee, Venkat Pallem, Glenn Kuchenbeiser
  • Publication number: 20140017906
    Abstract: A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 16, 2014
    Inventors: Zuozhen Fu, Huaxiang Yin, Jiang Yan
  • Patent number: 8623750
    Abstract: A film of silicon dioxide is formed on the silicon-germanium layer, and a high dielectric constant film is further formed on the film of silicon dioxide. First irradiation from a flash lamp is performed on the semiconductor wafer to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 3 milliseconds to 1 second. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 3 milliseconds to 1 second. This promotes the crystallization of the high dielectric constant film while suppressing the alleviation of distortion in the silicon-germanium layer.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: January 7, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Kazuhiko Fuse, Shinichi Kato
  • Patent number: 8623770
    Abstract: A method for sidewall spacer line doubling uses thermal atomic layer deposition (ALD) of a titanium oxide (TiOx) spacer layer. A hardmask layer is deposited on a suitable substrate. A mandrel layer of diamond-like carbon (DLC) is deposited on the hardmask layer and patterned into stripes with tops and sidewalls. A layer of TiOx is deposited, by thermal ALD without the assistance of plasma or ozone, on the tops and sidewalls of the mandrel stripes. Thermal ALD of the TiO2, without energy assistance by plasma or ozone, has been found to cause no damage to the DLC mandrel stripes. After removal of the TiOx from the tops of the mandrel stripes and removal of the mandrel stripes, stripes of TiO2 are left on the hardmask layer and may be used as an etch mask to transfer the pattern into the hardmask layer.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: January 7, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: He Gao, Jeffrey S. Lille, Kanaiyalal Chaturdas Patel
  • Patent number: 8623671
    Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: January 7, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Nobumichi Fuchigami, Pragati Kumar, Prashant Phatak
  • Publication number: 20130344692
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Dina Triyoso, Elke Erben, Robert Binder
  • Publication number: 20130337659
    Abstract: The present invention relates to novel 4B group metalorganic compounds represented by following formula I and the preparation thereof. Specifically, the present invention relates to a thermally and chemically stable 4B group organo-metallic compound utilized in chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the preparation thereof. A 4B group metalorganic compound prepared according to the present invention volatiles easily and is stable at high temperature, and can be used effectively in manufacturing 4B group metal oxide thin films. wherein M represents Ti, Zr or Hf, R1 represents C1˜C4 alkyl, R2 and R3 represent independently C1˜C6 alkyl.
    Type: Application
    Filed: March 2, 2012
    Publication date: December 19, 2013
    Applicant: MECHARONICS CO. LTD.
    Inventors: Dae-jun Ahn, Hyun-chang Kim
  • Publication number: 20130337625
    Abstract: The present invention provides a method for manufacturing a semiconductor device including a metal compound film formation process based on an atomic layer deposition (ALD) with repeating a plurality of cycles in which a supply time of a metallic source gas at the first time of the cycles is longer than a supply time of the source gas at the second time or later of the cycles, the ALD including, as one cycle, supplying the metallic source gas to adsorb a metallic source onto a foundation; purging the metallic source gas from a film-forming space; supplying a reactant gas to convert the metallic source into a corresponding metal compound; and purging the reactant gas.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 19, 2013
    Inventor: Naonori FUJIWARA
  • Patent number: 8609553
    Abstract: Methods of forming rutile titanium dioxide. The method comprises exposing a transition metal (such as V, Cr, W, Mn, Ru, Os, Rh, Ir, Pt, Ge, Sn, or Pb) to oxygen gas (O2) to oxidize the transition metal. Rutile titanium dioxide is formed over the oxidized transition metal. The rutile titanium dioxide is formed by atomic layer deposition by introducing a gaseous titanium halide precursor and water to the oxidized transition metal. Methods of forming semiconductor structures having rutile titanium dioxide are also disclosed.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chris Carlson
  • Publication number: 20130313657
    Abstract: In some embodiments, the present invention discloses a gate dielectric deposition process, including depositing a fluorinated hafnium oxide by an ALD process utilizing a fluorinated hafnium precursor and an oxidant. A two-step ALD deposition process can be used, including a fluorinated hafnium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide high dielectric constant, high density, large bandgap and good thermal stability. Fluorinated hafnium oxide can passivate interface states and bulk traps in the hafnium oxide, for example, by forming Si—F or Hf—F bonds, which can improve the reliability of the hafnium oxide gate dielectrics.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: Intermolecular, Inc.
    Inventor: Jinhong Tong
  • Publication number: 20130316546
    Abstract: In some embodiments, the present invention discloses a two-step deposition process for forming hafnium oxide gate dielectric, comprising an interface layer deposition followed by a bulk layer deposition. In the interface layer deposition process, water is used as an oxidizer precursor together with a hafnium-containing precursor. In the bulk layer deposition process, oxygen or ozone is used as an oxidizer precursor together with a hafnium-containing precursor.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: Intermolecular, Inc.
    Inventor: Jinhong Tong
  • Publication number: 20130302998
    Abstract: An ammonium thio-transition metal complex is used as an adhesion promoter for immobilizing temperature-stable transition metal oxide layers on an inert metal surface. The ammonium thio-transition metal complex comprises a transition metal selected from molybdenum, tungsten and vanadium, and is preferably ammonium tetrathiomolybdate. A precursor of the transition metal oxide is deposited on the inert metal surface by a solution-based process. The precursor is a dispersion or a dissolution of the transition metal oxide, a transition metal oxide hydrate, an ammonium salt of an acidic transition metal oxide hydrate or phosphoric acid-transition metal oxide complex in water or a phosphoric acid-transition metal oxide complex dissolved in a polar organic solvent.
    Type: Application
    Filed: December 1, 2011
    Publication date: November 14, 2013
    Applicant: CAMBRIDGE DISPLAY TOCHNOLOGY LIMITED
    Inventor: Thomas Kugler
  • Patent number: 8580671
    Abstract: A method of manufacturing a semiconductor device of the present invention includes a first step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminum, zirconium, strontium, titanium, barium, tantalum, niobium, on a substrate having a metal thin film formed on the surface, at a first temperature allowing no oxidization of the metal thin film to occur, and allowing the metal oxide film to be set in an amorphous state; and a second step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminum, zirconium, strontium, titanium, barium, tantalum, niobium on the metal oxide film formed in the first step, up to a target film thickness, at a second temperature exceeding the first temperature.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Sadayoshi Horii, Yoshinori Imai, Mika Karasawa
  • Publication number: 20130295778
    Abstract: Compound of the formula Cp(R1)mM(NR22)2(?NR3) (I): wherein: M is a metal independently selected from Vanadium (V) or Niobium (Nb) and m?5; R1 is an organic ligand, each one independently selected in the group consisting of H, linear or branched hydrocarbyl radical comprising from 1 to 6 carbon atom; R2 is an organic ligand, each one independently selected in the group consisting of H, linear or branched hydrocarbyl radical comprising from 1 to 6 carbon atom; R3 is an organic ligand selected in the group consisting of H, linear or branched hydrocarbyl radical comprising from 1 to 6 carbon atom.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 7, 2013
    Inventor: L'Air Liquide, Société Anonyme pour I'Etude et l'Exploitation des Procédés Georges
  • Patent number: 8563444
    Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according to some embodiments can be used to form silicon-rich hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surface.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: October 22, 2013
    Assignee: ASM America, Inc.
    Inventors: Chang-Gong Wang, Eric Shero, Glen Wilk
  • Patent number: 8558295
    Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 15, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Min Yoon, Chun Won Byun, Shin Hyuk Yang, Sang Hee Park, Soon Won Jung, Seung Youl Kang, Chi Sun Hwang, Byoung Gon Yu
  • Patent number: 8557713
    Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Jin Lim, Hyung-Suk Jung, Yun-Ki Choi
  • Patent number: 8546275
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: October 1, 2013
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik, Tony Chiang
  • Patent number: 8546276
    Abstract: Disclosed are group IV metal-containing precursors and their use in the deposition of group IV metal-containing films {nitride, oxide and metal) at high process temperature. The use of cyclopentadienyl and imido ligands linked to the metal center secures thermal stability, allowing a large deposition temperature window, and low impurity contamination. The group IV metal (titanium, zirconium, hafnium)-containing f{umlaut over (?)}m depositions may be carried out by thermal and/or plasma-enhanced CVD, ALD, and pulse CVD.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: October 1, 2013
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Julien Gatineau, Changhee Ko
  • Patent number: 8541276
    Abstract: A dielectric containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric produce a reliable dielectric for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium aluminum oxide film.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8541283
    Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 24, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Mitsuhiro Horikawa, Kenichi Koyanagi, Hiroyuki Ode, Xiangxin Rui
  • Publication number: 20130244447
    Abstract: Methods for the aqueous oxidation of metallic films are described. For example, a film of hafnium metal on a silicon substrate can be oxidized to hafnium dioxide using hot deionized water. Methods for fabricating electrical components such as capacitors and field effect transistors using the oxidized metallic films are also described. For example, capacitors having a hafnium dioxide dielectric layer can be fabricated.
    Type: Application
    Filed: November 24, 2011
    Publication date: September 19, 2013
    Applicant: UNIVERSITY OF MANITOBA
    Inventors: Auxence Minko, Douglas A. Buchanan
  • Patent number: 8536656
    Abstract: A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ravikumar Ramachandran, Ramachandra Divakaruni, Ying Li
  • Patent number: 8535998
    Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fung Ka Hing, Haiting Wang, Han-Ting Tsai, Chun-Fai Cheng, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
  • Patent number: 8530322
    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: September 10, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Edward Haywood, Pragati Kumar, Sandra Malhotra, Xiangxin Rui
  • Patent number: 8524591
    Abstract: In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: September 3, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Rick Carter, Andreas Hellmich, Berthold Reimer
  • Patent number: 8524618
    Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8524617
    Abstract: A method for manufacturing a dielectric film having a high dielectric constant is provided. The method is a method for forming, on a substrate, a dielectric film including a metal oxide containing O and elements A and B, wherein the element A comprises Hf or a mixture of Hf and Zr and the element B comprises Al or Si, which includes the steps of: forming a metal oxide having an amorphous structure which has a molar ratio between element A and element B, B/(A+B) of 0.02?(B/(A+B))?0.095 and a molar ratio between element A and O, O/A of 1.0<(O/A)<2.0; and annealing the metal oxide having the amorphous structure at 700° C. or more to form a metal oxide containing a crystal phase with a cubic crystal content of 80% or more.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: September 3, 2013
    Assignee: Canon Anelva Corporation
    Inventors: Takashi Nakagawa, Naomu Kitano, Toru Tatsumi
  • Patent number: 8525274
    Abstract: A semiconductor device includes a substrate, a semiconductor, a first surface passivation film including nitride, a second passivation film, a gate electrode, and a source electrode and a drain electrode. The semiconductor layer is provided on the substrate. The first surface passivation film including nitride is provided on the semiconductor layer and has at least two openings. The second surface passivation film covers an upper surface and a side surface of the first surface passivation film. The gate electrode is provided on a part of the second surface passivation film. The source electrode and the drain electrode are respectively provided on the two openings. In addition, the second surface passivation film includes a material of which melting point is higher than the melting points of the gate electrode, the source electrode, and the drain electrode.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Patent number: 8524613
    Abstract: A method of forming a film of lanthanide oxide nanoparticles. In one embodiment, the method includes the steps of: (a) providing a first substrate with a conducting surface and a second substrate that is positioned apart from the first substrate, (b) applying a voltage between the first substrate and the second substrate, (c) immersing the first and the second substrates in a solution that comprises a plurality of lanthanide oxide nanoparticles suspended in a non-polar solvent or apolar solvent for a first duration of time effective to form a film of lanthanide oxide nanoparticles on the conducting surface of the first substrate, and (d) after the immersing step, removing the first substrate from the solution and exposing the first substrate to air while maintaining the applied voltage for a second duration of time to dry the film of lanthanide oxide nanoparticles formed on the conducting surface of the first substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 3, 2013
    Assignee: Vanderbilt University
    Inventors: James Dickerson, Sameer V. Mahajan
  • Publication number: 20130207171
    Abstract: A first semiconductor device comprises a metal-oxide film over a substrate. The metal-oxide film is formed by an atomic layer deposition method including a treatment in a reducing gas atmosphere after forming oxidized metal. A second semiconductor device comprises a lower electrode having a cup shape over a substrate, a metal-oxide film covering the lower electrode, and an upper electrode covering the metal-oxide film. The metal-oxide film is formed by an atomic layer deposition method including a treatment in a reducing gas atmosphere after forming oxidized metal.
    Type: Application
    Filed: January 3, 2013
    Publication date: August 15, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Elpida Memory, Inc.
  • Patent number: 8507389
    Abstract: Methods for forming a dielectric layer on a substrate are provided herein. In some embodiments a method for forming a dielectric layer on a substrate may include exposing the substrate to a first source gas comprising a silicon precursor and an oxidizer for a first period of time to form a first layer comprising silicon and oxygen; and exposing the substrate to a second source gas comprising a metal precursor and the silicon precursor for a second period of time to form a second layer comprising silicon and a metal, where in the first layer and the second layer form the dielectric layer.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 13, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Lucien Date, Paul William Turnbull
  • Patent number: 8501268
    Abstract: A method of forming a material over a substrate includes performing at least one iteration of the following temporally separated ALD-type sequence. First, an outermost surface of a substrate is contacted with a first precursor to chemisorb a first species onto the outermost surface from the first precursor. Second, the outermost surface is contacted with a second precursor to chemisorb a second species different from the first species onto the outermost surface from the second precursor. The first and second precursors include ligands and different central atoms. At least one of the first and second precursors includes at least two different composition ligands. The two different composition ligands are polyatomic or a lone halogen. Third, the chemisorbed first species and the chemisorbed second species are contacted with a reactant which reacts with the first species and with the second species to form a reaction product new outermost surface of the substrate.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Zhe Song, Chris M. Carlson
  • Patent number: 8501523
    Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jong-Won Lee, Kuo-Wei Chang, Michael L. McSwiney
  • Patent number: 8492852
    Abstract: A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Dechao Guo, Philip J. Oldiges, Yanfeng Wang
  • Patent number: 8492258
    Abstract: A manufacturing method of a semiconductor device of the present invention includes the step of forming an insulating film on a substrate, and the step of forming a high dielectric constant insulating film on the insulating film, and the step of forming a titanium aluminum nitride film on the high dielectric constant insulating film, wherein in the step of forming the titanium aluminum nitride film, formation of an aluminum nitride film and formation of a titanium nitride film are alternately repeated, and at that time, the aluminum nitride film is formed firstly and/or lastly.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 23, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Kazuhiro Harada