Silicon Oxide Formation Patents (Class 438/787)
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Publication number: 20090061608Abstract: A method of depositing a silicon dioxide layer for a semiconductor device. The method includes depositing the silicon dioxide layer to have a silicon concentration of greater than 30 atomic percent and a nitrogen concentration of less than 5 atomic percent. The depositing includes flowing nitric oxide gas with a silicon precursor over a substrate. In one example, the silicon precursor and nitric oxide are flowed over a substrate with the substrate being at a temperature in a range of approximately 600 to approximately 900 degrees Celsius. In one example, the silicon dioxide layer is formed on a layer including charge storage memory material.Type: ApplicationFiled: August 29, 2007Publication date: March 5, 2009Inventors: Tushar P. Merchant, Lakshmanna Vishnubhotla, Ramachandran Muralidhar, Rajesh A. Rao, Sriram Kalpat
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Patent number: 7491653Abstract: A metal- and metalloid-free nanolaminate dielectric film can be formed according to a pulsed layer deposition (PDL) process. A metal- and metalloid-free compound is used to catalyze the reaction of silica deposition by surface reaction of alkoxysilanols. Films can be grown at rates faster than 30 nm per exposure cycle. The invention can be used for the deposition of both doped (e.g., PSG) and undoped silicon oxide films. The films deposited are conformal, hence the method can accomplish void free gap-fill in high aspect ratio gaps encountered in advanced technology nodes (e.g., the 45 nm technology node and beyond), and can be used in other applications requiring conformal dielectric deposition.Type: GrantFiled: December 23, 2005Date of Patent: February 17, 2009Assignee: Novellus Systems, Inc.Inventors: George D. Papasouliotis, Seon-Mee Cho, Ron Rulkens, Mihai Buretea, Dennis M. Hausmann, Michael Barnes
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Patent number: 7491656Abstract: A silicon oxide film (1701) serving as a gate insulating film of a semiconductor device contains Kr. Therefore, the stress in the silicon oxide film (1701) and the stress at the interface between silicon and the silicon oxide film are relaxed, and the silicon oxide film has a high quality even though it was formed at a low temperature. The uniformity of thickness of the silicon oxide film (1701) on the silicon of the side wall of a groove (recess) in the element isolating region is 30% or less. Consequently, the silicon oxide film (1701) has its characteristics and reliability superior to those of a silicon thermal oxide film, and the element isolating region can be made small, thereby realizing a high-performance transistor integrated circuit preferably adaptable to an SOI transistor and a TFT.Type: GrantFiled: September 20, 2004Date of Patent: February 17, 2009Assignee: Foundation for Advancement of International ScienceInventor: Tadahiro Ohmi
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Publication number: 20090039417Abstract: A method of producing dielectric oxide nanodots (104) embedded in silicon dioxide as well as a nonvolatile flash memory device comprising a trapping layer (224), the trapping layer (224) comprising dielectric oxide nanodots (104) embedded in silicon dioxide are presented. Firstly an ultra-thin metal film is deposited over a first dielectric layer including silicon dioxide provided on a substrate. Then, the ultra-thin metal film is annealed for forming metallic nanodots (104) on the first dielectric layer. Afterwards, the metallic nanodots (104) are annealed for forming dielectric oxide nanodots (104) on the first dielectric layer. Finally, the first dielectric layer and the dielectric oxide nanodots (104) are covered with a second dielectric layer of silicon dioxide for forming dielectric oxide nanodots (104) embedded in silicon dioxide.Type: ApplicationFiled: February 17, 2005Publication date: February 12, 2009Applicant: NATIONAL UNIVERSITY OF SINGAPOREInventors: Jinghao Chen, Won Jong Yoo, Siu Hung Daniel Chan
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Publication number: 20090042407Abstract: A gas distributor for use in a semiconductor process chamber comprises a body. The body includes a first channel formed within the body and adapted to pass a first fluid from a first fluid supply line through the first channel to a first opening. A second channel is formed within the body and adapted to pass a second fluid from a second fluid supply line through the second channel to a second opening. The first and second openings are arranged to mix the fluids outside the body after the fluids pass through the openings.Type: ApplicationFiled: October 17, 2008Publication date: February 12, 2009Applicant: Applied Materials, Inc.Inventors: Won B. Bang, Srivivas D. Nemani, Phong Pham, Ellie Y. Yieh
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Patent number: 7488693Abstract: [Problems] It is to provide a method for producing a silicon oxide film having better quality than a TEOS at low temperature. And it is to provide a method for manufacturing a semiconductor device wherein an insulating film composed of a silicon oxide is formed. [Means for solving problems] A film composed of a silicon oxide is produced by CVD method where a silane compound represented by the following general formula is reacted. An insulating film is deposited by CVD method where a silane compound represented by the following general formula is reacted. HnSi2(OR)6?n (In the above formula, R is an alkyl group of carbon number from 1 to 5, and n is an integer from 0 to 2.Type: GrantFiled: February 17, 2005Date of Patent: February 10, 2009Assignee: Toagosei Co., Ltd.Inventors: Hiroaki Takeuchi, Satoshi Hattori, Hiroshi Suzuki, Katsuyoshi Harada
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Publication number: 20090035951Abstract: Provided is a manufacturing method of a semiconductor device composed of a step of carrying-in a wafer into a processing chamber; a step of forming an HfO2 film on the wafer by alternately supplying TEMAH and O3, under heating, into the processing chamber; and a step of carrying-out the wafer from the inside of the processing chamber, wherein in the step of forming the HfO2 film, heating temperature of TEMAH and heating temperature of O3 are set to be different.Type: ApplicationFiled: July 11, 2008Publication date: February 5, 2009Inventors: Hironobu Miya, Masanori Sakai, Norikazu Mizuno, Tsutomu Kato, Yuji Takebayashi
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Patent number: 7482244Abstract: A wafer including a high stressed thin film thereon is lifted, and a pre-heating process is performed while the wafer is lifted. Subsequently, a dielectric layer is deposited on the high stressed thin film.Type: GrantFiled: September 16, 2005Date of Patent: January 27, 2009Assignee: United Microelectronics Corp.Inventors: Chih-Jen Mao, Hui-Shen Shih, Kuo-Wei Yang, Chun-Han Chuang, Chun-Hung Hsia
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Patent number: 7482284Abstract: A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.Type: GrantFiled: February 28, 2007Date of Patent: January 27, 2009Assignee: Micron Technology, Inc.Inventors: Brian A. Vaartstra, Timothy A. Quick
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Publication number: 20090004883Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.Type: ApplicationFiled: September 16, 2005Publication date: January 1, 2009Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
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Patent number: 7470635Abstract: This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming bit line over capacitor arrays of memory cells. In one implementation, a semiconductor substrate having an exposed outer first surface comprising silicon-nitrogen bonds and an exposed outer second surface comprising at least one of silicon and silicon dioxide is provided. A layer comprising a metal is deposited over at least the outer second surface. A silanol is flowed to the metal of the outer second surface and to the outer first surface effective to selectively deposit a silicon dioxide comprising layer over the outer second surface as compared to the outer first surface. Other aspects and implementations are contemplated.Type: GrantFiled: March 17, 2006Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventors: Weimin Li, Gurtej S. Sandhu
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Publication number: 20080311754Abstract: A method of improving pattern loading in a deposition of a silicon oxide film is described. The method may include providing a deposition substrate to a deposition chamber, and adjusting a temperature of the deposition substrate to about 250° C. to about 325° C. An ozone containing gas may be introduced to the deposition chamber at a first flow rate of about 1.5 slm to about 3 slm, where the ozone concentration in the gas is about 6% to about 12%, by wt. TEOS may also be introduced to the deposition chamber at a second flow rate of about 2500 mgm to about 4500 mgm. The deposition rate of the silicon oxide film is controlled by a reaction rate of a reaction of the ozone and TEOS at a deposition surface of the substrate.Type: ApplicationFiled: June 11, 2008Publication date: December 18, 2008Applicant: Applied Materials, Inc.Inventors: BALAJI CHANDRASEKARAN, Douglas E. Manning, Nitin K. Ingle, Rong Pan, Zheng Yuan, Sidharth Bhatia
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Patent number: 7465680Abstract: A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.Type: GrantFiled: September 7, 2005Date of Patent: December 16, 2008Assignee: Applied Materials, Inc.Inventors: Xiaolin Chen, Srinivas D. Nemani, DongQing Li, Jeffrey C. Munro, Marlon E. Menezes
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Patent number: 7465679Abstract: A silicon oxide film is formed to cover an island non-monocrystalline silicon region by plasma CVD using an organic silane having ethoxy groups (e.g., TEOS) and oxygen as raw materials, while hydrogen chloride or a chlorine-containing hydrocarbon (e.g., trichloroethylene) of a fluorine-containing gas is added to the plasma CVD atmosphere, preferably in an amount of from 0.01 to 1 mol % of the atmosphere so as to reduce the alkali elements from the silicon oxide film formed and to improve the reliability of the film. Prior to forming the silicon oxide film, the silicon region may be treated in a plasma atmosphere containing oxygen and hydrogen chloride or a chlorine-containing hydrocarbon. The silicon oxide film is obtained at low temperatures and this has high reliability usable as a gate-insulating film in a semiconductor device.Type: GrantFiled: December 20, 1999Date of Patent: December 16, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takeshi Fukada, Mitsunori Sakama, Yukiko Uehara, Hiroshi Uehara
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Patent number: 7465682Abstract: A method for processing an organosiloxane film includes loading a target substrate (W) with a coating film formed thereon into a reaction chamber (2), and performing a heat process on the target substrate (W) within the reaction chamber (2) to bake the coating film. The coating film contains a polysiloxane base solution having an organic functional group. The heat process includes a temperature setting step of setting an interior of the reaction chamber (2) at a process temperature by heating, and a supplying step of supplying a baking gas into the reaction chamber (2) set at the process temperature, while activating the baking gas by a gas activation section (14) disposed outside the reaction chamber (2).Type: GrantFiled: April 20, 2004Date of Patent: December 16, 2008Assignee: Tokyo Electron LimitedInventor: Shingo Hishiya
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Patent number: 7462568Abstract: Disclosed herein is a method for forming an interlayer dielectric film in a semiconductor device. The method comprises the steps of preparing a semiconductor substrate having a dielectric film and conductive film patterns sequentially deposited thereon, and depositing a high plasma oxide film as the interlayer dielectric film on the conductive film patterns and the dielectric films by supplying H2 as an adding gas together with a source gas. A dangling bond in an interface of the semiconductor substrate is reduced by adding hydrogen into the dielectric film, thereby enhancing the uniformity of the deposition. Moreover, hydrogen in the dielectric film decreases current leakage occurring in the gate by preventing electrons in the plasma from flowing into a gate through the bit-line, thereby enhancing the refresh characteristics of the semiconductor device.Type: GrantFiled: May 27, 2005Date of Patent: December 9, 2008Assignee: Hynix Semiconductor Inc.Inventor: Jie Won Chung
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Patent number: 7462519Abstract: A pair of substrates forming the active matrix liquid crystal display are fabricated from resinous substrates having transparency and flexibility. A thin-film transistor has a semiconductor film formed on a resinous layer formed on one resinous substrate. The resinous layer is formed to prevent generation of oligomers on the surface of the resinous substrate during formation of the film and to planarize the surface of the resinous substrate.Type: GrantFiled: August 26, 2004Date of Patent: December 9, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuyuki Arai, Satoshi Teramoto
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Patent number: 7459405Abstract: Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an initial deposition stage, a relatively low ratio of silicon-containing gas:oxidant deposition gas is flowed, resulting in formation of highly conformal silicon oxide at relatively slow rates. Over the course of the deposition process step, the ratio of silicon-containing gas:oxidant gas is increased, resulting in formation of less-conformal oxide material at relatively rapid rates during later stages of the deposition process step.Type: GrantFiled: July 25, 2006Date of Patent: December 2, 2008Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Xinyua Xia, Zheng Yuan
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Publication number: 20080293255Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking Dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.Type: ApplicationFiled: May 21, 2008Publication date: November 27, 2008Inventor: Krishnaswamy Ramkumar
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Patent number: 7456116Abstract: A method to form a silicon oxide layer, where the method includes the step of providing a continuous flow of a silicon-containing precursor to a chamber housing a substrate, where the silicon-containing precursor is selected from TMOS, TEOS, OMTS, OMCTS, and TOMCATS. The method may also include the steps of providing a flow of an oxidizing precursor to the chamber, and causing a reaction between the silicon-containing precursor and the oxidizing precursor to form a silicon oxide layer. The method may further include varying over time a ratio of the silicon-containing precursor:oxidizing precursor flowed into the chamber to alter a rate of deposition of the silicon oxide on the substrate.Type: GrantFiled: December 20, 2004Date of Patent: November 25, 2008Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Shan Wong, Xinyun Xia, Vikash Banthia, Won B. Bang, Yen-Kun V. Wang, Zheng Yuan
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Publication number: 20080283972Abstract: The present invention relates to a process for producing an SiO2-containing insulating layer on chips and the use of specific precursors for this purpose. The invention further relates to an insulating layer obtainable in this way and also to chips which have been provided with such an insulating layer.Type: ApplicationFiled: December 22, 2004Publication date: November 20, 2008Applicant: DEGUSSA AGInventors: Ekkehard Muh, Hartwig Rauleder, Harald Klein, Jaroslaw Monkiewicz, Iordanis Savvopoulos
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Publication number: 20080283975Abstract: In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.Type: ApplicationFiled: May 18, 2007Publication date: November 20, 2008Inventors: Laura M. Matz, Ting Y. Tsui, Thad E. Briggs, Robert Kraft
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Patent number: 7452830Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. An example method includes loading a first substrate to be provided with an oxynitride layer along with a second substrate having a nitride layer in a boat, and forming the oxynitride layer on the first substrate by placing the boat into a furnace and thermally treating the boat under an oxygen atmosphere.Type: GrantFiled: July 27, 2005Date of Patent: November 18, 2008Assignee: Dongbu Electronics Co., Ltd.Inventors: Chul-Ho Shin, Tae-Hong Kim
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Publication number: 20080274627Abstract: Using a cyclic siloxane compound having a vinyl group directly attached to a silicon atom and a relatively bulky substituent group containing a primary carbon vicinal to the silicon, a dielectric film, especially a low-k interlayer dielectric film can be formed by the plasma-enhanced CVD process.Type: ApplicationFiled: May 1, 2008Publication date: November 6, 2008Applicants: SHIN-ETSU CHEMICAL CO., LTD., NEC CORPORATIONInventors: Yoshitaka HAMADA, Jun KAWAHARA
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Publication number: 20080274626Abstract: In certain embodiments methods for depositing materials on substrates, and more particularly, methods for depositing dielectric layers, such as silicon oxides or silicon oxynitrides, on germanium substrates are provided. The methods involve depositing a barrier layer on the germanium substrate to prevent oxidation of the germanium substrate when forming a dielectric layer on the germanium substrate. In certain embodiments, a silicon layer is deposited on the germanium substrate to form a barrier layer. In certain embodiments, nitridation of the germanium substrate forms a GexNy layer which functions as a barrier layer. In certain embodiments, a silicon nitride layer is deposited on the germanium substrate to form a barrier layer.Type: ApplicationFiled: May 4, 2007Publication date: November 6, 2008Inventors: Frederique Glowacki, Laurent Vandroux, Rajesh Mani
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Patent number: 7446055Abstract: This invention relates to an improvement in a deposition process for producing low dielectric films having a dielectric constant of 3, preferably <2.7 and lower. The process comprises the steps: (a) forming a liquid precursor solution comprised of an organosilicon source containing both Si—O and Si—C bonds and solvent; (b) generating a liquid mist of said liquid precursor solution, said mist existing as precursor solution droplets having a number average droplet diameter size of less than 0.5 ?m; (c) preferably electrically charging the liquid mist of said liquid precursor solution droplets; (d) depositing liquid mist of said liquid precursor solution droplets onto a substrate; and, (e) converting the thus deposited liquid mist of said liquid precursor solution droplets to a solid, low dielectric film.Type: GrantFiled: March 17, 2005Date of Patent: November 4, 2008Assignee: Air Products and Chemicals, Inc.Inventors: Scott Jeffrey Weigel, Jean Louise Vincent, Sarah Kathryn Coulter, James Edward MacDougall
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Patent number: 7435690Abstract: Method of preparing a silicon dioxide layer by high-temperature oxidation on a substrate of formula Si1-xGex in which x is greater than 0 and less than or equal to 1, the said method comprising the following successive steps: a) at least one additional layer of thickness hy and of overall formula Si1-yGey, in which y is greater than 0 and less than x, is deposited on the said substrate of formula Si1-xGex; and b) the high-temperature oxidation of the said additional layer of overall formula Si1-yGey is carried out, whereby the said additional layer is completely or partly converted into a layer of silicon oxide SiO2. Method of preparing an optical or electronic component, comprising at least one step for preparing an SiO2 layer using the method described above.Type: GrantFiled: March 25, 2005Date of Patent: October 14, 2008Assignee: Commissariat a l'Energie AtomiqueInventors: Hubert Moriceau, Pierre Mur
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Patent number: 7435683Abstract: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: September 15, 2006Date of Patent: October 14, 2008Assignee: Intel CorporationInventors: Jack T. Kavalieros, Uday Shah, Willy Rachmady, Brian S. Doyle
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Publication number: 20080248644Abstract: In the fabrication of a semiconductor device, an SiO2GeO2 film is formed on a substrate, then washed with water to dissolve the GeO2, leaving a porous SiO2 film. The SiO2GeO2 film may be deposited directly on the substrate, or an SiGe film may be deposited on the substrate and then oxidized to form the SiO2GeO2 film. The porous SiO2 film has an easily controllable dielectric constant and can be advantageously used as an interlayer dielectric film.Type: ApplicationFiled: March 12, 2008Publication date: October 9, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Guo lin Liu
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Patent number: 7429541Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.Type: GrantFiled: August 31, 2005Date of Patent: September 30, 2008Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Chris W. Hill
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Patent number: 7425505Abstract: The present invention provides improvements to the use of silyating agents in semiconductor processing. More particularly, the silyating agents may be provided in combination with a substantially non-flammable ether, so that the combination is substantially non-flammable. Additionally, the silyating agent may be utilized in vapor form, or applied in conjunction with the electromagnetic radiation. Each of these embodiments can enhance the usability of the silyating agent, i.e., by rendering the silyating agent more safe, more easily utilized in a variety of processing equipment and/or by enhancing the passivation efficacy/efficiency of the silyating agent.Type: GrantFiled: July 19, 2004Date of Patent: September 16, 2008Assignee: FSI International, Inc.Inventors: Philip G. Clark, Kurt Karl Christenson, Brent D. Schwab
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Patent number: 7422975Abstract: A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on the first and second spacer layers, respectively, such that each of the first and second dielectric layers is separated by one of the spacer layers. The first and second dielectric layers each include a first and second dielectric component. The second dielectric component is a sacrificial dielectric material. At least a portion of the second dielectric component is removed to thereby form voids in the first and second dielectric layers. At least a portion of the sacrificial dielectric material in the first and second spacer layers is also removed to thereby form voids in the first and/or second spacer layers.Type: GrantFiled: August 18, 2005Date of Patent: September 9, 2008Assignees: Sony Corporation, Sony Electronics Inc.Inventors: Takeshi Nogami, Kensaku Ida
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Publication number: 20080214019Abstract: A method of manufacturing an oxide film includes jetting onto a substrate a high-pressure solution containing an oxygen source and having a pressure of 5 MPa, and forming an oxide film on the substrate using the jetted high-pressure solution.Type: ApplicationFiled: February 29, 2008Publication date: September 4, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi KATSUMATA, Makoto Saito, Hiroshi Fujita, Eriko Nishimura
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Patent number: 7419903Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.Type: GrantFiled: April 13, 2005Date of Patent: September 2, 2008Assignee: ASM International N.V.Inventors: Suvi P. Haukka, Ivo Raaijmakers, Wei Min Li, Juhana Kostamo, Hessel Sprey
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Patent number: 7420202Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.Type: GrantFiled: November 8, 2005Date of Patent: September 2, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
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Patent number: 7416955Abstract: A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film.Type: GrantFiled: May 25, 2006Date of Patent: August 26, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi
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Publication number: 20080191322Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.Type: ApplicationFiled: April 22, 2008Publication date: August 14, 2008Applicant: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Jerome B. Lasky, Christopher D. Muzzy, Wolfgang Sauter
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Patent number: 7410869Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.Type: GrantFiled: July 5, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hun-Hyeoung Leam, Hyeon-Deok Lee, Young-Sub You, Won-Jun Jang, Woong Lee, Jung-Hyun Park, Sang-Kyoung Lee, Jung-Geun Jee, Sang-Hoon Lee
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Patent number: 7410913Abstract: Provided are methods for manufacturing silicon rich oxide (SRO) layers useful in the fabrication of semiconductor devices, for example, non-volatile memory devices, and methods for fabricating semiconductor devices incorporating such SRO layers. The methods include absorbing a first silicon source gas onto the substrate, oxidizing the first absorbed layer to form a silicon oxide layer, absorbing a second silicon source gas onto the substrate and reducing the second absorbed layer to form a silicon layer. The combination of the silicon oxide layer(s) and the silicon layer(s) comprise, in turn, a composite SRO layer. These manufacturing methods facilitate control of the oxygen concentration in the SRO, the relative thicknesses of the silicon oxide and silicon layers, and provides improved step coverage, thus allowing the manufacturing of high quality semiconductor devices.Type: GrantFiled: September 12, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hyun Lee, Sang-Bong Bang
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Patent number: 7407896Abstract: A fabrication method and materials produce high quality aperiodic photonic structures. Light emission can be activated by thermal annealing post growth treatments when thin film layers of SiO2 and SiNx or Si-rich oxide are used. From these aperiodic structures, that can be obtained in different vertical and planar device geometries, the presence of aperiodic order in a photonic device provides strong group velocity reduction (slow photons), enhanced light-matter interaction, light emission enhancement, gain enhancement, and/or nonlinear optical properties enhancement.Type: GrantFiled: April 25, 2005Date of Patent: August 5, 2008Assignee: Massachusetts Institute of TechnologyInventors: Luca Dal Negro, Jae Hyung Yi, Jurgen Michel, Yasha Yi, Victor T. Nguyen, Lionel C. Kimerling
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Publication number: 20080182428Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.Type: ApplicationFiled: January 26, 2007Publication date: July 31, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Tushar P. Merchant, Chun-Li Liu, Ramachandran Muralidhar, Marius K. Orlowski, Rajesh A. Rao, Matthew Stoker
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Publication number: 20080182429Abstract: A semiconductor manufacturing system, having a filter that is disposed in a clean room and removes an organic solvent containing siloxane from a gas supplied from the outside of said clean room; a first semiconductor manufacturing apparatus that is disposed in said clean room and uses light in an atmosphere containing the gas having passed through said filter; a second semiconductor manufacturing apparatus that is disposed in said clean room and has an exhaust gas outlet for discharging a gas containing an organic solvent containing siloxane; and a removing device that is disposed at said exhaust gas outlet of said second semiconductor manufacturing apparatus, filters out the organic solvent containing siloxane from the exhaust gas output from said exhaust gas outlet, and discharges the filtered gas into an exhaust gas duct for discharging the exhaust gas to the outside of said clean room.Type: ApplicationFiled: January 22, 2008Publication date: July 31, 2008Inventors: Ayako MIZUNO, Hiroshi Tomita
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Patent number: 7399697Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting a mixture comprising an oxidizable silicon component and an oxidizable component having thermally labile groups with an oxidizing gas in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.Type: GrantFiled: December 2, 2004Date of Patent: July 15, 2008Assignee: Applied Materials, Inc.Inventor: Robert P. Mandal
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Publication number: 20080166888Abstract: A method for filling silicon nitride materials into a trench includes providing a substrate having a plurality of trenches, performing a first deposition process to form a first silicon nitride layer in the trenches, and performing a second deposition process to form a second silicon nitride layer in the trenches. The reactant gas of the first deposition process has a first O3/TEOS flow ratio larger than a second O3/TEOS flow ratio of the reactant gas of the second deposition process.Type: ApplicationFiled: January 10, 2007Publication date: July 10, 2008Inventors: Shao-Ta Hsu, Neng-Kuo Chen, Teng-Chun Tsai
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Patent number: 7396775Abstract: The present invention discloses improved method for manufacturing semiconductor device wherein the gate oxide films in the cell region, VPP peripheral circuit region and VDD peripheral circuit region are formed to have different thicknesses from one another so that the threshold voltage of the cell transistor may be increased to a desired value as well as increasing the operation speed of the transistor and suppress the short channel effect.Type: GrantFiled: May 31, 2005Date of Patent: July 8, 2008Assignee: Hynix Semiconductor Inc. Inc.Inventor: Sang Don Lee
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Publication number: 20080160785Abstract: A method of forming an oxide layer in a semiconductor device comprising the step of loading a semiconductor substrate in a chamber, optionally increasing a temperature of an interior of the chamber, performing the first oxidation process in the chamber under the atmosphere of ozone to form an oxide layer on the semiconductor substrate, and lowering a temperature of an interior of the chamber.Type: ApplicationFiled: June 7, 2007Publication date: July 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Wan Sup SHIN, Kwang Chul JOO, Kwang Seok JEON
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Patent number: 7387973Abstract: A method for treating an inter-metal dielectric (IMD) layer to improve a mechanical strength and/or repair plasma etching damage including providing a low-K silicon oxide containing dielectric insulating layer; and carrying out a super critical fluid treatment of the low-K dielectric insulating layer including supercritical CO2 and a solvent including a silicon bond forming substituent having a bonding energy greater than a Si—H to replace at least a portion of the Si—H bonds with the silicon bond forming substituent.Type: GrantFiled: September 30, 2004Date of Patent: June 17, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Ya Wang, Joshua Tseng, Henry Lo
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Publication number: 20080132086Abstract: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.Type: ApplicationFiled: February 11, 2008Publication date: June 5, 2008Inventors: Zhong Dong, Chiliang Chen, Ching-Hwa Chen
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Publication number: 20080128764Abstract: A semiconductor substrate including a plurality of insulating elements formed of an insulating material in the substrate, a semiconductor device having the same, and methods of manufacturing the substrate and the device are provided. The semiconductor device includes isolation regions formed in a semiconductor substrate, transistors formed on the semiconductor substrate, source/drain regions formed between the transistors and the isolation regions in the semiconductor substrate, and a plurality of the elements formed of insulating material being formed within the semiconductor substrate a predetermined distance beneath a top surface of the substrate.Type: ApplicationFiled: November 29, 2007Publication date: June 5, 2008Applicant: Samsung Electronics Co., Ltd.Inventor: Won-chang Lee
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Patent number: RE40507Abstract: A method of forming a pre-metal dielectric film having good as deposited gapfill characteristics, as well as good mobile-ion gettering capability. The method involves first depositing a layer of high-ozone undoped silicon dioxide film having a high ozone/TEOS volume ratio. Then, a low-ozone doped BPSG film is deposited over the high-ozone undoped silicon dioxide layer. The film layers are heat treated to densify the film, and then the top layer is planarized using known planarization techniques to a thickness that allows for adequate mobile-ion gettering.Type: GrantFiled: June 25, 2003Date of Patent: September 16, 2008Assignee: Atmel CorporationInventors: Amit S. Kelkar, Michael D. Whiteman