Silicon Oxide Formation Patents (Class 438/787)
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Publication number: 20120164847Abstract: A control unit heats a reaction pipe to a load temperature by controlling a temperature-raising heater 16, and then makes semiconductor wafers received in the reaction pipe. Next, the control unit heats the reaction pipe in which the semiconductor wafers are received to a film formation temperature by controlling the temperature-raising heater, and then forms thin films on the semiconductor wafers by supplying a film forming gas into the reaction pipe from a process gas introducing pipe. Also, the control unit sets the load temperature to a temperature higher than the film formation temperature.Type: ApplicationFiled: December 27, 2011Publication date: June 28, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Toshiyuki IKEUCHI, Pao-Hwa CHOU, Kazuya YAMAMOTO, Kentarou SERA
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Patent number: 8206788Abstract: In the manufacture of electronic devices that use porous dielectric materials, the properties of the dielectric in a pristine state can be altered by various processing steps. In a method for restoring and preserving the pristine properties of a porous dielectric layer, a substrate is provided with a layer of processed porous dielectric on top, whereby the processed porous dielectric is at least partially exposed. A thin aqueous film is formed at least on the exposed parts of the processed porous dielectric. The exposed porous dielectric with the aqueous film is exposed to an ambient containing a mixture comprising at least one silylation agent and dense CO2, resulting in the restoration and preservation of the pristine properties of the porous dielectric.Type: GrantFiled: July 3, 2007Date of Patent: June 26, 2012Assignee: IMECInventors: Fabrice Sinapi, Jan Alfons B. Van Hoeymissen
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Publication number: 20120156894Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.Type: ApplicationFiled: February 9, 2012Publication date: June 21, 2012Applicant: Advanced Technology Materials, Inc.Inventors: Ziyun Wang, Chongying Xu, Thomas H. Baum
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Patent number: 8202785Abstract: A method of bonding a first substrate to a second substrate by molecular bonding by forming an insulating layer on the bonding face of the first substrate, chemical-mechanical polishing of the insulating layer, activating a bonding surface of the second substrate by plasma treatment, etching an exposed surface of the insulating layer, and bonding together the two substrates together by molecular bonding wherein the etching is conducted after the chemical-mechanical polishing and before the bonding.Type: GrantFiled: October 27, 2009Date of Patent: June 19, 2012Assignee: SoitecInventors: Arnaud Castex, Gweltaz Gaudin, Marcel Broekaart
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Patent number: 8158487Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.Type: GrantFiled: January 21, 2011Date of Patent: April 17, 2012Assignee: SoitecInventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
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Patent number: 8153534Abstract: An oxidation method for performing direct oxidation includes respectively supplying an oxidizing gas and a deoxidizing gas to the process field, and directly oxidizing a surface target substrates by use of oxygen radicals and hydroxyl group radicals generated by a reaction between the oxidizing gas and the deoxidizing gas. The oxidizing gas is supplied through an oxidizing gas nozzle extending over a vertical length corresponding to the process field and is spouted from a plurality of gas spouting holes formed on the oxidizing gas nozzle and arrayed over the vertical length corresponding to the process field. The deoxidizing gas is supplied through a plurality of deoxidizing gas nozzles having different heights respectively corresponding to a plurality of zones of the process field arrayed vertically and is spouted from gas spouting holes respectively formed on the deoxidizing gas nozzles each at height of a corresponding zone.Type: GrantFiled: February 11, 2011Date of Patent: April 10, 2012Assignee: Tokyo Electron LimitedInventors: Hisashi Inoue, Masataka Toiya, Yoshikatsu Mizuno
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Patent number: 8153481Abstract: A semiconductor power device comprises a semiconductor substrate. The substrate includes an N-type silicon region and N+ silicon region. An oxide layer overlies the N? type silicon region, the oxide layer formed using a Plasma Enhanced Chemical Vapor deposition (PECVD) method. First and second electrodes are coupled to the N? type silicon region and the N+ type silicon region, respectively. The oxide layer has a thickness 0.5 to 3 microns. The power device also includes a polymide layer having a thickness of 3 to 20 microns; a first field plate overlying the oxide layer; and second field plate overlying the polymide layer and the first field plate, wherein the second field plate overlaps the first field plate by 2 to 15 microns.Type: GrantFiled: April 27, 2006Date of Patent: April 10, 2012Assignee: IXYS CorporationInventor: Subhas Chandra Bose Jayappa Veeramma
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Patent number: 8143175Abstract: The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing disconnection or deflection of the wiring. The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein during a step for etching a material 12 to be etched using a mask pattern composed of a photoresist 15 and inorganic films 14 and 13 made of SiN, SiON, SiO and the like formed on the material 12 to be etched, a mixed gas formed of a halogen-based gas such as chlorine-containing gas or bromine-containing gas and at least one fluorine-containing gas selected from a group of fluorine-containing gases composed of CF4, CHF3, SF6 and NF3 is used to reduce the mask pattern and the processing dimension of the material to be etched substantially equally during processing of the material 12 to be etched.Type: GrantFiled: May 5, 2009Date of Patent: March 27, 2012Assignee: Hitachi High-Technologies CorporationInventors: Satoshi Une, Masamichi Sakaguchi, Kenichi Kuwabara, Tomoyoshi Ichimaru
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Publication number: 20120064733Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a silicon oxide film on a surface of a substrate holder by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer; forming a thin film on a substrate by using a process gas; removing deposits attached onto the substrate holder by using a fluorine-containing gas; and reforming a silicon oxide film on the surface of the substrate holder after removal of the deposits by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer by using an oxygen-containing gas and a hydrogen-containing gas.Type: ApplicationFiled: September 7, 2011Publication date: March 15, 2012Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Ryota SASAJIMA, Yoshiro HIROSE, Naonori AKAE, Osamu KASAHARA
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Patent number: 8133822Abstract: A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.Type: GrantFiled: August 22, 2008Date of Patent: March 13, 2012Assignee: Sharp Laboratories of America, Inc.Inventors: Jiandong Huang, Pooran Chandra Joshi, Hao Zhang, Apostolos T. Voutsas
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Patent number: 8129289Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.Type: GrantFiled: October 5, 2006Date of Patent: March 6, 2012Assignee: Micron Technology, Inc.Inventors: John A. Smythe, Gurtej S. Sandhu, Brian J. Coppa, Shyam Surthi, Shuang Meng
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Patent number: 8129242Abstract: A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.Type: GrantFiled: May 12, 2006Date of Patent: March 6, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Tian-Shuan Luo, Chun-Pei Wu
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Publication number: 20120052694Abstract: Techniques to improve characteristics of processed semiconductor substrates are described, including cleaning a substrate using a preclean process, the substrate comprising a dielectric region and a conductive region, introducing a hydroquinone to the substrate after cleaning the substrate using the preclean operation, and forming a capping layer over the conductive region of the substrate after introducing the hydroquinone.Type: ApplicationFiled: November 4, 2011Publication date: March 1, 2012Applicant: Intermolecular, Inc.Inventors: Anh Ngoc Duong, Chi-I Lang
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Publication number: 20120045905Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying at least two types of source gases into the process vessel, each of the at least two types of source gases containing the element, and (b) changing the layer containing the element by supplying reaction gas into the process vessel, the reaction gas being different from the at least two types of source gases; and unloading the processed substrate from the process vessel.Type: ApplicationFiled: November 1, 2011Publication date: February 23, 2012Inventors: Naonori AKAE, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
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Patent number: 8119539Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.Type: GrantFiled: July 14, 2009Date of Patent: February 21, 2012Assignee: Cree, Inc.Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
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Patent number: 8119543Abstract: Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate.Type: GrantFiled: December 10, 2010Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventor: Shyam Surthi
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Patent number: 8119538Abstract: A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.Type: GrantFiled: August 9, 2007Date of Patent: February 21, 2012Assignee: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Patent number: 8105956Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: GrantFiled: October 20, 2009Date of Patent: January 31, 2012Assignee: Micron Technology, Inc.Inventors: Yunjun Ho, Brent Gilgen
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Patent number: 8093142Abstract: There is provided a plasma processing device capable of forming a film in a favorable manner irrespective of deflection generated in an anode electrode and a cathode electrode in the case where an area of the electrodes is increased. A plasma processing device 100 includes a chamber 15, a gas introducing portion 28, an exhaust unit 29, and a high-frequency power supply unit 30. In the chamber 15, there are provided an anode electrode (first electrode) 4 having a flat-plate shape, a cathode electrode (second electrode) 12 having a flat-plate shape, and first supporting members 6 and second supporting members 5 for slidably supporting the two electrodes 4 and 12 in parallel with each other. The cathode electrode 12 is provided so as to face the anode electrode 4. The anode electrode 4 and the cathode electrode 12 are not fixed with screws or the like but are merely placed on the first supporting members 6 and the second supporting members 5.Type: GrantFiled: November 16, 2006Date of Patent: January 10, 2012Assignee: Sharp Kabushiki KaishaInventors: Yusuke Fukuoka, Katsushi Kishimoto
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Patent number: 8084373Abstract: A manufacturing method of a semiconductor device is provided which can uniformly form a good and thin silicon oxide film or the like at a relatively low temperature. In step 1, a semiconductor substrate is exposed to monosilane (SiH4). Then, in step 2, the remaining monosilane (SiH4) is emitted. In step 3, the semiconductor substrate is exposed to nitrous oxide plasma. A desired silicon oxide film is formed by repeating one cycle including steps 1 to 3 until a necessary thickness of the film is obtained.Type: GrantFiled: June 30, 2010Date of Patent: December 27, 2011Assignee: Renesas Electronics CorporationInventors: Tatsunori Murata, Yoshihiro Miyagawa
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Publication number: 20110312192Abstract: A film formation method of forming a silicon oxide film on a surface of an object to be processed in a process chamber includes absorbing a seed gas comprising a silane-based gas on the surface of the object to be processed by supplying the seed gas into the process chamber, forming a silicon film having an impurity by supplying a silicon-containing gas as a material gas, and an addition gas including the impurity into the process chamber, and oxidizing the silicon film to convert the silicon film into the silicon oxide film. Accordingly, the silicon oxide film having the high density and the high stress is formed on the surface of the object to be processed.Type: ApplicationFiled: June 20, 2011Publication date: December 22, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Hiroki MURAKAMI, Kazuhide HASEBE, Kazuya YAMAMOTO, Toshihiko TAKAHASHI, Daisuke SUZUKI
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Patent number: 8076251Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an oxide, nitride, or oxynitride film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying and exhausting first and second source gases containing the element into and from the process vessel; and (b) changing the layer containing the element into an oxide, nitride, or oxynitride layer by supplying and exhausting reaction gas different from the first and second source gases into and from the process vessel; and unloading the substrate from the process vessel. The first source gas is more reactive than the second source gas, and an amount of the first source gas supplied into the process vessel is set to be less than that of the second source gas supplied into the process vessel.Type: GrantFiled: September 29, 2010Date of Patent: December 13, 2011Assignee: Hitachi Kokusai Electric, Inc.Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
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Publication number: 20110298099Abstract: A silicon dioxide layer is deposited onto a substrate using a process gas comprising BDEAS and an oxygen-containing gas such as ozone. The silicon dioxide layer can be part of an etch-resistant stack that includes a resist layer. In another version, the silicon dioxide layer is deposited into through holes to form an oxide liner for through-silicon vias.Type: ApplicationFiled: June 4, 2010Publication date: December 8, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Yong-Won LEE, Vladimir Zubkov, Mei-Yee SHEK, Li-Qun XIA, Prahallad IYENGAR, Sanjeev BALUJA, Scott A. HENDRICKSON, Juan Carlos ROCHA-ALVAREZ, Thomas NOWAK, Derek R. WITTY
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Patent number: 8062983Abstract: Porous dielectric layers are produced by embedding and removing nanoparticles in composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.Type: GrantFiled: February 11, 2009Date of Patent: November 22, 2011Assignee: Novellus Systems, Inc.Inventors: Nerissa S. Draeger, Gary William Ray
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Publication number: 20110281417Abstract: This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform thickness and excellent step coverage in holes with aspect ratios over 40:1. The films are transparent and good electrical insulators. This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices, particularly through materials and processes for producing semi-porous dielectric materials wherein surface porosity is significantly reduced or removed while internal porosity is preserved to maintain a desired low-k value for the overall dielectric material.Type: ApplicationFiled: July 22, 2011Publication date: November 17, 2011Inventors: Roy G. GORDON, Jill Becker, Dennis Hausmann
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Publication number: 20110281443Abstract: The film formation method includes transferring an object to be processed into a process chamber; controlling a temperature of the object to be processed to be equal to or lower than 350° C.; and supplying an aminosilane gas as a Si source gas and an oxidizing gas into the process chamber, wherein the oxidizing gas consists of a first oxidizing gas comprising at least one selected from the group consisting of an O2 gas and an O3 gas, and a second oxidizing gas comprising at least one selected from the group consisting of a H2O gas and a H2O2 gas, thereby forming a silicon oxide film on a surface of the object to be processed.Type: ApplicationFiled: May 12, 2011Publication date: November 17, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Pao-Hwa CHOU, Kota UMEZAWA, Yosuke WATANABE, Masayuki HASEGAWA
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Patent number: 8058177Abstract: Winged via structures to increase overlay margin are generally described. In one example, a method comprises depositing a sacrificial layer to an interlayer dielectric, the interlayer dielectric being coupled with a semiconductor substrate, forming at least one trench structure in the sacrificial layer wherein the trench structure comprises a first direction along a length of the trench structure and a second direction along a width of the trench structure wherein the second direction is substantially perpendicular to the first direction, depositing a light sensitive material to the trench structure and the sacrificial layer, and patterning at least one winged via structure in the light sensitive material to overlay the trench structure wherein the winged via structure extends in the second direction beyond the width of the trench structure onto the sacrificial layer.Type: GrantFiled: July 31, 2008Date of Patent: November 15, 2011Assignee: Intel CorporationInventors: Martin Weiss, Ruth Brain, Bob Bigwood, Shannon Daviess
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Patent number: 8058183Abstract: A method for restoring the dielectric constant of a low dielectric constant film is described. A porous dielectric layer having a plurality of pores is formed on a substrate. The plurality of pores is then filled with an additive to provide a plugged porous dielectric layer. Finally, the additive is removed from the plurality of pores.Type: GrantFiled: June 9, 2009Date of Patent: November 15, 2011Assignee: Applied Materials, Inc.Inventors: Zhenjiang Cui, May Yu, Alexandros T. Demos, Mehul Naik
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Patent number: 8058184Abstract: Disclosed is a producing method of a semiconductor device, including: loading at least one substrate formed on a surface thereof with a tungsten film into a processing chamber; and forming a silicon oxide film on the surface of the substrate which includes the tungsten film by alternately repeating following steps a plurality of times: supplying the processing chamber with a first reaction material including a silicon atom while heating the substrate at 400° C.; and supplying the processing chamber with hydrogen and water which is a second reaction material while heating the substrate at 400° C. at a ratio of the water with respect to the hydrogen of 2×10?1 or lower.Type: GrantFiled: January 5, 2010Date of Patent: November 15, 2011Assignee: Hitachi Kokusai Electric Inc.Inventors: Hironobu Miya, Masayuki Asai, Norikazu Mizuno
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Patent number: 8043975Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.Type: GrantFiled: July 1, 2010Date of Patent: October 25, 2011Assignee: Micron Technology, Inc.Inventors: John Smythe, Gurtej S. Sandhu
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Patent number: 8043937Abstract: It is an object to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide. The method for manufacturing a semiconductor device includes the steps of performing carbonization treatment on a surface of a silicon substrate to form a silicon carbide layer; adding ions to the silicon substrate to form an embrittlement region in the silicon substrate; bonding the silicon substrate and a base substrate with insulating layers interposed between the silicon substrate and the base substrate; heating the silicon substrate and separating the silicon substrate at the embrittlement region to form a stacked layer of the silicon carbide layer and a silicon layer over the base substrate with the insulating layers interposed between the base substrate and the stacked layer; and removing the silicon layer to expose a surface of the silicon carbide layer.Type: GrantFiled: March 24, 2010Date of Patent: October 25, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Toru Takayama
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Patent number: 8030222Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.Type: GrantFiled: July 31, 2006Date of Patent: October 4, 2011Assignee: Round Rock Research, LLCInventors: Luan Tran, Bill Stanton
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Patent number: 8030219Abstract: A coated substrate product is described comprising a substrate and a dielectric coating material comprising carbon, hydrogen, silicon, and oxygen. According to the method, the substrate is processed by plasma cleaning the surface and then depositing a dielectric coating by a suitable plasma process. The coating may contain one or more layers. The substrate may be a rigid material or a thin film or foil. The coated products of this invention have superior dielectric material properties and utility as substrates for the manufacture of rolled or parallel plate capacitors with high energy densities.Type: GrantFiled: February 7, 2006Date of Patent: October 4, 2011Assignees: Morgan Advanced Ceramics, Inc., K Systems CorporationInventors: Fred M. Kimock, Steven J. Finke, Richard L. C. Wu
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Patent number: 8030220Abstract: A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.Type: GrantFiled: October 14, 2009Date of Patent: October 4, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Dina H. Triyoso, Olubunmi O. Adetutu
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Patent number: 8021991Abstract: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.Type: GrantFiled: February 28, 2006Date of Patent: September 20, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Harold L Hughes, Bernard J Mrstik, Reed K Lawrence, Patrick J McMarr
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Publication number: 20110215445Abstract: Described herein are methods of forming dielectric films comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.Type: ApplicationFiled: January 28, 2011Publication date: September 8, 2011Applicant: AIR PRODUCTS AND CHEMICALS, INC.Inventors: Liu Yang, Manchao Xiao, Bing Han, Kirk S. Cuthill, Mark L. O'Neill
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Patent number: 8012886Abstract: A method is provided for treating a leadframe comprising copper or copper alloy to enhance adhesion of molding compound to it. The leadframe is oxidized in an oxidation treatment bath to form copper oxide on the surface of the leadframe. It is then dipped in a complexing or chelating agent to enhance the purity of the copper oxide formed. Thereafter, the leadframe is cleaned with an acid to remove any contaminants remaining on the leadframe.Type: GrantFiled: March 7, 2007Date of Patent: September 6, 2011Assignee: ASM Assembly Materials LtdInventors: Yiu Fai Kwan, Tat Chi Chan, Wai Chan, Chi Chung Lee
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Patent number: 8008190Abstract: Disclosed is a method of manufacturing a semiconductor device which includes: providing an insulating film formed above a semiconductor substrate with a processed portion; supplying a surface of the processed portion of the insulating film with a primary reactant from a reaction of a raw material including at least a Si-containing compound; and subjecting the primary reactant to dehydration condensation to form a silicon oxide film on the surface of the processed portion.Type: GrantFiled: June 20, 2008Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhide Yamada, Hideto Matsuyama, Hideshi Miyajima
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Patent number: 8008743Abstract: This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform thickness and excellent step coverage in holes with aspect ratios over 40:1. The films are transparent and good electrical insulators. This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices, particularly through materials and processes for producing semi-porous dielectric materials wherein surface porosity is significantly reduced or removed while internal porosity is preserved to maintain a desired low-k value for the overall dielectric material.Type: GrantFiled: September 27, 2004Date of Patent: August 30, 2011Assignee: President And Fellows of Harvard CollegeInventors: Roy G. Gordon, Jill Becker, Dennis Hausmann
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Patent number: 7998880Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.Type: GrantFiled: July 30, 2007Date of Patent: August 16, 2011Assignees: International Business Machines Corporation, Sony CorporationInventors: Son V. Nguyen, Sarah L. Lane, Eric G. Liniger, Kensaku Ida, Darryl D. Restaino
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Patent number: 7998844Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.Type: GrantFiled: July 15, 2008Date of Patent: August 16, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Akiharu Miyanaga, Takeshi Fukunaga, Hongyong Zhang
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Patent number: 7994070Abstract: A method for depositing a dielectric film on a substrate includes positioning a plurality of substrates in a process chamber, heating the process chamber to a deposition temperature between 400° C. and less than 650° C., flowing a first process gas comprising water vapor into the process chamber, flowing a second process gas comprising dichlorosilane (DCS) into the process chamber, establishing a gas pressure of less than 2 Torr, and reacting the first and second process gases to thermally deposit a silicon oxide film on the plurality of substrates. One embodiment further includes flowing a third process gas comprising nitric oxide (NO) gas into the process chamber while flowing the first process gas and the second process gas; and reacting the oxide film with the third process gas to form a silicon oxynitride film on the substrate.Type: GrantFiled: September 30, 2010Date of Patent: August 9, 2011Assignee: Tokyo Electron LimitedInventors: Anthony Dip, Kimberly G Reid
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Patent number: 7994035Abstract: There is provided a method of fabricating a semiconductor device in which a gate electrode is formed on an oxide film, which is formed by thermal oxidation on a substrate. The fabrication method includes: a first step of forming a first oxide film on the substrate; a second step of thermally processing the first oxide film in an inactive gas atmosphere; a third step of forming a second oxide film that is obtained by etching the first oxide film, which has been thermally processed in the inactive gas, to a predetermined film thickness; and a fourth step of forming and thermally processing a gate electrode on the second oxide film.Type: GrantFiled: February 3, 2009Date of Patent: August 9, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Isamu Matsuyama
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Patent number: 7994605Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.Type: GrantFiled: April 30, 2008Date of Patent: August 9, 2011Assignee: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Patent number: 7989363Abstract: A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections.Type: GrantFiled: October 27, 2008Date of Patent: August 2, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: David Gao, Mieno Fumitake
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Patent number: 7989364Abstract: A plasma oxidation process is performed to form a silicon oxide film on the surface of a target object by use of plasma with an O(1D2) radical density of 1×1012 [cm?3] or more generated from a process gas containing oxygen inside a process chamber of a plasma processing apparatus. During the plasma oxidation process, the O(1D2) radical density in the plasma is measured by a VUV monochromator 63, and a correction is made to the plasma process conditions.Type: GrantFiled: August 27, 2007Date of Patent: August 2, 2011Assignees: National University Corporation Nagoya University, Tokyo Electron LimitedInventors: Masaru Hori, Toshihiko Shiozawa, Yoshiro Kabe, Junichi Kitagawa
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Patent number: 7977121Abstract: The present invention provides a method for restoring the dielectric properties of a porous dielectric material. The method comprises providing a substrate comprising at least one layer of a porous dielectric material comprising a contaminant comprising at least one entrapped liquid having a surface tension, wherein the porous dielectric material comprising the at least one contaminant has a first dielectric constant. The substrate is contacted with a restoration fluid comprising water and at least one compound having a surface tension that is less than the surface tension of the at least one entrapped liquid in the at least one layer of a porous dielectric material. Upon drying, the porous dielectric material has a second dielectric constant that is lower than the first dielectric constant and all constituents of the restoration fluid are removed upon drying.Type: GrantFiled: November 17, 2006Date of Patent: July 12, 2011Assignee: Air Products and Chemicals, Inc.Inventors: Dnyanesh Chandrakant Tamboli, Madhukar Bhaskara Rao, Mark Leonard O'Neill
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Publication number: 20110165781Abstract: Methods of forming silicon oxide layers are described. The methods include mixing a carbon-free silicon-containing precursor with a radical-nitrogen precursor, and depositing a silicon-and-nitrogen-containing layer on a substrate. The radical-nitrogen precursor is formed in a plasma by flowing a hydrogen-and-nitrogen-containing precursor into the plasma. Prior to depositing the silicon-and-nitrogen-containing layer, a silicon oxide liner layer is formed to improve adhesion, smoothness and flowability of the silicon-and-nitrogen-containing layer. The silicon-and-nitrogen-containing layer may be converted to a silicon-and-oxygen-containing layer by curing and annealing the film. Methods also include forming a silicon oxide liner layer before applying a spin-on silicon-containing material.Type: ApplicationFiled: December 21, 2010Publication date: July 7, 2011Applicant: Applied Materials, Inc.Inventors: Jingmei Liang, Nitin K. Ingle
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Patent number: 7972979Abstract: Provided is a substrate processing method comprising: loading a substrate, on which polysilazane is applied, into a substrate process chamber; maintaining an inside of the substrate process chamber, into which the substrate is loaded, in water vapor atmosphere and depressurization atmosphere at a temperature of 400° C.; performing a first heat treatment process on the substrate in a state where the inside of the substrate process chamber is maintained in the water vapor atmosphere and the depressurization atmosphere at the temperature of 400° C.; next, increasing an inner temperature of the substrate process chamber from the temperature of 400° C. in the first heat treatment process to a temperature ranging from 900° C. to 1000° C.; and performing a second heat treatment process on the substrate in a state where the inside of the substrate process chamber is maintained in water vapor atmosphere and depressurization atmosphere at the temperature ranging from 900° C. to 1000° C.Type: GrantFiled: August 17, 2010Date of Patent: July 5, 2011Assignee: Hitachi Kokusai Electric, Inc.Inventors: Toru Harada, Masayoshi Minami
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Patent number: 7973390Abstract: A modifier for lowering relative dielectric constant of a low dielectric constant film used in semiconductor devices, the modifier of the low dielectric constant film being characterized in that it contains as an effective component a silicon compound represented by formula (1) R3-nHnSiN3??(1) in which R is a C1-C4 alkyl group, and n is an integer from 0 to 3.Type: GrantFiled: July 11, 2007Date of Patent: July 5, 2011Assignee: Central Glass Company, LimitedInventors: Tsuyoshi Ogawa, Mitsuya Ohashi