Using Electromagnetic Or Wave Energy (e.g., Photo-induced Deposition, Plasma, Etc.) Patents (Class 438/788)
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Patent number: 7494894Abstract: A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.Type: GrantFiled: August 29, 2002Date of Patent: February 24, 2009Assignee: Micron Technology, Inc.Inventors: Neal R. Rueger, William Budge, Weimin Li
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Patent number: 7494938Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.Type: GrantFiled: February 5, 2007Date of Patent: February 24, 2009Assignees: International Business Machines Corporation, Sony Corporation, Sony Electronics Inc.Inventors: Son V. Nguyen, Sarah L. Lane, Jia Lee, Kensaku Ida, Darryl D. Restaino, Takeshi Nogami
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Patent number: 7494941Abstract: At a time of a substrate loading step or/and at a time of a substrate unloading step, particles are effectively eliminated from a reaction chamber. Provided are a step of loading at least one wafer 200 into a reaction chamber 201, a step of introducing reaction gas into the reaction chamber 201, and exhausting an inside of the reaction chamber 201, thereby processing the wafer 200, and a step of unloading the processed wafer 200 from the reaction chamber 201. In the step of loading the wafer 200 or/and in the step of unloading the wafer 200, the inside of the reaction chamber 201 is exhausted at a larger exhaust flow rate than an exhaust flow rate in the step of processing the wafer 200.Type: GrantFiled: November 19, 2004Date of Patent: February 24, 2009Assignee: Hitachi Kokusai Electric Inc.Inventors: Osamu Kasahara, Kiyohiko Maeda, Akihiko Yoneda
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Patent number: 7491657Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film Is interposed between the gate and the PEOX film in the main chip region.Type: GrantFiled: March 2, 2007Date of Patent: February 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Hyung Lee, Seung-Han Yoo
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Patent number: 7491656Abstract: A silicon oxide film (1701) serving as a gate insulating film of a semiconductor device contains Kr. Therefore, the stress in the silicon oxide film (1701) and the stress at the interface between silicon and the silicon oxide film are relaxed, and the silicon oxide film has a high quality even though it was formed at a low temperature. The uniformity of thickness of the silicon oxide film (1701) on the silicon of the side wall of a groove (recess) in the element isolating region is 30% or less. Consequently, the silicon oxide film (1701) has its characteristics and reliability superior to those of a silicon thermal oxide film, and the element isolating region can be made small, thereby realizing a high-performance transistor integrated circuit preferably adaptable to an SOI transistor and a TFT.Type: GrantFiled: September 20, 2004Date of Patent: February 17, 2009Assignee: Foundation for Advancement of International ScienceInventor: Tadahiro Ohmi
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Publication number: 20090035927Abstract: Methods of forming dielectric layers on a substrate comprising silicon and oxygen are disclosed herein. In some embodiments, a method of forming a dielectric layer on a substrate includes provide a substrate having an exposed silicon oxide layer; treating an upper surface of the silicon oxide layer with a plasma; and depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition. The silicon nitride layer may be exposed to a plasma nitridation process. The silicon oxide and silicon nitride layers may be subsequently thermally annealed. The dielectric layers may be used as part of a gate structure.Type: ApplicationFiled: July 30, 2007Publication date: February 5, 2009Applicant: APPLIED MATERIALS, INC.Inventors: CHRISTOPHER S. OLSEN, TEJAL GOYANI, JOHANES SWENBERG
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Publication number: 20090035952Abstract: Methods of fabricating an oxide layer on a semiconductor substrate are provided herein. In some embodiments, a method of forming an oxide layer on a semiconductor substrate includes placing a substrate to be oxidized on a substrate support in a vacuum chamber of a plasma reactor, the chamber having an ion generation region remote from the substrate support; introducing a process gas into the chamber, the process gas comprising at least one of hydrogen (H2) and oxygen (O2)—provided at a flow rate ratio of hydrogen (H2) to oxygen (O2) of up to about 3:1—or water vapor (H2O vapor); and generating an inductively coupled plasma in the ion generation region of the chamber to form a silicon oxide layer on the substrate.Type: ApplicationFiled: July 30, 2007Publication date: February 5, 2009Applicant: APPLIED MATERIALS, INC.Inventors: THAI CHENG CHUA, JAMES P. CRUSE, CORY CZARNIK
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Publication number: 20090029564Abstract: In a plasma oxidation treatment apparatus 100, dual plate structure 60 is arranged above a susceptor 2. An upper plate 61 and a lower plate 62 are made of a dielectric material such as quartz, separately arranged in parallel at a prescribed interval, for instance an interval of 5 mm, and have a plurality of through holes 61a, 62a. The two plates are arranged one over another by shifting the positions so that the through hole 62a of the lower plate 62 and the through hole 61a of the upper plate 61 are not overlapped.Type: ApplicationFiled: May 30, 2006Publication date: January 29, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Jun Yamashita, Toshio Nakanishi, Tatsuo Nishita
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Patent number: 7482265Abstract: A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the layer with radiation having a first wavelength. After pore forming, a third step comprises cross-linking the dielectric by irradiating it at a second wavelength, the second being less than the first. In an embodiment, the irradiating wavelengths comprise ultra-violet radiation. Embodiments may further include repairing processing damage wherein the damage includes dangling bonds or silanol formation. The repairing includes annealing in a carbon-containing ambient such as C2H4, C3H6, or hexamethyldisilazane (HMDS).Type: GrantFiled: January 10, 2006Date of Patent: January 27, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-I Chen, Tien-I Bao, Shwang-Ming Cheug, Chen-Hua Yu
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Patent number: 7482244Abstract: A wafer including a high stressed thin film thereon is lifted, and a pre-heating process is performed while the wafer is lifted. Subsequently, a dielectric layer is deposited on the high stressed thin film.Type: GrantFiled: September 16, 2005Date of Patent: January 27, 2009Assignee: United Microelectronics Corp.Inventors: Chih-Jen Mao, Hui-Shen Shih, Kuo-Wei Yang, Chun-Han Chuang, Chun-Hung Hsia
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Patent number: 7473654Abstract: A method of forming an oxide film 3 on a surface of a base material 12 constituted from an inorganic material is disclosed. The oxide film 3 is constituted from a material containing an oxide of the inorganic material as a major component thereof. The method includes the steps of: preparing the base material 12; supplying a process liquid containing alcohol onto the surface of the base material 12 to form a liquid film 2 of the process liquid thereon; producing an oxide of the inorganic material through a reaction of the inorganic material with the alcohol in the liquid film 2; and eliminating the process liquid remaining in the liquid film 2 to form the oxide film 3 on the surface of the base material 12. Further, the oxide film 3 described above, a component including the oxide film 3, and an electronic apparatus including the component are disclosed.Type: GrantFiled: August 8, 2005Date of Patent: January 6, 2009Assignee: Seiko Epson CorporationInventor: Yukihiro Hashi
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Patent number: 7470454Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as interlevel dielectrics in integrated circuits as well as methods for making same. In certain embodiments of the invention, there is provided a low-temperature process to remove at least a portion of at least one pore-forming material within a composite film thereby forming a porous film. The pore-forming material may be removed via exposure to at least one energy source, preferably an ultraviolet light source, in a non-oxidizing atmosphere.Type: GrantFiled: July 21, 2003Date of Patent: December 30, 2008Assignee: Air Products and Chemicals, Inc.Inventors: Aaron Scott Lukas, Mark Leonard O'Neill, Mark Daniel Bitner, Jean Louise Vincent, Raymond Nicholas Vrtis, Eugene Joseph Karwacki, Jr.
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Patent number: 7465679Abstract: A silicon oxide film is formed to cover an island non-monocrystalline silicon region by plasma CVD using an organic silane having ethoxy groups (e.g., TEOS) and oxygen as raw materials, while hydrogen chloride or a chlorine-containing hydrocarbon (e.g., trichloroethylene) of a fluorine-containing gas is added to the plasma CVD atmosphere, preferably in an amount of from 0.01 to 1 mol % of the atmosphere so as to reduce the alkali elements from the silicon oxide film formed and to improve the reliability of the film. Prior to forming the silicon oxide film, the silicon region may be treated in a plasma atmosphere containing oxygen and hydrogen chloride or a chlorine-containing hydrocarbon. The silicon oxide film is obtained at low temperatures and this has high reliability usable as a gate-insulating film in a semiconductor device.Type: GrantFiled: December 20, 1999Date of Patent: December 16, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takeshi Fukada, Mitsunori Sakama, Yukiko Uehara, Hiroshi Uehara
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Patent number: 7465681Abstract: The invention is directed to preparing optical elements having a thin, smooth, dense coating or film thereon, and a method for making such coating or film. The coated element has a surface roughness of <1.0 nm rms. The coating materials include hafnium oxide or a mixture of hafnium oxide and another oxide material, for example silicon dioxide. The method includes the use of a reverse mask to deposit the coating or film on a rotating substrate.Type: GrantFiled: August 25, 2006Date of Patent: December 16, 2008Assignee: Corning IncorporatedInventors: Gary Allen Hart, Robert LeRoy Maier, Jue Wang
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Patent number: 7465680Abstract: A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.Type: GrantFiled: September 7, 2005Date of Patent: December 16, 2008Assignee: Applied Materials, Inc.Inventors: Xiaolin Chen, Srinivas D. Nemani, DongQing Li, Jeffrey C. Munro, Marlon E. Menezes
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Patent number: 7462568Abstract: Disclosed herein is a method for forming an interlayer dielectric film in a semiconductor device. The method comprises the steps of preparing a semiconductor substrate having a dielectric film and conductive film patterns sequentially deposited thereon, and depositing a high plasma oxide film as the interlayer dielectric film on the conductive film patterns and the dielectric films by supplying H2 as an adding gas together with a source gas. A dangling bond in an interface of the semiconductor substrate is reduced by adding hydrogen into the dielectric film, thereby enhancing the uniformity of the deposition. Moreover, hydrogen in the dielectric film decreases current leakage occurring in the gate by preventing electrons in the plasma from flowing into a gate through the bit-line, thereby enhancing the refresh characteristics of the semiconductor device.Type: GrantFiled: May 27, 2005Date of Patent: December 9, 2008Assignee: Hynix Semiconductor Inc.Inventor: Jie Won Chung
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Patent number: 7459373Abstract: A method of fabricating and separating semiconductor structures comprises the steps of: (a) partially forming a semiconductor structure attached to a support structure, the partially formed semiconductor structure comprising a plurality of partially formed devices, where the partially formed devices are attached to one another by at least one connective layer; (b) forming a partial mask layer over at least a part of the partially formed devices; (c) etching the connective layer to separate the devices; and (d) removing the partial mask layer. Advantages of the invention include higher yield than conventional techniques. In addition, less expensive equipment can be used to separate the devices. The result is a greater production of devices per unit of time and per dollar.Type: GrantFiled: November 15, 2005Date of Patent: December 2, 2008Assignee: Verticle, Inc.Inventor: Myung Cheol Yoo
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Publication number: 20080293257Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.Type: ApplicationFiled: August 6, 2008Publication date: November 27, 2008Applicant: International Business Machines CorporationInventors: Chih-Chao Yang, Haining Yang, Keith Kwong Hon Wong
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Patent number: 7456116Abstract: A method to form a silicon oxide layer, where the method includes the step of providing a continuous flow of a silicon-containing precursor to a chamber housing a substrate, where the silicon-containing precursor is selected from TMOS, TEOS, OMTS, OMCTS, and TOMCATS. The method may also include the steps of providing a flow of an oxidizing precursor to the chamber, and causing a reaction between the silicon-containing precursor and the oxidizing precursor to form a silicon oxide layer. The method may further include varying over time a ratio of the silicon-containing precursor:oxidizing precursor flowed into the chamber to alter a rate of deposition of the silicon oxide on the substrate.Type: GrantFiled: December 20, 2004Date of Patent: November 25, 2008Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Shan Wong, Xinyun Xia, Vikash Banthia, Won B. Bang, Yen-Kun V. Wang, Zheng Yuan
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Patent number: 7452829Abstract: In a process of forming a silicon oxide film 116 that constitutes an interlayer insulating film with TEOS as a raw material through the plasma CVD method, the RF output is oscillated at 50 W, and the RF output is gradually increased from 50 W to 250 W (an output value at the time of forming a film) after discharging (after the generation of O2-plasma). A TEOS gas is supplied to start the film formation simultaneously when the RF output becomes 250 W, or while the timing is shifted. As a result, because the RF power supply is oscillated at a low output when starting discharging, a voltage between the RF electrodes can be prevented from changing transitionally and largely.Type: GrantFiled: June 29, 2006Date of Patent: November 18, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masaaki Hiroki, Mitsunori Sakama
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Patent number: 7446060Abstract: Disclosed is a film-forming method, comprising supplying into a plasma processing chamber at least three kinds of gases including a silicon compound gas, an oxidizing gas, and a rare gas, the percentage of the partial pressure of the rare gas (Pr) based on the total pressure being not smaller than 85%, i.e., 85%?Pr<100%, and generating a plasma within the plasma processing chamber so as to form a film of silicon oxide on a substrate to be processed.Type: GrantFiled: January 3, 2007Date of Patent: November 4, 2008Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventors: Masashi Goto, Kazufumi Azuma, Yukihiko Nakata
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Patent number: 7446061Abstract: A semiconductor substrate with a groove is placed in a plasma generating reaction chamber. Silicon, oxygen and hydrogen containing gases are introduced into the reaction chamber as process gases. A ratio of a gas flow of the hydrogen containing gas except the silicon containing gas to a total gas flow of the silicon containing gas and the oxygen containing gas defines a first gas-flow ratio. A ratio of a gas flow of the oxygen containing gas to that of the silicon containing gas defines a second gas-flow ratio. The first and second gas-flow ratios establish a linear function for a critical condition. A cluster formation condition is set up by relatively increasing the first gas-flow ratio while relatively decreasing the second gas-flow ratio with respect to the critical condition. A cluster suppression condition is also set up by relatively decreasing the first gas-flow ratio while relatively increasing the second gas-flow ratio with respect to the critical condition.Type: GrantFiled: December 5, 2006Date of Patent: November 4, 2008Assignee: Kabushiki Kaihsa ToshibaInventors: Hiroshi Sato, Rempei Nakata, Yukio Nishiyama, Taketo Matsuda
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Patent number: 7442656Abstract: A silicon oxide film is formed on a target substrate by CVD, in a process field configured to be selectively supplied with a first process gas containing a chlorosilane family gas, a second process gas containing a Cl-replacing gas, and a third process gas containing an oxidizing gas. This method alternately includes first to sixth steps. The first, third, and fifth steps perform supply of the first, second, and third process gases, respectively, while stopping supply of the other two process gases. Each of the second, fourth, and sixth steps stops supply of the first to third process gases. The third and fifth steps include an excitation period of supplying the second and third process gases, respectively, to the process field while exciting the respective process gases by an exciting mechanism.Type: GrantFiled: June 7, 2006Date of Patent: October 28, 2008Assignee: Tokyo Electron LimitedInventor: Hiroyuki Matsuura
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Patent number: 7435684Abstract: This invention relates to electronic device fabrication processes for making devices such as semiconductor wafers and resolves the fluorine loading effect in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features. The fluorine loading effect in the chamber is minimized and wafers are provided having less deposition thickness variations by employing the method using a hydrogen plasma treatment of the chamber and the substrate after the chamber has been used to grow a dielectric film on a substrate. After the hydrogen plasma treatment of the chamber, the chamber is treated with an etchant gas to etch the substrate. Preferably a hydrogen gas is then introduced into the chamber after the etching process and the process repeated until the fabrication process is complete. The wafer is then removed from the chamber and a new wafer placed in the chamber and the above fabrication process repeated.Type: GrantFiled: July 26, 2006Date of Patent: October 14, 2008Assignee: Novellus Systems, Inc.Inventors: Chi-I Lang, Ratsamee Limdulpaiboon, Kan Quan Vo
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Publication number: 20080246099Abstract: An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon coating using UV O3 low temperature oxidation and plasma nitridation using either decoupled plasma nitridation or NH3 annealing.Type: ApplicationFiled: April 9, 2007Publication date: October 9, 2008Inventors: Ajith Varghese, James J. Chambers
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Publication number: 20080233765Abstract: A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Inventors: Chung-Chi Ko, Lih-Ping Li, Yung-Cheng Lu, Hui-Lin Chang, Chih-Hsien Lin
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Patent number: 7427518Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.Type: GrantFiled: October 28, 2005Date of Patent: September 23, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Seiji Inumiya, Motoyuki Sato, Akio Kaneko, Kazuhiro Eguchi
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Patent number: 7422774Abstract: The present invention generally provides a method for depositing a low dielectric constant film using an e-beam treatment. In one aspect, the method includes delivering a gas mixture comprising one or more organosilicon compounds and one or more hydrocarbon compounds having at least one cyclic group to a substrate surface at deposition conditions sufficient to deposit a non-cured film comprising the at least one cyclic group on the substrate surface. The method further includes substantially removing the at least one cyclic group from the non-cured film using an electron beam at curing conditions sufficient to provide a dielectric constant less than 2.5 and a hardness greater than 0.5 GPa.Type: GrantFiled: March 9, 2005Date of Patent: September 9, 2008Assignee: Applied Materials, Inc.Inventors: Yi Zheng, Srinivas D. Nemani, Li-Qun Xia, Eric Hollar, Kang Sub Yim
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Patent number: 7410913Abstract: Provided are methods for manufacturing silicon rich oxide (SRO) layers useful in the fabrication of semiconductor devices, for example, non-volatile memory devices, and methods for fabricating semiconductor devices incorporating such SRO layers. The methods include absorbing a first silicon source gas onto the substrate, oxidizing the first absorbed layer to form a silicon oxide layer, absorbing a second silicon source gas onto the substrate and reducing the second absorbed layer to form a silicon layer. The combination of the silicon oxide layer(s) and the silicon layer(s) comprise, in turn, a composite SRO layer. These manufacturing methods facilitate control of the oxygen concentration in the SRO, the relative thicknesses of the silicon oxide and silicon layers, and provides improved step coverage, thus allowing the manufacturing of high quality semiconductor devices.Type: GrantFiled: September 12, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hyun Lee, Sang-Bong Bang
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Patent number: 7405129Abstract: A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising a lead selenide nanowire or nanocrystal film and methods of forming these devices.Type: GrantFiled: May 26, 2005Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Cherie R. Kagan, Christopher B. Murray, Robert L. Sandstrom, Dmitri V. Talapin
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Patent number: 7390757Abstract: The present invention relates to fluorinated silicate glass (FSG) with low dielectric constant and improved gap-fill characteristics. In the present method, a fluorinated silicon source, an optional fluorine source, an optional carbon source, a hydrogen source, and an oxygenator are used as the reactant gases. Inert or carrier gas(es) may also be used. In accordance with the present invention, the reactant gas mixture does not comprise a silane compound having the general formula SixHy, wherein x has a range of 1 to 2, y has a range of 4 to 6. The material deposited is thus referred to herein alternatively as “SixFy-only FSG” or “SixFy-only fluorinated oxide” (“SOFO”).Type: GrantFiled: November 15, 2005Date of Patent: June 24, 2008Assignee: Applied Materials, Inc.Inventors: Seong-Oh Woo, Jun Tae Choi
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Patent number: 7390537Abstract: Methods of preparing a carbon doped oxide (CDO) layer with a low dielectric constant and low residual stress are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to a chemical precursor having molecules with at least one carbon-carbon triple bond, followed by igniting and maintaining a plasma in a deposition chamber using radio frequency power having high and low frequency components or one frequency component only, and depositing the carbon doped oxide film under conditions in which the resulting dielectric layer has a compressive stress or a tensile stress of not greater than, e.g., about 50 MPa, and dielectric constant of less than 3.Type: GrantFiled: February 27, 2004Date of Patent: June 24, 2008Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, Dong Niu, Haiying Fu
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Patent number: 7380328Abstract: The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.Type: GrantFiled: November 25, 2003Date of Patent: June 3, 2008Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Publication number: 20080124940Abstract: A method of forming a dielectric layer is provided. A first dielectric layer is formed on a substrate having metal layers formed thereon. The first dielectric layer includes overhangs in the spaces between two neighboring metal layers and voids under the overhangs. The first dielectric layer is partially removed to cut off the overhangs and expose the voids and therefore openings are formed. A second dielectric layer is formed on the dielectric layer to fill up the opening.Type: ApplicationFiled: September 22, 2006Publication date: May 29, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsu-Sheng Yu, Shing-Ann Lo, Ta-Hung Yang
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Publication number: 20080122045Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.Type: ApplicationFiled: November 29, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Haining Yang, Keith Kwong Hon Wong
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Patent number: 7378356Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated processes performed on a reactor according to the present inention.Type: GrantFiled: March 16, 2002Date of Patent: May 27, 2008Assignee: SpringWorks, LLCInventors: Hongmei Zhang, Mukundan Narasimhan, Ravi B. Mullapudi, Richard E. Demaray
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Patent number: 7378304Abstract: The present method of forming a silicon oxide layer comprises providing two frequency excitation plasma CVD device which comprises a high frequency electrode, a susceptor electrode, and two matching box for impedance matching between the electrodes and a power supply, wherein one side electrode constituting a tuning condenser of a matching box toward the high frequency electrode is the high frequency electrode; placing a substrate on the susceptor electrode; applying high frequency electric power on the high frequency electrode and the susceptor electrode respectively; and forming a silicon oxide layer on the substrate by generating plasma with using a reaction gas of which main reaction gas is a mixing gas of monosilane and nitrous oxide.Type: GrantFiled: December 30, 2004Date of Patent: May 27, 2008Assignee: LG.Philips LCD Co., Ltd.Inventors: Kwang Nam Kim, Gee Sung Chae
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Patent number: 7374635Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.Type: GrantFiled: December 11, 2006Date of Patent: May 20, 2008Assignee: Tokyo Electron LimitedInventors: Shigemi Murakawa, Toshikazu Kumai, Toshio Nakanishi
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Patent number: 7368369Abstract: A method for activating the P-type semiconductor layer of a semiconductor device is disclosed in this present invention. The above-mentioned method can activate the impurities in the P-type semiconductor layer of a semiconductor device by plasma. The plasma comprises a gas source including a VI Group compound element. The performance of the semiconductor device activated by plasma according to this invention is similar to the performance of the semiconductor device activated by heat in the prior art. Therefore, this invention can provide a method, other then heat, for activating the P-type semiconductor layer of a semiconductor device. Moreover, in this invention, during the activating process by plasma, the layers other than P-type semiconductor layer will not be affected by plasma. That is, the activating process according to this invention will not cause any side-reactions in the layers other than the P-type semiconductor layer of a semiconductor device.Type: GrantFiled: February 4, 2005Date of Patent: May 6, 2008Assignee: Uni Light Technology Inc.Inventors: Bor-Jen Wu, Nae-Guann Yih, Yuan-Hsiao Chang
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Patent number: 7351668Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding or oxynitriding gas, and a third process gas containing a carbon hydride gas. This method alternately includes first to fourth steps. The first step performs supply of the first and third process gases to the field while stopping supply of the second process gas to the process field. The second step stops supply of the first to third process gases to the field. The third step performs supply of the second process gas to the field while stopping supply of the first and third process gases to the field. The fourth step stops supply of the first to third process gases to the field.Type: GrantFiled: March 7, 2006Date of Patent: April 1, 2008Assignee: Tokyo Electron LimitedInventors: Pao-Hwa Chou, Kazuhide Hasebe
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Patent number: 7341761Abstract: Methods of preparing a carbon doped oxide (CDO) layers having a low dielectric constant are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to one or multiple carbon-doped oxide precursors having molecules with at least one carbon—carbon triple bond, or carbon—carbon double bond, or a combination of these groups and depositing the carbon doped oxide dielectric layer under conditions in which the resulting dielectric layer has a dielectric constant of not greater than about 2.7.Type: GrantFiled: March 11, 2004Date of Patent: March 11, 2008Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, Haiying Fu, Xingyuan Tang
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Publication number: 20080050932Abstract: The present invention generally provides an apparatus and method for reducing defects on films deposited on semiconductor substrates. One embodiment of the present invention provides a method for depositing a film on a substrate. The method comprises treating the substrate with a first plasma configured to reduce pre-existing defects on the substrate, and depositing a film comprising silicon and carbon on the substrate by applying a second plasma generated from at least one precursor and at least one reactant gas.Type: ApplicationFiled: August 23, 2006Publication date: February 28, 2008Inventors: Annamalai Lakshmanan, Vu NT Nguyen, Sohyun Park, Ganesh Balasubramanian, Steven Reiter, Tsutomu Kiyohara, Francimar Schmitt, Bok Hoen Kim
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Patent number: 7335586Abstract: A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric layer with a silazane to form a monolayer of silane molecules on the surface, and applying a second plasma to the surface of the dielectric layer to induce a polymerization of at least a portion of the silane molecules. The polymerized silane molecules form a cross-linked matrix that builds over a substantial portion of the surface of the dielectric layer and seals at least some of the exposed pores.Type: GrantFiled: June 10, 2005Date of Patent: February 26, 2008Assignee: Intel CorporationInventors: Vijayakumar S. RamachandraRao, Boyan Boyanov, Grant Kloster, Hyun-Mog Park
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Patent number: 7332409Abstract: A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed.Type: GrantFiled: June 9, 2005Date of Patent: February 19, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Won Cha, Kyu-Tae Na, Yong-Soon Choi, Eunkee Hong, Ju-Seon Goo
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Patent number: 7329956Abstract: A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the opening remain relatively untreated by the plasma. Thereafter, one or more barrier layers may be formed and the opening may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by plasma bombardment or ion implantation using a gas selected from one of O2, an O2/N2 mixture, H2O, or combinations thereof.Type: GrantFiled: September 12, 2006Date of Patent: February 12, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ching-Ya Wang
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Patent number: 7329612Abstract: A semiconductor device is manufactured by the steps of generating a film forming gas by setting a flow rate ratio of H2O to any one of a silicon-contained organic compound having a siloxane bond and a silicon-contained organic compound having a CH3 group to 4 or more and adjusting a gas pressure to 1.5 Torr or more, applying a power to the film forming gas to generate a plasma thereof so as to react it, and thus forming a low-dielectric insulating film (62) on a substrate (61), plasmanizing a process gas containing at least any one of He, Ar, H2 or deuterium, and bringing the low-dielectric insulating film (62) into contact with the plasma of the process gas.Type: GrantFiled: October 20, 2003Date of Patent: February 12, 2008Assignee: Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Yuhko Nishimoto, Kazuo Maeda
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Patent number: 7329586Abstract: Methods deposit a film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. Flows of first precursor deposition gases are provided to the substrate processing chamber. A first high-density plasma is formed from the flows of first deposition gases to deposit a first portion of the film over the substrate and within the gap with a first deposition process that has simultaneous deposition and sputtering components until after the gap has closed. A sufficient part of the first portion of the film is etched back to reopen the gap. Flows of second precursor deposition gases are provided to the substrate processing chamber. A second high-density plasma is formed from the flows of second precursor deposition gases to deposit a second portion of the film over the substrate and within the reopened gap with a second deposition process that has simultaneous deposition and sputtering components.Type: GrantFiled: June 24, 2005Date of Patent: February 12, 2008Assignees: Applied Materials, Inc., Matsushita Electric Industrial Co., Ltd.Inventors: Manoj Vellaikal, Hemant P. Mungekar, Young S. Lee, Yasutoshi Okuno, Hiroshi Yuasa
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Patent number: 7314837Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.Type: GrantFiled: December 29, 2005Date of Patent: January 1, 2008Assignee: Micron Technology, Inc.Inventors: Li Li, Weimin Li
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Patent number: 7309662Abstract: This invention relates to a method and apparatus for forming a film on the substrate. The method comprises supplying to the chamber in gaseous or vapor form a silicon containing organic compound and an oxidizing agent in the presence of a plasma to deposit a film on the substrate and setting the film such that carbon containing groups are retained therein. In particular embodiments the setting is achieved by exposing the film to H2 plasma.Type: GrantFiled: June 26, 2000Date of Patent: December 18, 2007Assignee: Aviza Europe LimitedInventors: Katherine Giles, Knut Beekmann, Christopher David Dobson, John MacNeil, Antony Paul Wilby
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Patent number: 7307028Abstract: Disclosed is a film-forming method, comprising supplying into a plasma processing chamber at least three kinds of gases including a silicon compound gas, an oxidizing gas, and a rare gas, the percentage of the partial pressure of the rare gas (Pr) based on the total pressure being not smaller than 85%, i.e., 85%?Pr<100%, and generating a plasma within the plasma processing chamber so as to form a film of silicon oxide on a substrate to be processed.Type: GrantFiled: April 12, 2004Date of Patent: December 11, 2007Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventors: Masashi Goto, Kazufumi Azuma, Yukihiko Nakata