Using Electromagnetic Or Wave Energy (e.g., Photo-induced Deposition, Plasma, Etc.) Patents (Class 438/788)
  • Publication number: 20070273003
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device is provided. The method includes the steps of forming a first insulating layer on a top surface of a semiconductor substrate having a plurality of patterns, immediately before gaps between the patterns are completely closed; forming a lower insulating film by isotropically etching the first insulating layer for a specific amount of time, such that aspect ratios of the gaps between the patterns are reduced; forming a second insulating layer on the lower insulating film such that the gaps between the patterns are completely filled with the second insulating film; and forming an upper insulating film by planarizing the second insulating layer.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 29, 2007
    Applicant: DONGBU HITEK CO., LTD.
    Inventor: Jong-Taek Hwang
  • Patent number: 7297620
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Patent number: 7294588
    Abstract: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: November 13, 2007
    Assignee: Applied Materials, Inc.
    Inventors: M. Ziaul Karim, DongQing Li, Jeong Soo Byun, Thanh N. Pham
  • Patent number: 7294583
    Abstract: A method for depositing conformal dielectric films uses alkoxy silanol or silanediol precursors and oxidizing and/or hydrolyzing agents. The method produces a material with liquid-like flow properties capable of achieving improved high aspect ratio gap fill more efficiently than previous methods using alkoxysilanes since fewer oxidation reactions are required. In addition, the dielectric can be formed with or without a metal-containing catalyst/nucleation layer, so that metal content in the dielectric film can be avoided, if desired. Seams and voids are therefore avoided in gaps filled more efficiently with higher quality dielectric. In addition, the films as dense as deposited, reducing or eliminating the need for post-deposition processing (e.g., annealing).
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 13, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Ron Rulkens, George D. Papasouliotis, Dennis M. Hausmann, Raihan M. Tarafdar, Bunsen Nie, Adrianne K. Tipton, Jeff Tobin
  • Patent number: 7288463
    Abstract: Conformal dielectric deposition processes supplemented with a deposited expansion material can fill high aspect ratio narrow width gaps with significantly reduced incidence of voids or weak spots. The technique can also be used generally to form composites, such as for the densification of any substrate having open spaces or gaps to be filled without the incidence of voids or seams.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: October 30, 2007
    Assignee: Novellus Systems, Inc.
    Inventor: George D. Papasouliotis
  • Patent number: 7285503
    Abstract: A method of forming a cap layer over a dielectric layer on a substrate including forming a plasma from a process gas including oxygen and tetraethoxysilane, and depositing the cap layer on the dielectric layer, where the cap layer comprises a thickness of about 600 ? or less, and a compressive stress of about 200 MPa or more. Also, a method of forming a cap layer over a dielectric layer on a substrate including forming a process gas by flowing together about 200 mgm to about 8000 mgm of tetraethoxysilane, about 2000 to about 20000 sccm of oxygen (O2), and about 2000 sccm to about 20000 sccm of carrier gas, generating a plasma from the process gas, where one or more RF generators supply about 50 watts to about 100 watts of low frequency RF power to the plasma, and about 100 watts to about 600 watts of high frequency RF power to the plasma, and depositing the cap layer on the dielectric layer.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: October 23, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Vu Ngoc Tran Nguyen, Bok Hoen Kim, Kang Sub Yim
  • Patent number: 7279434
    Abstract: The material contemplated by this invention for the formation of a low-dielectric-constant film contains in all the stereoisomer molecules of 1,3,5,7-tetramethyl cyclotetrasiloxane (TMCTS) not less than 15% and not more than 100% of a stereoisomer having all the four hydrogen atoms forming an Si—H bond fall on the same size relative to the Si—O ring plane. It is utilized as a material for forming a low-dielectric-constant film which can be used for enhancing the function of an integrated circuit in the field of semiconductors.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: October 9, 2007
    Assignees: National Institute of Advanced Industrial Science and Technology, Tokyo Electron Limited
    Inventors: Nobuhiro Hata, Hidenori Miyoshi
  • Patent number: 7279398
    Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: October 9, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Trung T. Doan, Ronald A. Weimer, Kevin L. Beaman, Lyle D. Breiner, Lingyi A. Zheng, Er-Xuan Ping, Demetrius Sarigiannis, David J. Kubista
  • Patent number: 7273823
    Abstract: A method of processing a substrate including depositing a low dielectric constant film comprising silicon, carbon, and oxygen on the substrate and depositing an oxide rich cap on the low dielectric constant film is provided. The low dielectric constant film is deposited in the presence of low frequency RF power from a gas mixture including an organosilicon compound and an oxidizing gas. The low frequency RF power is terminated after the deposition of the low dielectric constant film. The oxide rich cap is deposited on the low dielectric constant film in the absence of low frequency RF power from another gas mixture including the organosilicon compound and the oxidizing gas used to deposit the low dielectric constant film.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: September 25, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Annamalai Lakshmanan, Daemian Raj, Francimar Schmitt, Bok Hoen Kim, Ganesh Balasubramanian
  • Patent number: 7273638
    Abstract: A method of oxidizing a substrate having area of about 30,000 mm2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal suicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1e12 cm?3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: September 25, 2007
    Assignees: International Business Machines Corp., Infineon Technologies, North American Corp.
    Inventors: Michael Belyansky, Oleg Glushenkov, Andreas Knorr
  • Patent number: 7271110
    Abstract: An embodiment of the invention is a HDP CVD FSG layer and an HDP CVD SIN layer with more stability (e.g., less free F and less free H). A feature is that the FSG and SIN are formed using a HDP CVD process with a high plasma density between 1E12 and 1E15 ions/cc and more preferably between 1E14 and 1E15 ions/cc. The high bias has sufficient energy to break the F—Si bonds in the FSG. The high bias has sufficient energy to break the H—Si bonds in the silicon nitride. Whereby the FSG layer has less F and the SiN layer has less H that increases the FSG/SiN interface reliability. The embodiments can be used on smooth surfaces (non-gap fill applications).
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: September 18, 2007
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Wei Lu, Liang Choo Hsia
  • Patent number: 7268089
    Abstract: A method of forming a PE-TEOS layer of a semiconductor IC device provides uniformly thick PE-TEOS layers on a batch of wafers. First, a loading wafer cassette is prepared to provide the wafers to be processed. Next, a process atmosphere is pre-created in a processing chamber. Then the wafers are supplied in sequence into the chamber from the loading wafer cassette and the wafers are mounted on a heater table in the chamber. Next, the PE-TEOS layer is deposited on the wafers by spraying a process gas into the chamber through showerheads. Next, the wafers are discharged from the chamber. Once the chamber is cleared of wafers, the inside of the chamber is cleaned by supplying a cleaning gas into the chamber, and exciting the cleaning gas with RF power. Subsequently, more TEOS gas is supplied into the chamber through the showerheads without being excited by RF power to especially reduce the temperature of the showerheads and that prevailing inside the chamber.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: September 11, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-Jun Jang
  • Patent number: 7268057
    Abstract: The invention includes methods in which oxide is formed within openings in a three-step process. A first step is deposition of oxide under a pressure of greater than 15 mTorr. A second step is removal of a portion of the oxide with an etch. A third step is an oxide deposition under a pressure of less than or equal to 10 mTorr. Methodology of the present invention can be utilized for forming trenched isolation regions, such as, for example, shallow trench isolation regions.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Ryan, Damon E. VanGerpen
  • Patent number: 7259112
    Abstract: The invention concerns a method for minimizing “corner” effects in shallow silicon oxide trenches, by densifying the silicon oxide layer after it has been deposited in the trenches. Said densification is preferably carried out by irradiating the layer under luminous radiation with weak wavelength.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: August 21, 2007
    Assignee: Fahrenheit Thermoscope, LLC
    Inventors: Patrick Schiavone, Frédéric Gaillard
  • Publication number: 20070190808
    Abstract: A system and method for producing a film is described. One embodiment of the process includes the following processes: providing a substrate comprising a glass plate, electrodes; and bus bars; heating the substrate to an approximate critical temperature; initiating the chemical vapor deposition process when the substrate is near the approximate critical temperature, thereby depositing a film on the substrate; maintaining the upper portion of the film at approximately the critical temperature while the chemical vapor deposition process is ongoing; terminating the chemical vapor deposition process once the film has reached a desired thickness; and cooling the substrate and the deposited film.
    Type: Application
    Filed: November 9, 2006
    Publication date: August 16, 2007
    Inventors: Michael W. Stowell, Jose M. Dieguez-Campo, Michael Liehr
  • Patent number: 7238616
    Abstract: The present invention provides a processing system comprising a remote plasma activation region for formation of active gas species, a transparent transfer tube coupled between the remote activation region and a semiconductor processing chamber, and a source of photo-energy for maintaining activation of the active species or providing photo-energy for a non-plasma species during transfer through the transparent tube to the processing chamber. The source of photo-energy preferably includes an array of UV lamps. Additional UV lamps may also be used to further sustain active species and assist processes by providing additional in-situ energy through a transparent window of the processing chamber. The system can be utilized for processes such as layer-by-layer annealing and deposition and also removal of contaminants from deposited layers.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: July 3, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Vishnu K. Agarwal
  • Patent number: 7229935
    Abstract: A method for forming a thin film includes: supplying an additive gas, a dilution gas, and a silicon-containing source gas into a reaction chamber wherein a substrate is placed; forming a thin film on the substrate by plasma CVD under a given pressure with a given intensity of radio-frequency (RF) power from a first point in time to a second point in time; at the second point in time, stopping the supply of the silicon-containing source gas; and at the second point in time, beginning reducing but not stopping the RF power, and beginning reducing the pressure, wherein the reduction of the RF power and the reduction of the pressure are synchronized up to a third point in time.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: June 12, 2007
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Kenichi Kagami, Manabu Kato
  • Patent number: 7229931
    Abstract: Methods are provided for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A process gas having a silicon-containing gas, an oxygen-containing gas, and a fluent gas is flowed into the substrate processing chamber. The fluent gas is introduced into the substrate processing chamber at a flow rate of at least 500 sccm. A plasma is formed having an ion density of at least 1011 ions/cm3 from the process gas to deposit a first portion of the silicon oxide film over the substrate and into the gap. Thereafter, the deposited first portion is exposed to an oxygen plasma having at least 1011 ions/cm3. Thereafter, a second portion of the silicon oxide film is deposited over the substrate and into the gap.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: June 12, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hemant P. Mungekar, Young S Lee, Manoj Vellaikal, Karen Greig, Bikram Kapoor
  • Patent number: 7223706
    Abstract: A method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy. The gas rates and pressure are selected to produce a plasma enhanced deposited oxide film on a substrate having a Si—O—Si bond peak absorbance in the IR spectrum of at least 1092 cm?1.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 29, 2007
    Assignee: Intersil Americas, Inc.
    Inventors: Katie H. Pentas, Mark D. Bordelon, Jack H. Linn
  • Patent number: 7220685
    Abstract: A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon from the codeposit to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced chemical vapor deposition. After codeposition, the codeposit is exposed to a selective silicon removal reagent that can preferentially remove the silicon in the codeposit, leaving behind a porous structure. Repeated execution of the codeposition and the selective silicon removal steps build up thickness of the porous film. A porous film with highly uniform small pores and a desired porosity profile can be obtained with this method. This method is advantageous for forming a broad range of low-k dielectrics for semiconductor integrated circuit fabrication. The general method is also advantageous for forming other porous films for other applications.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: May 22, 2007
    Inventors: Cecilia Y. Mak, Kam S. Law
  • Patent number: 7211524
    Abstract: The present invention relates to a method of forming an insulating film in a semiconductor device. After a mixed gas of alkyl silane gas and N2O gas is supplied into the deposition equipment, a radio frequency power including a short pulse wave for causing incomplete reaction upon a gas phase reaction is applied to generate nano particle. The nano particle is then reacted to oxygen radical to form the insulating film including a plurality of nano voids. A low-dielectric insulating film that can be applied to the nano technology even in the existing LECVD equipment is formed.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: May 1, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Choon Kun Ryu, Tae Kyung Kim
  • Patent number: 7211525
    Abstract: Methods of filling gaps on semiconductor substrates with dielectric film are described. The methods reduce or eliminate sidewall deposition and top-hat formation. The methods also reduce or eliminate the need for etch steps during dielectric film deposition. The methods include treating a semiconductor substrate with a hydrogen plasma before depositing dielectric film on the substrate. In some embodiments, the hydrogen treatment is used is conjunction with a high rate deposition process.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Sunil Shanker, Sean Cox, Chi-I Lang, Judy H. Huang, Minh Anh Nguyen, Ken Vo, Wenxian Zhu
  • Patent number: 7208426
    Abstract: A method and apparatus for preventing plasma induced damage resulting from high density plasma deposition processes. In the present embodiment, Un-doped Silica Glass(USG) is deposited so as to form a USG liner. In the present embodiment, the USG liner directly overlies a conductive interconnect structure that couples to semiconductor devices that are susceptible to plasma-induced damage during high density plasma deposition processes. A silicon-rich oxide is deposited in-situ immediately following the deposition of the USG liner so as to form a silicon-rich oxide liner that directly overlies the USG liner. The silicon-rich oxide liner protects the interconnect structure during the subsequent high density plasma deposition process, preventing damage resulting from plasma charge to the interconnect structure.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: April 24, 2007
    Assignee: Chartered Semiconductors Manufacturing Limited
    Inventors: Liu Huang, John Sodijono
  • Patent number: 7205249
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level from 10–250 W. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organosilane film is produced by reaction of methylsilane, CH3SiH3, or dimethylsilane, (CH3)2SiH2, and nitrous oxide, N2O, at an RF power level from about 10 to 200 W or a pulsed RF power level from about 20 to 250 W during 10–30% of the duty cycle.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: April 17, 2007
    Assignee: Applied Materials, Inc.
    Inventors: David Cheung, Wai-Fan Yau, Robert R. Mandal
  • Patent number: 7205248
    Abstract: Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the method, and devices and systems incorporating the oxide material are provided.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: April 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Weimin Li
  • Patent number: 7196020
    Abstract: A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under vacuum pressure while introducing a precursor gas, a reactant gas, and an ionization enhancer agent into the chamber. A plasma is generated from the gases within the chamber. The energy generating the plasma causes the formation of charged species. The resulting charged species of the ionization enhancer agent assists in the formation of chemically reactive species of at least the precursor.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: March 27, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sujit Sharan, Gurtej S. Sandhu
  • Patent number: 7196021
    Abstract: A method for forming a silicon oxide layer over a substrate disposed in a high density plasma substrate processing chamber. The method includes flowing a process gas that includes a silicon-containing source, an oxygen-containing source and a fluorine-containing source into the substrate processing chamber and forming a plasma from said process gas. The substrate is heated to a temperature above 450° C. during deposition of said silicon oxide layer and the deposited layer has a fluorine content of less than 1.0 atomic percent.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 27, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Zhengquan Tan, Dongqing Li, Walter Zygmunt
  • Patent number: 7195936
    Abstract: In a thin film processing method and system, a film thickness is regulated by using electron beams irradiated from a plurality of electron beam tubes onto a film of varying thickness formed on an object to be processed, wherein the output powers or beam irradiation times of the electron beam tubes are individually controlled according to a distribution of the thickness. In the method and system, electric charges charged in a film of an object to be processed can be removed also.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: March 27, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Tadashi Onishi, Manabu Hama, Minoru Honda, Kazuyuki Mitsuoka, Mitsuaki Iwashita
  • Patent number: 7186663
    Abstract: A method is provided for forming a Si and Si—Ge thin films. The method comprises: providing a low temperature substrate material of plastic or glass; supplying an atmosphere; performing a high-density (HD) plasma process, such as an HD PECVD process using an inductively coupled plasma (ICP) source; maintaining a substrate temperature of 400 degrees C., or less; and, forming a semiconductor layer overlying the substrate that is made from Si or Si-germanium. The HD PECVD process is capable of depositing Si at a rate of greater than 100 ? per minute. The substrate temperature can be as low as 50 degrees C. Microcrystalline Si, a-Si, or a polycrystalline Si layer can be formed over the substrate. Further, the deposited Si can be either intrinsic or doped. Typically, the supplied atmosphere includes Si and H. For example, an atmosphere can be supplied including SiH4 and H2, or comprising H2 and Silane with H2/Silane ratio in the range of 0–100.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: March 6, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, Apostolos T. Voutsas, John W. Hartzell
  • Patent number: 7183143
    Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 27, 2007
    Assignee: Macronix International Co., Ltd.
    Inventor: Tzu-Yu Wang
  • Patent number: 7179760
    Abstract: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: February 20, 2007
    Assignee: International Buisness Machines Corporation
    Inventors: Richard A. Conti, Thomas F. Houghton, Michael F. Lofaro, Jeffery B. Maxson, Ann H. McDonald, Yun-Yu Wang, Keith Kwong Hon Wong, Daewon Yang
  • Patent number: 7176130
    Abstract: A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer (20) is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer (22) is formed over the TEOS layer (20) and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer (20) before applying photoresist, pattern defects are reduced.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: February 13, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jin Miao Shen, Brian J. Fisher, Mark D. Hall, Kurt H. Junker, Vikas R. Sheth, Mehul D. Shroff
  • Patent number: 7166542
    Abstract: A method of fabricating a passivation layer is provided. A substrate with a plurality of device structures and at least an interconnect thereon is provided. A patterned metallic layer is formed over the interconnection layer. A plasma-enhanced chemical vapor deposition process is performed to form a first passivation over the metallic layer such that the processing pressure is higher (and/or the processing power is lower) than the pressure (the power) used in prior art. A moisture impermeable second passivation is formed over the first passivation layer. With the first passivation formed in a higher processing pressure (and/or lower processing power), damages to metallic layers or devices due to plasma bombardment is minimized.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: January 23, 2007
    Assignee: Nanya Technology Corporation
    Inventors: Ming-Hung Lo, Liang-Pin Chou, Chun-Ming Wang, Li-Fu Chen
  • Patent number: 7166185
    Abstract: The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: January 23, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Shigemi Murakawa, Toshikazu Kumai, Toshio Nakanishi
  • Patent number: 7163899
    Abstract: A densified dielectric film is formed on a substrate by a process that involves annealing a film deposited on the substrate by application of a localized energy pulse, such as a laser pulse, for example one of about 10 to 100 ns in duration from an excimer laser, that raises the temperature of the film above 1000° C. without raising the substrate temperature sufficiently to modify its properties (e.g., the substrate temperature remains below 550° C. or preferably in many applications below 400° C.). The dielectric deposition may be by any suitable process, for example CVD, SOG (spin-on glass), ALD, or catalyzed PDL. The resulting film is densified without detrimentally impacting underlying substrate layers. The invention enables dielectric gap fill and film densification at low temperature to the 45 nm technology node and beyond, while maintaining oxide film properties.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: January 16, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Seon-Mee Cho, George D. Papasouliotis
  • Patent number: 7157384
    Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: January 2, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Kang Sub Yim, Melissa M. Tam, Dian Sugiarto, Chi-I Lang, Peter Wai-Man Lee, Li-Qun Xia
  • Patent number: 7144606
    Abstract: The present invention generally provides improved adhesion and oxidation resistance of carbon-containing layers without the need for an additional deposited layer. In one aspect, the invention treats an exposed surface of carbon-containing material, such as silicon carbide, with an inert gas plasma, such as a helium (He), argon (Ar), or other inert gas plasma, or an oxygen-containing plasma such as a nitrous oxide (N2O) plasma. Other carbon-containing materials can include organic polymeric materials, amorphous carbon, amorphous fluorocarbon, carbon containing oxides, and other carbon-containing materials. The plasma treatment is preferably performed in situ following the deposition of the layer to be treated. Preferably, the processing chamber in which in situ deposition and plasma treatment occurs is configured to deliver the same or similar precursors for the carbon-containing layer(s). However, the layer(s) can be deposited with different precursors.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: December 5, 2006
    Assignee: Applied Materials, Inc.
    Inventor: Judy Huang
  • Patent number: 7144822
    Abstract: A method for plasma processing of semiconductor wafers is provided that reduces plasma-induced damage to the gate dielectric while limiting damage to the wafer from particulates that flake off of the interior surfaces of the reaction chamber. Plasma conditions are maintained in the reaction chamber while the wafer is transferred into the chamber and the plasma process is performed. After the plasma process, while still maintaining plasma conditions, the wafer is cooled to a removal temperature and removed from the reaction chamber.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: December 5, 2006
    Assignee: Novellus Systems, Inc.
    Inventor: Michael D. Kilgore
  • Patent number: 7129125
    Abstract: A semiconductor device comprises a semiconductor region including silicon, and an insulating film including silicon, oxygen, nitrogen, and helium, the dielectric film provided on the semiconductor region, and the dielectric film having a concentration distribution with respect to a film thickness direction, the concentration distribution having a maximal value of concentration of the helium in a surface portion on the semiconductor region side and a maximal value of concentration of the nitrogen in a surface portion on a side opposite to the semiconductor region.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: October 31, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Seiji Inumiya, Ichiro Mizushima
  • Patent number: 7122488
    Abstract: Methods are provided for forming silicon dioxide (SiO2) on a silicon carbide (SiC) substrate. The method comprises: providing a SiC substrate; supplying an atmosphere including oxygen; performing a high-density (HD) plasma-based process; and, forming a SiO2 layer overlying the SiC substrate. Typically, performing the HD plasma-based process includes connecting a top electrode to an inductively coupled HD plasma source. In one aspect, SiO2 is grown on the SiC substrate. Then, an HD plasma oxidation process is performed that creates a reactive oxygen species and breaks the Si—C bonds in the SiC substrate, to form free Si and C atoms in the SiC substrate. The free Si atoms in the SiC substrate are bonded to the HD plasma-generated reactive oxygen species, and the SiO2 layer is grown.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: October 17, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, Apostolos T. Voutsas, John W. Hartzell
  • Patent number: 7122487
    Abstract: A deposition oxide interface with improved oxygen bonding and a method for bonding oxygen in an oxide layer are provided. The method includes depositing an M oxide layer where M is a first element selected from a group including elements chemically defined as a solid and having an oxidation state in a range of +2 to +5, plasma oxidizing the M oxide layer at a temperature of less than 400° C. using a high density plasma source, and in response to plasma oxidizing the M oxide layer, improving M-oxygen bonding in the M oxide layer. The plasma oxidation process diffuses excited oxygen radicals into the oxide layer. The plasma oxidation is performed at specified parameters including temperature, power density, pressure, process gas composition, and process gas flow. In some aspects of the method, M is silicon, and the oxide interface is incorporated into a thin film transistor.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: October 17, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Pooran Chandra Joshi
  • Patent number: 7122485
    Abstract: Disclosed are methods for modifying the topography of HDP CVD films by modifying the composition of the reactive mixture. The methods allow for deposition profile control independent of film deposition rate. They rely on changes in the process chemistry of the HDP CVD system, rather than hardware modifications, to modify the local deposition rates on the wafer. The invention provides methods of modifying the film profile by altering the composition of the reactive gas mixture, in particular the hydrogen content. In this manner, deposition profile and wiw uniformity are decoupled from deposition rate, and can be controlled without hardware modifications.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: October 17, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: George D. Papasouliotis, Edith Goldner, Vishal Gauri, Md Sazzadur Rahman, Vikram Singh
  • Patent number: 7112352
    Abstract: A method and apparatus for depositing a uniform coating on a large area, planar surface using an array of multiple plasma sources and a common reactant gas injector. The apparatus includes at least one array of a plurality of plasma sources, wherein each of the plurality of plasma sources includes a cathode, an anode, and an inlet for a non-reactive plasma source gas disposed in a plasma chamber, and a common reactant gas injector disposed in a deposition chamber that contains the substrate. The common reactant gas injector provides a uniform flow of at least one reactant gas to each of the multiple plasmas generated the multiple plasma sources through a single delivery system. The at least one reactant gas reacts with the plurality of plasmas to form a uniform coating on a substrate.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: September 26, 2006
    Assignee: General Electric Company
    Inventor: Marc Schaepkens
  • Patent number: 7109083
    Abstract: A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: September 19, 2006
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa
  • Patent number: 7109132
    Abstract: High-density plasma CVD processes with improved gap filling characteristics are provided. In one exemplary process, the process includes loading a semiconductor substrate into a process chamber. First main process gases, including a silicon source gas, an oxygen gas, a nitrogen free chemical etching gas and a hydrogen gas, are then injected into the process chamber. Thus, a high-density plasma is generated over the semiconductor substrate, and the semiconductor substrate is heated to a temperature in the range of about 550° C. to about 700° C. by the high-density plasma. Thus, a silicon oxide layer is formed to completely fill a gap region without any voids or defects in the semiconductor substrate. In addition, the first main process gases can be replaced with second main process gases including a silicon source gas, an oxygen gas, a nitrogen free chemical etching gas, a hydrogen gas and a helium gas.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 19, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jai-Hyung Won, Young-Kyou Park
  • Patent number: 7101815
    Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is provided, comprising placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: September 5, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Ravi Iyer
  • Patent number: 7098087
    Abstract: It is an object of the present invention is to provide a technique for forming a dense insulating film of good quality that is applicable to a transistor made on a substrate weak against heat such as a glass and a semiconductor device that can realize high performance and high reliability using the technique. In the present invention a silicon oxide film is formed on a crystalline semiconductor film, which is formed on an insulating surface, by the sputtering method using silicon as a target by applying high-frequency power in an atmosphere containing oxygen or oxygen and a rare gas, a silicon nitride film is formed thereon by applying high-frequency power in an atmosphere containing nitrogen or nitrogen and a rare gas, and then, heat treatment of a stacked body of the crystalline semiconductor film, the silicon oxide film, and the silicon nitride film at a temperature higher than a temperature for forming the films is performed.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: August 29, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toru Takayama, Tetsuji Yamaguchi, Shunpei Yamazaki
  • Patent number: 7087537
    Abstract: A method for fabricating a thin film oxide is provided. The method includes: forming a substrate; treating the substrate at temperatures equal to and less than 360° C. using a high density (HD) plasma source; and forming an M oxide layer overlying the substrate where M is an element selected from a group including elements chemically defined as a solid and having an oxidation state in a range of +2 to +5. In some aspects, the method uses an inductively coupled plasma (ICP) source. In some aspects the ICP source is used to plasma oxidize the substrate. In other aspects, HD plasma enhanced chemical vapor deposition is used to deposit the M oxide layer on the substrate. In some aspects of the method, M is silicon and a silicon layer and an oxide layer are incorporated into a TFT.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: August 8, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, Apostolos T. Voutsas
  • Patent number: 7087525
    Abstract: The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the chamber. The mixture comprises a precursor of a desired material within a supercritical fluid. The precursor is relatively reactive under one set of conditions and is relatively non-reactive under another set of conditions. The precursor and supercritical fluid mixture is initially provided in the chamber under the conditions at which the precursor is relatively non-reactive. Subsequently, and while maintaining the supercritical state of the supercritical fluid, the conditions within the reaction chamber are changed to the conditions under which the precursor is relatively reactive. The precursor reacts to form the desired material, and at least some of the desired material forms a film on the substrate.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: August 8, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri
  • Patent number: 7074727
    Abstract: Low-k organosilicate dielectric material can be exposed to a series of reagents, including a halogenation reagent, an alkylation reagent, and a termination reagent, in order to reverse degradation of dielectric properties caused by previous processing steps.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: July 11, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Fu Hsu, Jyu-Horng Shieh, Yung-Cheng Lu, Hun-Jan Tao, Yuan-Hung Chiu