Abstract: A method for fabricating a substantially smooth-surfaced anti-reflective coating on a semiconductor device structure including generating a plasma from an inert gas in a process chamber in which the anti-reflective coating is to be deposited. The anti-reflective coating may include silicon, oxygen and nitrogen, and is preferably of the general formula SixOyNz, where x equals 0.40 to 0.65, y equals 0.02 to 0.56 and z equals 0.05 to 0.33. Preferably, x+y+z equals one. The method may also include fabricating a silicon nitride layer over the anti-reflective coating. A semiconductor device which includes a silicon nitride layer over the anti-reflective coating has a density of less than about 40,000 particles or surface roughness features in the silicon nitride of about 120-150 nanometers dimension per eight inch wafer. Accordingly, a mask that is subsequently formed over the silicon nitride layer has a substantially uniform thickness and is substantially distortion-free.

Abstract: A method for forming a ternary thin film using an atomic layer deposition process includes supplying a first and a second reactive material to a chamber containing a wafer, the first and second reactive materials being adsorbing on a surface of the wafer, supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, supplying a third reactive material to the chamber to cause a reaction between the first and second reactive materials and the third reactive material to form a thin film monolayer, supplying a second gas to purge the third reactive material that remains unreacted and a byproduct, and repeating the above steps for forming the thin film monolayer a predetermined number of times to form a ternary thin film having a predetermined thickness on the wafer. Preferably, the ternary thin film is a SiBN film.

Abstract: According to one aspect of the invention, a method is provided of processing a substrate, including locating the substrate in a processing chamber, creating a nitrogen plasma in the chamber, the plasma having an ion density of at least 1010 cm−3, and a potential of less than 20 V, and exposing a layer on the substrate to the plasma to incorporate nitrogen of the plasma into the layer.

Abstract: A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

Abstract: A method for forming a microelectronics device is disclosed. In one embodiment, the method includes depositing a conductive structure on a substrate. A first layer comprising silicon and nitrogen is formed on the substrate. A second layer comprising silicon and nitrogen is then formed on the first layer. The nitrogen to silicon ratio in the first layer is greater than the nitrogen to silicon ratio in the second layer.

Abstract: The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

Abstract: The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

Abstract: A method for forming a nitrided gate oxide over a silicon substrate in a semiconductor device fabrication process including providing a silicon semiconductor substrate; thermally growing a gate oxide layer including silicon dioxide over the silicon substrate; plasma treating the gate oxide layer including a plasma supplied with a plasma source gas including at least one of helium, hydrogen, deuterium, and oxygen; plasma nitriding the gate oxide layer according to a plasma treatment including a plasma supplied with a plasma source gas including nitrogen; and, thermally annealing the silicon semiconductor substrate including the gate oxide layer according to at least one annealing treatment.

Abstract: The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the material. The nitrogen is thermally annealed within the material to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the material. The invention also encompasses a method of forming a transistor device. A silicon-oxide-comprising layer is formed over a substrate. The silicon-oxide-comprising layer is exposed to nitrogen from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the layer. The nitrogen is thermally annealed within the layer to bond at least some of the nitrogen silicon proximate the nitrogen.

Abstract: A substrate support utilized in high-density plasma chemical vapor deposition (HDP-CVD) processing functions as a radio frequency (RF) electrode (e.g., a bias RF cathode). An upper surface of the substrate support has a central upper surface portion and a peripheral upper surface portion, with the peripheral upper surface portion recessed relative to the central upper surface portion. The upper surface of the support extends beyond an outer edge of the substrate when the substrate is positioned on the substrate support. This extension in the support upper surface may enhance process performance by reducing electric field edge effects, as well as by improving directional distribution of ions traveling to the substrate.

Abstract: The invention includes reactive gaseous deposition precursor feed apparatus and chemical vapor deposition methods. In one implementation, a reactive gaseous deposition precursor feed apparatus includes a gas passageway having an inlet and an outlet. A variable volume accumulator reservoir is joined in fluid communication with the gas passageway. In one implementation, a chemical vapor deposition method includes positioning a semiconductor substrate within a deposition chamber. A first deposition precursor is fed to an inlet of a variable volume accumulator reservoir. With the first deposition precursor therein, volume of the variable volume accumulator reservoir is decreased effective to expel first deposition precursor therefrom into the chamber under conditions effective to deposit a layer on the substrate.

Abstract: A method of film layer deposition is described. A film layer is deposited using a cyclical deposition process. The cyclical deposition process consists essentially of a continuous flow of one or more process gases and the alternate pulsing of a precursor and energy to form a film on a substrate structure.

Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.

Abstract: A method of forming a silicon nitride film includes a CVD process that uses an organic Si compound having an organic silazane bond as a gaseous source. The CVD process is conducted under a condition that the organic silazane bond in the organic Si source is preserved in the silicon nitride film.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.

Abstract: Within a damascene method for forming a microelectronic fabrication, there is employed an etch stop layer comprising a comparatively low dielectric constant dielectric material sub-layer having formed thereupon a comparatively high dielectric constant dielectric material sub-layer. Within the method there is also simultaneously etched: (1) an anti-reflective coating layer from an inter-metal dielectric layer; and (2) the etch stop layer from a contact region. The microelectronic fabrication is formed with enhanced performance and enhanced reliability.

Abstract: An improved photolithography technique is provided whereby the beneficial effects of using an anti-reflective coating may be realized while maintaining critical dimensions in each subsequent step. This improvement is realized by the treatment of the anti-reflective coating with a gaseous plasma or a solution of sulfuric acid and hydrogen peroxide. By treating the anti-reflective coating with gaseous plasma or solution of sulfuric acid and hydrogen peroxide, no “footing” results and the critical dimensions as set by the photoresist mask are preserved to provide an accurately patterned mask for subsequent steps.

Abstract: A plasma processing chamber having a chamber liner and a liner support, the liner support including a flexible wall configured to surround an external surface of the chamber liner, the flexible wall being spaced apart from the wall of the chamber liner. The apparatus can include a heater thermally connected to the liner support so as to thermally conduct heat from the liner support to the chamber liner. The liner support can be made from flexible aluminum material and the chamber liner comprises a ceramic material. The flexible wall can include slots which divide the liner support into a plurality of fingers which enable the flexible wall to absorb thermal stresses.

Abstract: A method and apparatus for modifying the profile of narrow, high-aspect-ratio gaps on a semiconductor substrate are used to fill the gaps in a void-free manner. Differential heating characteristics of a substrate in a high-density plasma chemical vapor deposition (HDP-CVD) system helps to prevent the gaps from being pinched off before they are filled. The power distribution between coils forming the plasma varies the angular dependence of the sputter etch component of the plasma, and thus may be used to modify the gap profile, independently or in conjunction with differential heating. A heat source may be applied to the backside of a substrate during the concurrent deposition/etch process to further enhance the profile modification characteristics of differential heating.

Abstract: Disclosed herein is a process for vapor phase growth of gallium nitride compound semiconductor which yields uniform crystal layers with good reproducibility. The process comprises forming a first nitride semiconductor layer on a substrate, forming thereon a protective film for crystal growth prevention in such a way that it has partly open window regions through which the first nitride semiconductor layer is exposed, forming a second nitride semiconductor layer by selective growth from the first nitride semiconductor layer at a crystal growth starting temperature, and continuing crystal growth at a temperature higher than the crystal growth starting temperature. The vapor phase growth at a low temperature yields a uniform crystal layer, and the ensuing vapor phase growth at a raised temperature yields a uniform crystal layer with good reproducibility in conformity with the first crystal layer.

Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

Abstract: A method for removing discoloration and corrosion of an exposed copper surface and for forming a nitride capping layer on top of the surface provides an in-situ process in which the reactive plasma ambient is constantly maintained during a transition from the surface treatment step to the deposition step for forming the nitride capping layer. Permanently maintained plasma avoids an renewed formation of discoloration on the cleaned copper surface during the transition to the deposition step and at the beginning of the deposition step when silane gas is introduced into the plasma ambient. Moreover, the overall process time is significantly reduced.

Abstract: Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.

Abstract: A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

Abstract: A method of filling gaps on a semiconductor wafer with a dielectric material employs a plasma enhanced chemical vapor deposition (PECVD) process with a temperature in the range of 500 to 700° C. As a result of the deposition process, gaps resulting from e.g. shallow trench isolation or premetal dielectric techniques are filled homogeneously without any voids. The deposition may be improved by applying two radio frequency signals with different frequencies.

Abstract: A method of fabricating a void-free barrier layer located on a semiconductor substrate. First, conductive structures are defined on the semiconductor substrate. Second, a barrier layer is deposited over the conductive structures, wherein the barrier layer has a void between the conductive structures. Third, argon gas is introduced into a HDPCVD chamber to sputter the barrier layer so that the void is eliminated.

Abstract: A method for depositing an inter-metal-dielectric layer on a semiconductor substrate by plasma chemical vapor deposition without the layer cracking defect is disclosed. The semiconductor substrate is first heat-treated in the same plasma process chamber to a temperature of at least 300° C. for a length of time sufficient to outgas a surface of the semiconductor substrate. The impurity gases absorbed on the surface of the semiconductor substrate can be effectively outgassed during the heat treatment process such that they are not trapped under an IMD layer deposited in a subsequent plasma deposition process. The method effectively minimizes or eliminates completely the IMD layer cracking defect of the dielectric layer.

Abstract: A method for passivating at least interfaces between structures formed from a material including silicon and adjacent dielectric structures so as to reduce a concentration of dangling silicon bonds at these interfaces and to reduce or eliminate the occurrence of unwanted voltage changes across the dielectric structures. The method includes disassociating ammonia so as to expose at least the interfaces to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen-passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include a silicon nitride, substantially prevents the hydrogen species from escaping therethrough as processes that require temperatures of at least about 400° C. or of at least about 600° C. are conducted.

Abstract: Disclosed is a method of protecting semiconductor areas while exposing a structures for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma film of a silicon compound, selected from the group silicon oxide and silicon nitride, depositing a planarized polymer film to a thickness effective in protecting said high density plasma film while leaving high density plasma excess exposed, and etching away said high density plasma excess.

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

Abstract: A method of manufacturing a semiconductor device is provided. The method comprises the steps of forming an insulating interlayer film on a substrate, forming a Cu interconnection pattern in the insulating interlayer film, forming a first insulating film on the insulating interlayer film at a first temperature lower than 400° C. in a nonoxide situation so that the first insulating film covers the Cu interconnection pattern, and forming a second insulating film on the first insulating film at a second temperature higher than the first temperature.

Abstract: A silicon based PT/PZT/PT sandwich structure is disclosed. A dielectric layer is formed over a semiconductor substrate. The dielectric layer preferably comprises a silicon dioxide layer. A first and the second conductive films are sequentially formed over the dielectric layer. A first ferroelectric film is formed over the first and second conductive films. A second ferroelectric film is formed over the first ferroelectric film. A third ferroelectric film is formed over the second ferroelectric film. The resulting structure is annealed. A third and fourth conductive films are sequentially formed over the third ferroelectric layer. The third and fourth conductive films are patterned.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of SiH4 and then initiating deposition of a silicon nitride capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, ramping up the introduction of SiH4 in two stages, and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure, N2 flow rate and NH3 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.

Abstract: A processing chamber of a plasma CVD device comprises a lower electrode for placing a semiconductor substrate thereon and an upper electrode provided at a position facing the lower electrode and provided with a concave portion on a surface thereof facing a surface of the lower electrode on which the substrate is placed. In deposition process using such a processing chamber, a contaminant removal sequence is provided between a deposition processing step and an exhausting step. During the deposition process, reactive gases SiH4 and NH3 for forming a Si3N4 film are supplied together with an inert gas N2 into the processing chamber. High-frequency electric power is applied between the electrodes to discharge the reactive gases so as to form the Si3N4 film on the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer; decreasing the hydrophilic properties of a first portion of the dielectric layer, forming an opening through the dielectric layer, and filling the opening with metal to form a first metal feature. The hydrophilic properties of the first portion are lesser than a second portion of the dielectric layer. The hydrophilic properties of the first portion can be decreased by doping the first portion with hydrogen using ion implantation or plasma etching. An upper surface of the dielectric layer can also be roughened during the process of hydrogen doping. A semiconductor device produced by the method of manufacturing is also disclosed.

Abstract: The present invention provides an apparatus for depositing a film on a substrate comprising a processing chamber, a substrate support member disposed within the chamber, a first gas inlet, a second gas inlet, a plasma generator and a gas exhaust. The first gas inlet provides a first gas at a first distance from an interior surface of the chamber, and the second gas inlet provides a second gas at a second distance that is closer than the first distance from the interior surface of the chamber. Thus, the second gas creates a higher partial pressure adjacent the interior surface of the chamber to significantly reduce deposition from the first gas onto the interior surface.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is formed over the semiconductor substrate has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing lines the opening, and a copper or copper alloy conductor core fills the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. and above 3000 watts source power to reduce the residual oxide on the conductor core material. A silicon nitride capping layer is deposited by high density plasma (HDP) deposition with the source power between 2250 and 2750 watts and the bias power between 1800 and 2200 watts to suppress the formation of hillocks.

Abstract: A thin film transistor and a liquid crystal display panel are provided. These devices include a layer of ammonia-free silicon nitride formed between the gate and the gate insulator of the device.

Abstract: A new method is provided for treating the surface of a layer of passivation where this layer of passivation comprises silicon dioxide or silicon nitride. An oxygen rich layer is created over the surface of the layer of passivation. Under the first embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of plasma enhanced silicon nitride is deposited over the surface of the layer of silicon oxide, and a layer of oxynitride is deposited over the surface of the layer of plasma enhanced silicon nitride. Under the second embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of silicon nitride is deposited over the surface of layer of silicon oxide. The surface of the layer of silicon nitride is oxidized by N2O or O2 plasma treatment.

Abstract: The process comprises the following steps: a) pretreatment of a surface of the substrate by means of a cold gas plasma at low or medium pressure in order to clean the said surface; b) growth, from the said cleaned surface of the substrate, of a nitride barrier layer by means of a cold gas plasma made up of an N2/H2 mixture at low or medium pressure; and c) deposition, on the nitride barrier layer, of a Ta2O5 dielectric layer by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).

Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions herein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.

Abstract: An apparatus and method for reducing the production of white powder in a process chamber used for depositing silicon nitride. Steps of the method include heating at least a portion of a wall of the process chamber; providing a liner covering a substantial portion of a wall of the process chamber; providing a remote chamber connected to the interior of the process chamber; causing a plasma of cleaning gas in the remote chamber; and flowing a portion of the plasma of cleaning gas into the process chamber.

Abstract: An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).

Abstract: The oxynitride or oxide layer formed on a semiconductor substrate is pre-treated with UV-excited gas (such as chlorine or nitrogen) to improve the layer surface condition and increase the density of nucleation sites for subsequent silicon nitride deposition. The pre-treatment is shown to reduce the root mean square surface roughness of thinner silicon nitride films (with physical thicknesses below 36 Å, or even below 20 Å that are deposited on the oxynitride layer by chemical vapor deposition (CVD).

Abstract: The present invention has a processing zone having a coating unit for forming a coating film on a substrate, a developing unit for performing development of the substrate, a heat treatment unit for performing heat treatment of the substrate, and a first transfer device for transferring the substrate from/to the coating unit, the developing unit and the heat treatment unit, an interface section in which the substrate is transferred at least on a path between the processing zone and an exposure processing unit outside the system for performing exposure processing for the substrate, a casing for housing the processing zone and the interface section, a gas supply device for supplying an inert gas into the interface section, and an exhaust portion through which an atmosphere in the interface section is discharged, and the heat treatment unit, and a second transfer device for transferring the substrate on a path between the heat treatment unit and the exposure processing unit are disposed in the interface section.

Abstract: A method and apparatus for reducing fluorine and other sorbable contaminants in plasma reactor used in chemical vapor deposition process such as the deposition of silicon oxide layer by the reaction of TEOS and oxygen. According to the method of the present invention, plasma of an inert gas is maintained in plasma reactor following chamber clean to remove sorbable contaminants such as fluorine. The plasma clean is typically followed by seasoning of the reactor to block or retard remaining contaminants. According to one embodiment of the invention, the combination of chamber clean, plasma clean, and season film is conducted before PECVD oxide layer is deposited on wafer positioned in the plasma reactor.

Abstract: A method and apparatus for reducing plasma-induced charging damage in a semiconducting device are provided. The method includes exposing an article having a dielectric material susceptible to plasma-induced charging, to vacuum-ultraviolet (VUV) radiation of an energy greater than the bandgap energy of the dielectric material during or after plasma processing of the device. The plasma-induced charge is conducted from, or recombined at, the charging site.

Abstract: A method for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride and structures produced by the method. A thin film transistor for use in a liquid crystal display and a method of constructing the same, wherein the transistor has a gate, a source and a drain, and a gate insulator between the gate and an active silicon layer. The improvement is a layer of the ammonia-free silicon nitride deposited between the copper,aluminum, or other refractory metal gate and the gate insulator. Further,. the gate is copper, aluminum, or another refractory metal and is deposited directly on the substrate. The layer of ammonia-free silicon nitride is also deposited on portions of the substrate adjacent the gate and the gate line extending therefrom. The layer is made in a plasma-enhanced chemical vapor deposition process wherein the gas mixture comprises one part silane to 135 parts nitrogen to 100 parts helium and 100 parts hydrogen.

Abstract: A method for producing a plasma silicon nitride series film with a small heat load having a low hydrogen concentration is provided. The method is for producing a silicon nitride series film on a material to be treated using a plasma CVD apparatus having a reaction chamber evacuated to vacuum. The method comprises the steps of introducing a monosilane gas (SiH4) and a nitrogen gas (N2) as raw material gases into the reaction chamber at prescribed flow rates, and heating the material to be treated to a prescribed temperature. At this time, it is characterized in that the flow rate of the nitrogen gas is at least 100 times the flow rate of the monosilane gas.