Abstract: The invention relates to a method for fabricating a microtechnical structure (28) having a depression (25), which has a high aspect ratio. In order to achieve a good filling behavior, it is proposed to increase the quantity of the passivating particles which are present in the reactor and passivate the surface of the structure (28) against further addition of the filling material (30). With suitable process control, the additional passivation has an effect essentially only on the side walls (27) of the depression (25).

Abstract: A chemical mechanical polishing slurry and method for using the slurry for polishing copper, barrier material and dielectric material that comprises a first and second slurry. The first slurry has a high removal rate on copper and a low removal rate on barrier material. The second slurry has a high removal rate on barrier material and a low removal rate on copper and dielectric material. The first and second slurries at least comprise silica particles, an oxidizing agent, a corrosion inhibitor, and a cleaning agent.

Abstract: In a method of manufacturing a transistor, a gate conductor is defined over an insulating substrate. A gate insulator layer is formed over the gate conductor. A first microcrystalline silicon layer is deposited over the gate insulator layer and is exposed to nitrogen plasma, thereby forming silicon nitride and substantially maintaining the crystalline structure. Successive layers are similarly deposited and then exposed to nitrogen plasma, forming multiple microcrystalline silicon layers. A further microcrystalline silicon layer is formed over the exposed layers, defining the semiconductor body of the transistor. A source and drain structure are defined over the transistor body.

Abstract: Silicon oxynitride layers are deposited by plasma enhanced chemical vapor deposition with significantly reduced defects, such as nodules, employing a ramp down step at the end of the deposition cycle. Embodiments include depositing a SION ARC at a first power, discontinuing the flow of SiH4 and ramping down to a second power while continuing the flow of N2O and N2, and ramping down to a third power while continuing the flow of N20 and N2 before pumping down. The resulting relatively defect free silicon oxynitride layers can be advantageously employed as an ARC, particularly when patterning contact holes in manufacturing flash memory devices.

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

Abstract: In an atmosphere of processing gas, on a wafer W consisting mainly of silicon, through a planar-array antenna RLSA 60 having a plurality of slits, microwaves are irradiated to generate plasma containing oxygen, or nitrogen, or oxygen and nitrogen and to implement therewith on the surface of the wafer W direct oxidizing, nitriding, or oxy-nitriding to deposit an insulator film 2 of a thickness of 1 nm or less in terms of oxide film. A manufacturing method and apparatus of semiconductors that can successfully regulate film quality of the interface between a silicon substrate and a SiN film and can form SiN film of high quality in a short time can be obtained.

Abstract: A method of depositing a film, such as a barrier layer, on a substrate using a gaseous mixture including a hydrocarbon-containing gas and a silicon-containing gas. Suitable hydrocarbon-containing gases include alkanes such as methane (CH4), ethane (C2H6), butane (C3H8), propane (C4H10), etc. Suitable silicon-containing gases include silanes such as monosilane (SiH4). The method generally comprises providing a suitable gaseous mixture to the chamber, generating a plasma from the gaseous mixture, and depositing a film onto the substrate using the plasma. In a preferred embodiment, the film is deposited in a high-density plasma chemical vapor deposition (HDP-CVD) system. The gaseous mixture typically includes a silicon containing gas, such as an alkane, and a hydrocarbon containing gas, such as a silane. Embodiments of the method of the present invention can integrated stack structures having overall dielectric constant of about 4.0 or less.

Abstract: A method of manufacturing a thin film transistor, includes preparing a process chamber having a stage, providing a substrate on the stage of the process chamber, injecting a first mixed gas of NH3, N2 and SiH4 into the process chamber, forming a plasma in the process chamber and forming a silicon nitride film (SiNx) on the substrate, injecting a second mixed gas of H2 and SiH4 into the process chamber while removing the first mixed gas in the plasma state, forming a pure amorphous silicon film (a-Si:H) on the silicon nitride film using the second mixed gas, injecting a third mixed gas of H2, SiH4 and PH3 into the process chamber while removing the second mixed gas in the plasma state, and forming a doped amorphous silicon film (n+ a-Si:H) on the silicon nitride film using the second mixed gas.

Abstract: A method of polishing a wafer in a carrier by a polishing pad, controlling a ratio of platen speed to carrier speed (PS to CS) within a specific range, or controlling a first polishing step with a PS to CS ratio in the range of about 150:1 to about 1:150 followed by a second polishing step with a platen speed of about 0 to 20 rpm while maintaining the carrier speed used in the first polishing step, which maximizes clearing of residual material removed from a patterned wafer surface by polishing.

Abstract: Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.

Abstract: In a film structure comprising a ferroelectric thin film formed on a substrate, the ferroelectric thin film contains a rare earth element (Rn), Pb, Ti, and O in an atomic ratio in the range: 0.8≦(Pb+Rn)/Ti≦1.3 and 0.5≦Pb/(Pb+Rn)≦0.99, has a perovskite type crystal structure, and is of (001) unidirectional orientation or a mixture of (001) orientation and (100) orientation. The ferroelectric thin film can be formed on a silicon (100) substrate, typically by evaporating lead oxide and TiOx in a vacuum chamber while introducing an oxidizing gas therein.

Abstract: An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

Abstract: Multiple sequential processes are conducted in situ in a single-wafer processing chamber, particularly for forming ultrathin dielectric stacks of high quality. The chamber exhibits single-pass, laminar gas flow, facilitating safe and clean sequential processing. Furthermore, a remote plasma source widens process windows, permitting isothermal sequential processing and thereby reducing the transition time for temperature ramping between in situ steps. In exemplary processes, extremely thin interfacial silicon oxide, nitride and/or oxynitride is grown, followed by in situ silicon nitride deposition. Cleaning, anneal and electrode deposition can also be conducted in situ, reducing transition time without commensurate loss in reaction rates.

Abstract: A deposition method for filling recesses in a substrate is described. In the method, the substrate is exposed to an energized deposition gas comprising first and second components, to deposit a first layer of a material in the recess, and thereafter, the ratio of the first component to the second component is reduced, to deposit a second layer of the material over the first layer in the recess. The deposition method may be used to fill recesses in a substrate and smoothen out reentrant cavities in a silicon nitride liner, in the fabrication of polysilicon gates in a substrate.

Abstract: A method of manufacturing a semiconductor device includes the step of forming a MOS transistor structure on a semiconductor substrate, the MOS transistor structure having an insulated gate electrode. The method further includes the step of depositing a silicon nitride film covering the insulated gate electrode over the semiconductor substrate by single wafer processing type thermal CVD at a substrate temperature of 500° to 800° C.

Abstract: A wafer surface is irradiated with ultraviolet rays which has a central wavelength of 172 nm and which is emitted from an excimer lamp so that organic contaminations such as photo resist residues and so on are oxidized and removed from the wafer surface. Thus, cleaning of the wafer surface is carried out.

Abstract: A method of forming a silicon nitride layer in a semiconductor device manufacturing process. The silicon nitride layer (SixNyHz) is formed by PE-CVD technique at low temperature to have at most 0.35 hydrogen composition. The resulting silicon nitride layer has substantially no Si—H bonding as compared with a silicon nitride layer formed at high temperature, thereby reducing thermal stress variation during annealing. The resulting silicon nitride layer exhibits reduced thermal stress variation before and after deposition, preventing a popping phenomenon and reducing the stress applied to the underlying layer.

Abstract: Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

Abstract: In the fabrication of EDRAM/SDRAM silicon chips with ground rules beyond 0.18 microns, a Si3N4 barrier layer is deposited onto the patterned structure during the borderless polysilicon contact fabrication. It is required that this layer be conformal and has a high hydrogen atom content to prevent junction leakage. These objectives are met with the method of the present invention. In a first embodiment, the Si3N4 layer is deposited in a Rapid Thermal Chemical Vapor Deposition (RTCVD) reactor using a NH3/SiH4 chemistry at a temperature and a pressure in the 600-950° C. and 50-200 Torr ranges respectively. In a second embodiment, it is deposited in a Low Pressure Chemical Vapor Deposition (LPCVD) furnace using a NH3/SiH2Cl2 chemistry (preferred ratio 1:1) at a temperature and a pressure in the 640-700° C. and 0.2-0.8 Torr ranges respectively.

Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions therein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.

Abstract: The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed surface. The film can be supported by a semiconductor substrate. When the film is moved to a processing position, a focused source of radiation is created by a beam source. The exposed surface of the film is then irradiated by the beam source at the processing position until a predetermined dielectric constant is achieved. The film or beam source may be rotated, inclined, and/or moved between a variety of positions to ensure that the exposed surface of the film is irradiated evenly.

Abstract: Thin semiconductor films or layers having a pre-selected degree of crystallinity, from amorphous material to poly-crystalline material, can be obtained by selecting an appropriate aspect ratio for a collimator used during a sputtering process. The orientation of the deposited film also can be tailored by selection of the collimator aspect ratio. Sputtered collimation permits highly crystalline films to be formed at temperatures significantly below the annealing temperature of the sputtered material. Thus, required fabrication steps and increase the throughput of the use of low temperatures allows films of substantially greater crystallinity and carrier mobility to be fabricated on glass and other low temperature substrates. Additionally, thin semiconductor Trapped charge defects also can be reduced by grounding the collimator to provide electrical isolation between the charged plasma particles and the substrate on which the sputtered layer is to be formed.

Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate. A semiconductor film pattern is formed on the insulating film. A direct thermal nitriding method is performed to at least a portion of the semiconductor film pattern. The direct thermal nitriding method is performed by lamp annealing in a gas composed of nitrogen such that a thermally nitrided film has a film thickness of equal to or thicker than 1.5 nm. Thus, invasion of a hydrogen atom or ion into the semiconductor film pattern can be prevented.

Abstract: A plasma processing apparatus processes high-speed semiconductor circuits by using plasma with an increased yield. The plasma processing apparatus has a vacuum vessel including an exhaust device, a starting material gas supplying device, an electrode for installing a workpiece (wafer) and a device for applying radio frequency power to the wafer. This apparatus converts the starting material gas to plasma inside the vacuum vessel and plasma-processes a wafer surface, wherein an insulating film is interposed between the electrode for installing the wafer and the wafer and has a conductive material at a part thereof, and the conductive material is electrically grounded through an impedance regulating circuit.

Abstract: A silicon nitride deposition method includes providing a substrate surface. Silicon is predeposited on at least a portion of the surface. After predeposition of the silicon, silicon nitride is deposited. The substrate surface may include one or more component surfaces and when at least a monolayer of silicon is predeposited thereon silicon nitride nucleation at the substrate surface is performed at a substantially equivalent rate independent of the different component surfaces.

Abstract: This invention discloses a planarization method for semiconductor device. The planarization method includes the steps of: providing a semiconductor substrate in which metal patterns are formed with various pattern densities; depositing a porous oxide layer over the semiconductor substrate so as to cover the metal patterns; plasma-treating surface of the porous oxide layer; and polishing the plasma-treated porous oxide layer by chemical mechanical polishing.

Abstract: A method for forming an isolation layer in a semiconductor device, to avoid the occurrence of an angular formation phenomenon at the edge portions of the upper and lower portions of the trench during formation of a shallow trench isolation layer (STI), so that malfunction of the device and the deterioration of its performance due to a parasitic transistor and leakage current, can be prevented. Advantageously, silicon nitride films are formed at the side wall of the pad oxide film and the surface of trench silicon through a nitrogen (N+) plasma nitrification process, after a trench etching process, for formation of STI, so that the generation of a moat is inhibited and deterioration of the device is prevented.

Abstract: A showerhead diffuser apparatus for a CVD process has a first channel region having first plural independent radially-concentric channels and individual gas supply ports from a first side of the apparatus to individual ones of the first channels, a second channel region having second plural independent radially-concentric channels and a pattern of diffusion passages from the second channels to a second side of the apparatus, and a transition region between the first channel region and the second channel region having at least one transition gas passage for communicating gas from each first channel in the first region to a corresponding second channel in the second region. The showerhead apparatus has a vacuum seal interface for mounting the showerhead apparatus to a CVD reactor chamber such that the first side and supply ports face away from the reactor chamber and the second side and the patterns of diffusion passages from the second channels open into the reactor chamber.

Abstract: An apparatus for forming a high dielectric oxide film includes a controllable atomic oxygen source and a vaporized precursor source. A deposition chamber for receiving the atomic oxygen from the atomic oxygen source and vaporized precursor from the vaporized precursor source is used for deposition of the high dielectric oxide film on a surface of a structure located therein. The apparatus further includes a detection mechanism for detecting a characteristic of the deposition of the high dielectric oxide film on the surface of the structure. The controllable atomic oxygen source is controlled as a function of the detected characteristic.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate.

Abstract: A half tone phase shift mask material, suitable for use at 193 nm is disclosed. It comprises a layer of nitrogen rich silicon nitride that was formed by subjecting a mixture of a nitrogen bearing gas, such as nitrogen and/or ammonia, with a silicon bearing gas, such as silane, to a plasma discharge. Provided the ratio of the nitrogen bearing to the silicon bearing gases is about 10 to 1, films having the required optical properties at 193 nm are formed. These properties are a reflectance that is less than 15% and a transmittance that is between 4 and 15%. Related optical properties, namely an extinction coefficient of about 0.4 and a refractive index of about 2.5, are also closely approached. Additionally, the films are stable under prolonged UV exposure and exhibit good etch behavior.

Abstract: A method and apparatus for reducing plasma-induced charging damage in a semiconducting device are provided. The method includes exposing an article having a dielectric material susceptible to plasma-induced charging, to vacuum-ultraviolet (VUV) radiation of an energy greater than the bandgap energy of the dielectric material during or after plasma processing of the device. The plasma-induced charge is conducted from, or recombined at, the charging site.

Abstract: A method to deposit insulating, semiconducting, and conducting films at pressures close to the atmospheric pressure and at temperatures less than 500° C. is provided. In this method, noble gas is mixed with reactant gas, and electric energy is applied to produce plasma at pressure substantially close to atmospheric pressure. The process can be applied to deposit films such as silicon dioxide, silicon nitride, silicon, and metal films.

Abstract: The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed surface. The film can be supported by a semiconductor substrate. When the film is moved to a processing position, a focused source of radiation is created by a beam source. The exposed surface of the film is then irradiated by the beam source at the processing position until a predetermined dielectric constant is achieved. The film or beam source may be rotated, inclined, and/or moved between a variety of positions to ensure that the exposed surface of the film is irradiated evenly.

Abstract: A process for preparing a semiconductor device includes a step of surface-modifying a desired portion of the surface of a substrate carried out in an atmosphere containing oxygen or nitrogen atoms. The process also includes a step of depositing selectively a metal on an electron-donative surface provided corresponding to the desired portion.

Abstract: A method of depositing an interlevel dielectric material on a semiconductor wafer at a selected thickness such that the best global planarity of the dielectric layer is achieved. A model for the deposition of a silicon dioxide layer is developed based upon the physics of deposition and sputtering and based upon the minimum geometry of features in the semiconductor device. First the geometric parameters of the metal features are determined. Then, based upon the most aggressive aspect ratio between metal lines, the deposition rate to sputter rate ratio is calculated. The film thickness for optimum global planarity is determined based on the calculated ratio. The dielectric material is then deposited on the metal features using HDP-CVD techniques in a manner using the calculated ratio to stop deposition at the determined film thickness such that the optimum thickness for global planarity is achieved.

Abstract: A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.

Abstract: The present invention relates to a method of processing a semiconductor device and comprising the following steps of generating plasma in a processing chamber to form a thin film on a semiconductor device or to process a thin film formed on a semiconductor device, scanning a laser beam which intensity is modulated at a desired frequency inside the processing chamber where the semiconductor device is being processed by the plasma through a window. Receiving by a sensor through the window a back scattered light being scattered from fine particles suspended in said processing chamber by scanning the laser, detecting said desired frequency component from a signal outputted from the sensor, obtaining information from the detected desired frequency component relating to quantity, size and distribution of fine particles illuminated by said laser beam inside the processing chamber, and outputting said obtained information relating to quantity, size and distribution of the fine particles.

Abstract: An improved method for forming inter-metal dielectrics (IMD) over a semiconductor substrate is provided, wherein a conductive line is formed thereon. A first dielectric layer is formed over the conductive line. A second dielectric layer is formed on the first dielectric layer by a spin-on glass method. A curing treatment with an electron beam having a low energy and a high dosage is performed to cure an upper portion of the second dielectric layer so that a cured third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the cured third dielectric layer. A chemical-mechanical polishing process is performed using the cured dielectric layer as a stop layer. A cap layer is formed on the fourth dielectric layer.

Abstract: Disclosed is a method of manufacturing a semiconductor device, including the step of supplying an oxidizing gas and a nitriding gas onto one main surface of a semiconductor substrate while heating the substrate so as to oxynitride the surface region of the substrate, wherein the supplying step is performed such that the gaseous phase above the main surface of the substrate forms a first region having a substantially uniform temperature in a direction perpendicular to the main surface of the substrate and a second region interposed between the first region and the substrate and having a temperature gradient in a direction perpendicular to the main surface of the substrate such that the temperature is elevated toward the substrate, and the distance from the main surface of the substrate to the interface between the first and second regions is set at 9.5 cm or less.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The present invention is directed to a method of forming process layers comprised of silicon nitride. In one embodiment, the method comprises forming a silicon nitride layer using silane volumes ranging from approximately 350-390 standard cubic centimeters.

Abstract: Plasma enhanced chemical vapor deposition (PECVD) reactors and methods of effecting the same are described. In accordance with a preferred implementation, a reaction chamber includes first and second electrodes operably associated therewith. A single RF power generator is connected to an RF power splitter which splits the RF power and applies the split power to both the first and second electrodes. Preferably, power which is applied to both electrodes is in accordance with a power ratio as between electrodes which is other than a 1:1 ratio. In accordance with one preferred aspect, the reaction chamber comprises part of a parallel plate PECVD system. In accordance with another preferred aspect, the reaction chamber comprises part of an inductive coil PECVD system. The power ratio is preferably adjustable and can be varied. One manner of effecting a power ratio adjustment is to vary respective electrode surface areas.

Abstract: A process for very low deposition rate plasma-enhanced chemical vapor deposition (PECVD) of nitride is provided. A nitride layer is used, for example, as a precursor for nitride spacers formed on the sidewalls of a polysilicon gate. The nitride layer may be produced in a PECVD chamber, using an increased flow rate of nitrogen applied to the chamber, an increased flow rate of molecular nitrogen, and a reduced flow rate of ammonia. The RF power is reduced, as well as the reactor pressure. This produces a nitride layer that exhibits improvements in density, refractive index, step coverage, and thickness non-unformity within a wafer and from wafer-to-wafer.

Abstract: A process of plasma-enhanced chemical vapor deposition of silicon oxynitride from a gas mixture of nitrous oxide and a silicon-containing gas employs a dual-power source of plasma generation and sustenance, to produce optimum properties of the deposited layer, for the purposes of passivation of the semiconductor surface, minimization of trapped energetic electrons, and protection of the integrated circuit device from moisture and other potentially deleterious effects.

Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, O—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.

Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480° C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.

Abstract: To provide a fabrication method of compound semiconductor devices which can improve the problems of conventional MESFETs, such as the breakdown voltage degradation owing to increase of the gate leak current or the electron traps in the passivation film, the drain current decrease because of the gate-lag, or the threshold voltage dispersion caused by the interfacial tension, and easily restrain the emitter-size effect of conventional mesa type HBT without revising or complicating its epitaxial layer structure, a fabrication method according to the invention of a semiconductor device having a high-resistance film (9) covering a part of a surface other than electrodes (5, 6, and 7) of the semiconductor device comprises a step of depositing the high-resistance film (9) by way of catalytic CVD.

Abstract: A method of reducing a chemical mechanical polishing (CMP) dishing effect. A plurality of trenches are formed in the substrate, while a first insulating layer, such as silicon oxide layer is formed on the substrate to fill those trenches. A chemical reaction, such as nitridation reaction, is performed on the surface of the insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.