Utilizing Electromagnetic Or Wave Energy (e.g., Photo-induced Deposition, Plasma, Etc.) Patents (Class 438/792)
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Patent number: 6933250Abstract: A process of manufacturing a semiconductor device uses catalytic chemical vapor deposition. In the process, a reaction chamber containing a catalyzer and a substrate has gasses, including silane, ammonia, and hydrogen supplied to the reaction chamber. The gases are brought into contact with the catalyzer and then with the substrate to deposit a silicon nitride film.Type: GrantFiled: October 21, 2002Date of Patent: August 23, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masahiro Totsuka, Tomoki Oku, Ryo Hattori
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Patent number: 6933245Abstract: A method of forming a thin film with a low hydrogen contents is provided by positioning a substrate inside a processing chamber, and supplying reacting materials into the chamber, chemisorbing a portion of the reacting materials onto the substrate. Then, a nitrogen (N2) remote plasma treatment is performed to reduce the hydrogen content of thin film layer formed by chemisorption of the reacting materials on the substrate. Accordingly, a thin film is formed having a low hydrogen content, since the hydrogen bonds in the thin film layer formed by chemisorption of the reacting materials are removed.Type: GrantFiled: March 31, 2003Date of Patent: August 23, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Hwan Lee, Jong-Ho Yang
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Patent number: 6933248Abstract: The instant invention describes a method for forming a dielectric film with a uniform concentration of nitrogen. The films are formed by first incorporating nitrogen into a dielectric film using RPNO. The films are then annealed in N2O which redistributes the incorporated species to produce a uniform nitrogen concentration.Type: GrantFiled: September 28, 2001Date of Patent: August 23, 2005Assignee: Texas Instruments IncorporatedInventor: Douglas T. Grider
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Patent number: 6929831Abstract: A silicon nitride film, for example, is deposited by introducing into a plasma region of a chamber a silicon containing gas, molecular nitrogen and sufficient hydrogen to dissociate the nitrogen to allow the silicon and nitrogen to react to form a silicon nitride film on a surface adjacent the plasma region. The thus deposited film may then be subjected to an activation anneal.Type: GrantFiled: September 13, 2002Date of Patent: August 16, 2005Assignee: Trikon Holdings LimitedInventors: Jashu Patel, Knut Beekman
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Patent number: 6924241Abstract: A method for producing an ultraviolet light (UV) transmissive silicon nitride layer in a plasma enhanced chemical vapor deposition (PECVD) reactor is presented. The UV transmissive film is produced by reducing, in comparison to a standard silicon nitride process, a flow rate of the silane and ammonia gas precursors to the PECVD reactor, and significantly increasing a flow rate of nitrogen gas to the reactor. The process reduces the concentration of Si—H bonds in the silicon nitride film to provide UV transmissivity. Further, the amount of nitrogen in the film is greater than in a standard PECVD silicon nitride film, and as a percentage constitutes a greater part of the film than silicon. The film has excellent step coverage and a low number of pinhole defects. The film may be used as a passivation layer in a UV erasable memory integrated circuit.Type: GrantFiled: February 24, 2003Date of Patent: August 2, 2005Assignee: ProMOS Technologies, Inc.Inventor: Tai-Peng Lee
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Patent number: 6924229Abstract: A method for forming a semiconductor device having improved characteristics and reliability by forming a hard mask layer on a bit line to prevent degradation of characteristics of the device in a self-alignment contact process of a storage electrode is disclosed. The hard mask layer utilizes over-hang formed at the upper portion of the bit line so as to provide sufficient protection for the bit line in the subsequent etching processes.Type: GrantFiled: June 30, 2003Date of Patent: August 2, 2005Assignee: Hynix Semiconductor Inc.Inventors: Jung Taik Cheong, Sang Do Lee, Bong Ho Choi
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Patent number: 6916730Abstract: First of all, a semiconductor substrate is provided. Then a gate oxide layer having an uniform thickness is formed on the semiconductor substrate by way of using thermal oxidation. Subsequently, a doping layer is formed on the gate oxide layer by a plasma doped process. Next, forming a poly-layer on the doping layer of the gate oxide layer, wherein the poly-layer has an ions-distribution. Afterward, defining the poly-layer to form a poly-gate. The P-type ions are then implanted into the poly-gate and the substrate by way of using a self-aligned process. Finally, performing a thermal annealing process to form a uniform ion-implanting region and a poly-gate having a lower contact-resistance.Type: GrantFiled: February 20, 2003Date of Patent: July 12, 2005Assignee: Macronix International Co., Ltd.Inventor: Wei-Wen Chen
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Patent number: 6905982Abstract: A CVD device (100) used for depositing a silicon nitride has a structure in which a hot wall furnace (103) for thermally degrading a source gas and a chamber (101) for forming a film over a surface of a wafer (1) are separated from each other. The hot wall furnace (103) for thermally degrading the source gas is provided above the chamber (101), and a heater (104) capable of setting the inside of the furnace at a high temperature atmosphere of approximately 1200° C. is provided at the outer periphery thereof. The source gas, supplied to the hot wall furnace (103) through pipes (105) and (106), is thermally degraded in this furnace in advance, and degraded components thereof are supplied on a stage (102) of the chamber (101) to form a film on the surface of the wafer (1).Type: GrantFiled: April 19, 2002Date of Patent: June 14, 2005Assignee: Renesas Technology Corp.Inventors: Hidenori Sato, Katsuhiko Ichinose, Yukino Ishii, Tomoko Jinbo
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Patent number: 6903393Abstract: In a semiconductor device in which a plurality of field effect transistors are formed on a silicon surface having substantially a <110> orientation, the field effect transistors are disposed on the silicon surface such that a direction connecting a source region and a drain region of the field effect transistor is coincident to a substantially <110> direction.Type: GrantFiled: October 2, 2002Date of Patent: June 7, 2005Assignees: Tokyo Electron LimitedInventors: Tadahiro Ohmi, Shigetoshi Sugawa
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Patent number: 6900092Abstract: The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.Type: GrantFiled: June 27, 2002Date of Patent: May 31, 2005Assignee: International Business Machines CorporationInventors: Atul C. Ajmera, Dominic J. Schepis, Michael D. Steigerwalt
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Patent number: 6897149Abstract: A process for producing an electronic device material of a high quality MOS-type semiconductor having an insulating layer and a semiconductor layer with excellent electrical characteristics. A substrate incorporating single-crystal silicon as a main component is CVD-treated to form an insulating layer. The substrate is then exposed to a plasma generated from a process gas by microwave radiation from a plane antenna having a plurality of slots, to thereby modify the insulating film.Type: GrantFiled: January 25, 2002Date of Patent: May 24, 2005Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Toshio Nakanishi, Shigenori Ozaki, Seiji Matsuyama, Shigemi Murakawa, Yoshihide Tada
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Patent number: 6881684Abstract: A plate high-frequency electrode for supplying a high-frequency power of the VHF band and a grounding electrode are disposed in opposition to each other at an interval of less than 8 mm in a vacuum vessel; at least a silane-based gas and nitrogen gas as source gases are introduced into a reaction space of the vacuum vessel, and a silicon nitride deposited film is formed with the pressure of the reaction space being kept at 40 to 133. Thereby, a silicon nitride film with good quality can be obtained.Type: GrantFiled: August 29, 2003Date of Patent: April 19, 2005Assignee: Canon Kabushiki KaishaInventors: Yukito Aota, Masahiro Kanai, Atsushi Koike, Tomokazu Sushihara
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Patent number: 6861104Abstract: A method of enhancing adhesion strength of a boro-silicate glass (BSG) film to a silicon nitride film is provided. A semiconductor substrate with a silicon nitride film formed thereon is provided. The silicon nitride film is then exposed to oxygen-containing plasma such as ozone plasma. A thick BSG film is then deposited onto the treated surface of the silicon nitride film. By pre-treating the silicon nitride film with ozone plasma for about 60 seconds, an increase of near 50% of Kapp of the BSG film is obtained.Type: GrantFiled: May 22, 2002Date of Patent: March 1, 2005Assignee: United Microelectronics Corp.Inventors: Hsin-Chang Wu, Cheng-Yuan Tsai, Yu-Wen Fang, Neng-Hui Yang
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Patent number: 6861321Abstract: One or more of three different measures are taken to preheat a wafer before it is loaded into direct contact with a wafer holder, in order to provide optimal throughput while reducing the risk of thermal shock to the wafer. The first measure is to move the wafer holder to a raised position prior to inserting the wafer into the reaction chamber and holding the wafer above the wafer holder. The second measure is to provide an increased flow rate of a heat-conductive gas (such as Hs purge gas) through the chamber prior to inserting the wafer therein. The third measure is to provide a power bias to radiative heat elements (e.g., heat lamps) above the reaction chamber.Type: GrantFiled: April 5, 2002Date of Patent: March 1, 2005Assignee: ASM America, Inc.Inventors: Tony J. Keeton, Michael R. Stamp, Mark R. Hawkins
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Patent number: 6849513Abstract: The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.Type: GrantFiled: October 14, 2003Date of Patent: February 1, 2005Assignee: Renesas Technology Corp.Inventors: Shimpei Tsujikawa, Jiro Yugami, Toshiyuki Mine, Masahiro Ushiyama
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Patent number: 6849562Abstract: A method for depositing a low k dielectric film comprising silicon, carbon, and nitrogen is provided. The low k dielectric film is formed by a gas mixture comprising a silicon source, a carbon source, and NR1R2R3, wherein R1, R2, and R3 are selected from the group consisting of alkyl and phenyl groups. The low k dielectric film may be used as a barrier layer, an etch stop, an anti-reflective coating, or a hard mask.Type: GrantFiled: March 4, 2002Date of Patent: February 1, 2005Assignee: Applied Materials, Inc.Inventors: Chi-I Lang, Li-Qun Xia, Ping Xu, Louis Yang
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Patent number: 6838397Abstract: An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulation film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 ?m in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×1021/cm3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH4HF2) of 7.13% and an ammonium fluoride (NH4F) of 15.4%.Type: GrantFiled: May 16, 2003Date of Patent: January 4, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Shunpei Yamazaki, Kengo Akimoto
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Publication number: 20040266123Abstract: One embodiment of the present invention is a method for treating silicon nitride (SixNy) films that includes electron beam treating the silicon nitride film.Type: ApplicationFiled: April 13, 2004Publication date: December 30, 2004Applicant: Applied Materials, Inc.Inventors: Zhenjiang Cui, Jun Zhao, Rick J. Roberts, Shulin Wang, Errol A. C. Sanchez, Aihua Chen
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Publication number: 20040259380Abstract: A plasma surface treatment system for irradiating a surface of a substrate to be treated with a nitrogen plasma excited by a high-frequency electric field to introduce nitrogen into the surface of the substrate comprises a pulse modulator for pulse modulation of the high-frequency electric field. By applying the high-frequency electric field in a pulsed form, it is possible to realize a nitriding by which the peak of nitrogen concentration is located at a shallower position and a desired nitrogen concentration can be obtained.Type: ApplicationFiled: March 17, 2004Publication date: December 23, 2004Inventors: Seiichi Fukuda, Seiji Samukawa
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Publication number: 20040256664Abstract: Methods for preparing a silicon oxynitride layer where the silicon oxynitride layer is deposited atop a substrate and have a low concentration of nitrogen at the interface of the silicon oxynitride layer and the substrate. The silicon oxynitride layer is formed by pulsing at least one interface precursor onto a substrate, where said substrate chemisorbs a portion of said at least one interface precursor to form a monolayer of said at least one interface precursor; and pulsing a nitrogen-containing precursor onto said substrate containing said monolayer of interface precursor, where said monolayer of said at least one interface precursor chemisorbs a portion of said nitrogen-containing precursor to form a monolayer of said nitrogen-containing precursor. The interface precursor includes oxygen-containing or silicon-containing precursor gasses.Type: ApplicationFiled: June 18, 2003Publication date: December 23, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Michael P. Chudzik, Toshiharu Furukawa, Oleg Gluschenkov, Paul D. Kirsch, Kristen C. Scheer, Joseph Shepard
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Patent number: 6825079Abstract: In order to form an oxide cover on a conductive filling in a trench in a semiconductor substrate an HDP oxide is deposited on the conductive filling using a PECVD method. In this case, the layer thickness on the horizontal surface of the conductive material is greater than the layer thickness on the sidewalls of the trench. Furthermore, the layer thickness is limited in such a way that the surface of the HDP oxide within the trench has a depth with respect to the surface of the semiconductor substrate surrounding the trench, or a layer disposed thereon. In a subsequent CMP step, the HDP oxide is removed from the surrounding surface. In an isotropic etching step, the HDP oxide is removed from the sidewalls. The result is a horizontal insulation layer with a layer thickness that varies only to a slight extent over the semiconductor substrate.Type: GrantFiled: March 21, 2003Date of Patent: November 30, 2004Assignee: Infineon Technologies AGInventor: Martin Popp
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Patent number: 6815350Abstract: A method for forming a ternary thin film using an atomic layer deposition process includes supplying a first and a second reactive material to a chamber containing a wafer, the first and second reactive materials being adsorbing on a surface of the wafer, supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, supplying a third reactive material to the chamber to cause a reaction between the first and second reactive materials and the third reactive material to form a thin film monolayer, supplying a second gas to purge the third reactive material that remains unreacted and a byproduct, and repeating the above steps for forming the thin film monolayer a predetermined number of times to form a ternary thin film having a predetermined thickness on the wafer. Preferably, the ternary thin film is a SiBN film.Type: GrantFiled: March 5, 2003Date of Patent: November 9, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Seok Kim, Yong-Woo Hyung, Man-Sung Kang, Jae-Young Ahn
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Patent number: 6815375Abstract: The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the material. The nitrogen is thermally annealed within the material to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the material. The invention also encompasses a method of forming a transistor device. A silicon-oxide-comprising layer is formed over a substrate. The silicon-oxide-comprising layer is exposed to nitrogen from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the layer. The nitrogen is thermally annealed within the layer to bond at least some of the nitrogen silicon proximate the nitrogen.Type: GrantFiled: November 3, 2003Date of Patent: November 9, 2004Assignee: Micron Technology, Inc.Inventor: John T. Moore
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Patent number: 6812164Abstract: A method for ionization film formation to form a deposited film by ionizing vaporized particles with an ionization mechanism of the hot-cathode system and injecting the ionized particles into a substrate is provided. The method includes the step of introducing He gas inside the ionization mechanism.Type: GrantFiled: January 24, 2003Date of Patent: November 2, 2004Assignee: Canon Kabushiki KaishaInventors: Hirohito Yamaguchi, Masahiro Kanai, Atsushi Koike, Katsunori Oya
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Patent number: 6812159Abstract: A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.Type: GrantFiled: April 22, 2003Date of Patent: November 2, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
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Publication number: 20040214413Abstract: By-products inside a furnace body of a CVD film forming apparatus after gas cleaning is performed in the furnace body are provided from being generated. The gas cleaning is performed in the furnace body by a plasma of a gas containing a halogen system gas and an Ar gas in an atmosphere in which the temperature of a heater disposed in the furnace body is approximately 500° C. or lower. Thereafter, a rise of the temperature of the heater is started. While the temperature of the heater is maintained constant, a film forming gas is introduced into the furnace body during a time period before the raised temperature reaches a temperature at which radicals or ions of a halogen system element are activated.Type: ApplicationFiled: April 22, 2004Publication date: October 28, 2004Applicant: Trecenti Technologies, Inc.Inventors: Tomoyasu Nakamine, Kenichi Yamaguchi, Kenichi Satoh
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Patent number: 6808758Abstract: A process for producing thin layers in electronic devices such as integrated circuit chips, is provided. The process includes the steps of injecting a precursor fluid into a thermal processing chamber containing a substrate, such as a semiconductor wafer. The precursor fluid is converted into a solid which forms a layer on the substrate. In accordance with the present invention, the precursor fluid is pulsed into the process chamber in a manner such that the fluid is completly exhausted or removed from the chamber in between each pulse. Light energy can be used in forming the solid layers.Type: GrantFiled: June 9, 2000Date of Patent: October 26, 2004Assignee: Mattson Technology, Inc.Inventor: Randhir P. S. Thakur
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Patent number: 6803309Abstract: A method for forming an adhesion/barrier liner with reduced fluorine contamination to improve adhesion and a specific contact resistance of metal interconnects including providing a semiconductor wafer having a process surface including an etched opening extending through a dielectric insulating layer thickness and in closed communication with a conductive underlayer surface; pre-heating the semiconductor wafer in a plasma reactor to a pre-heating temperature of at least about 400° C.; cleaning the etched opening according to a plasma assisted reactive pre-cleaning process (RPC) comprising nitrogen trifluoride (NF3); and, blanket depositing at least a first adhesion/barrier layer over the etched opening substantially free of fluorine containing residue.Type: GrantFiled: July 3, 2002Date of Patent: October 12, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Shih-Wei Chou, Chii-Ming Wu
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Patent number: 6787483Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.Type: GrantFiled: May 20, 2003Date of Patent: September 7, 2004Assignee: Novellus Systems, Inc.Inventors: Atiye Bayman, Md Sazzadur Rahman, Weijie Zhang, Bart van Schravendijk, Vishal Gauri, George D. Papasoulitotis, Vikram Singh
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Publication number: 20040166596Abstract: There are provided a step of forming an insulating film over a semiconductor substrate, a step of exciting a plasma of a gas having a molecular structure in which hydrogen and nitrogen are bonded and then irradiating the plasma onto the insulating film, a step of forming a self-orientation layer made of substance having a self-orientation characteristic on the insulating film, and a step of forming a first conductive film made of conductive substance having the self-orientation characteristic on the self-orientation layer.Type: ApplicationFiled: October 29, 2003Publication date: August 26, 2004Inventors: Naoya Sashida, Katsuyoshi Matsuura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
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Publication number: 20040166696Abstract: A method for producing an ultraviolet light (UV) transmissive silicon nitride layer in a plasma enhanced chemical vapor deposition (PECVD) reactor is presented. The UV transmissive film is produced by reducing, in comparison to a standard silicon nitride process, a flow rate of the silane and ammonia gas precursors to the PECVD reactor, and significantly increasing a flow rate of nitrogen gas to the reactor. The process reduces the concentration of Si—H bonds in the silicon nitride film to provide UV transmissivity. Further, the amount of nitrogen in the film is greater than in a standard PECVD silicon nitride film, and as a percentage constitutes a greater part of the film than silicon. The film has excellent step coverage and a low number of pinhole defects. The film may be used as a passivation layer in a UV erasable memory integrated circuit.Type: ApplicationFiled: February 24, 2003Publication date: August 26, 2004Applicant: Mosel Vitelic, Inc.Inventor: Tai-Peng Lee
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Patent number: 6777354Abstract: The present invention provides a semiconductor device capable of preventing deterioration in carrier mobility of a semiconductor layer, which is a quality of the interface between the semiconductor layer and an insulating layer, and a method of manufacturing the semiconductor device. In the semiconductor device, an interface layer is provided between a semiconductor layer made of active polycrystalline silicon and an insulating layer made of silicon oxide. The nitrogen element in silicon nitride diffuses into the semiconductor layer made of active polycrystalline silicon to compensate for lattice strain of the active polycrystalline silicon film, to satisfy the desired quality of the interface between the semiconductor layer and the insulating layer.Type: GrantFiled: August 20, 2003Date of Patent: August 17, 2004Assignee: LG Philips LCD Co., Ltd.Inventor: Chae Gee Sung
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Patent number: 6773999Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate, and a gate electrode formed on the gate insulating film. Nitrogen is introduced into the gate insulating film, and the nitrogen concentration distribution thereof has a peak near the surface of the gate insulating film or near the center of the gate insulating film in the thickness direction. The peak value of nitrogen concentration in the gate insulating film is equal to or greater than 10 atm % and less than or equal to 40 atm %.Type: GrantFiled: July 16, 2002Date of Patent: August 10, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kenji Yoneda
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Publication number: 20040127067Abstract: A showerhead diffuser apparatus for a CVD process has a first channel region having first plural independent radially-concentric channels and individual gas supply ports from a first side of the apparatus to individual ones of the first channels, a second channel region having second plural independent radially-concentric channels and a pattern of diffusion passages from the second channels to a second side of the apparatus, and a transition region between the first channel region and the second channel region having at least one transition gas passage for communicating gas from each first channel in the first region to a corresponding second channel in the second region. The showerhead apparatus has a vacuum seal interface for mounting the showerhead apparatus to a CVD reactor chamber such that the first side and supply ports face away from the reactor, chamber and the second side and the patterns of diffusion passages from the second channels open into the reactor chamber.Type: ApplicationFiled: September 4, 2003Publication date: July 1, 2004Inventor: Scott William Dunham
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Patent number: 6756293Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.Type: GrantFiled: December 16, 2002Date of Patent: June 29, 2004Assignee: Micron Technology, Inc.Inventors: Weimin Li, Sujit Sharan, Gurtej Sandhu
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Patent number: 6756324Abstract: A thin film transistor is described incorporating a gate electrode, a gate insulating layer, a semiconducting channel layer deposited on top of the gate insulating layer, an insulating encapsulation layer positioned on the channel layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer, all of which are situated on a plastic substrate. By enabling the use of plastics having low glass transition temperatures as substrates, the thin film transistors may be used in large area electronics such as information displays and light sensitive arrays for imaging which are flexible, lighter in weight and more impact resistant than displays fabricated on traditional glass substrates. The thin film transistors are useful in active matrix liquid crystal displays where the plastic substrates are transparent in the visible spectrum.Type: GrantFiled: March 25, 1997Date of Patent: June 29, 2004Assignee: International Business Machines CorporationInventor: Stephen McConnell Gates
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Publication number: 20040115943Abstract: A method for reducing electrical discharges within semiconductor wafers including providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process wafer; and, limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.Type: ApplicationFiled: December 17, 2002Publication date: June 17, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hsiang Yao, Yun-Cheng Lu
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Patent number: 6737364Abstract: This invention describes a new method for forming and depositing thin films of crystalline dielectric materials. The present technique uses chemical synthesis to control the granularity and thickness of the dielectric films. This method has several key advantages over existing technologies, and facilitates the integration of crystalline dielectric materials into high-density memory devices.Type: GrantFiled: October 7, 2002Date of Patent: May 18, 2004Assignee: International Business Machines CorporationInventors: Charles Black, Christopher Bruce Murray
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Patent number: 6737365Abstract: A dielectric layer is made porous by treating the dielectric material after metal interconnects are formed in or through that layer. The porosity lowers the dielectric constant of the dielectric material. The dielectric material may be subjected to an electron beam or a sonication bath to create the pores. The structure has smooth sidewalls for metal interconnects extending through the dielectric layer.Type: GrantFiled: March 24, 2003Date of Patent: May 18, 2004Assignee: Intel CorporationInventors: Grant M. Kloster, Kevin P. O'Brien, Justin K. Brask, Michael D. Goodner, Donald Bruner
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Patent number: 6734116Abstract: Within a damascene method for forming a microelectronic fabrication, there is employed an etch stop layer comprising a comparatively low dielectric constant dielectric material sub-layer having formed thereupon a comparatively high dielectric constant dielectric material sub-layer. Within the method there is also simultaneously etched: (1) an anti-reflective coating layer from an inter-metal dielectric layer; and (2) the etch stop layer from a contact region. The microelectronic fabrication is formed with enhanced performance and enhanced reliability.Type: GrantFiled: January 11, 2002Date of Patent: May 11, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Cheng Guo, Dian-Hau Chen, Li-Kong Turn, Han-Ming Sheng
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Publication number: 20040072081Abstract: Method and apparatus for etching an optically transparent layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for etching a substrate comprising placing the reticle on a support member in a processing chamber, positioning the reticle on a support member in a processing chamber, wherein the reticle comprises a patterned metal photomask layer formed on an optically transparent material, and a patterned resist material deposited on the patterned metal photomask layer, introducing a processing gas comprising one or more fluorine containing hydrocarbons and one or more chlorine-containing gases into the processing chamber, delivering power to the processing chamber to generate a plasma by applying a source RF power to a coil and applying a bias power to the support member, and etching exposed portions of the optically transparent material.Type: ApplicationFiled: May 13, 2003Publication date: April 15, 2004Inventors: Thomas P. Coleman, Yi-Chiau Huang, Melisa J. Buie, Lawrence C. Sheu, Brigitte C. Stoehr, Phillip L. Jones
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Patent number: 6713390Abstract: A method is provided for depositing a barrier layer on a substrate using a gaseous mixture that includes a hydrocarbon-containing gas and a silicon-containing gas. The gaseous mixture is provided to a process chamber and is used to form a plasma for depositing the barrier layer. The barrier layer is deposited with a thickness less than 500 Å. Suitable hydrocarbon-containing gases include alkanes and suitable silicon-containing gases include silanes.Type: GrantFiled: July 12, 2002Date of Patent: March 30, 2004Assignee: Applied Materials Inc.Inventors: Hichem M'Saad, Seon Mee Cho, Dana Tribula
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Publication number: 20040058497Abstract: Novel methods for improving the within-wafer uniformity of a gate oxide layer on a semiconductor wafer substrate. According to a first embodiment, a gate oxide layer is formed on a wafer using conventional oxidation parameters and equipment. Next, the edge-thick gate oxide layer is nitridated using a center-thick plasma nitridation profile to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer. According to a second embodiment, the wafer substrate is first nitridated and then oxidized to form the gate oxide layer. The nitrogen incorporated into the wafer surface during the nitridation step retards oxidation of the wafer at the wafer edge to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer.Type: ApplicationFiled: August 7, 2002Publication date: March 25, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Chun Chen, Ming-Fang Wang, Shih-Chang Chen
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Patent number: 6709965Abstract: A process for forming a bond pad structure to be used to accommodate a subsequent wire bond, has been developed. The process features defining a bond pad opening in a composite insulator stack, exposing a portion of a top surface of an upper level metal interconnect structure at the bottom of the bond pad opening. The bond pad opening is formed with a top portion of the composite insulator stack laterally pulled back from a bottom portion of the same composite insulator stack. The bond pad structure, comprised of aluminum—copper, is then formed entirely in the bond pad opening, with the top surface of the bond pad structure lower than the top surface of the composite insulator stack, thus resulting in a bond pad structure topography offering reduced risk of damage during subsequent pre-wire bonding procedures.Type: GrantFiled: October 2, 2002Date of Patent: March 23, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuo-Chou Chen, Huai-Jen Hsu
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Publication number: 20040043637Abstract: A plate high-frequency electrode for supplying a high-frequency power of the VHF band and a grounding electrode are disposed in opposition to each other at an interval of less than 8 mm in a vacuum vessel; at least a silane-based gas and nitrogen gas as source gases are introduced into a reaction space of the vacuum vessel, and a silicon nitride deposited film is formed with the pressure of the reaction space being kept at 40 to 133. Thereby, a silicon nitride film with good quality can be obtained.Type: ApplicationFiled: August 29, 2003Publication date: March 4, 2004Inventors: Yukito Aota, Masahiro Kanai, Atsushi Koike, Tomokazu Sushihara
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Publication number: 20040043638Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: ApplicationFiled: August 20, 2003Publication date: March 4, 2004Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20040043560Abstract: In order to form an oxide cover on a conductive filling in a trench in a semiconductor substrate an HDP oxide is deposited on the conductive filling using a PECVD method. In this case, the layer thickness on the horizontal surface of the conductive material is greater than the layer thickness on the sidewalls of the trench. Furthermore, the layer thickness is limited in such a way that the surface of the HDP oxide within the trench has a depth with respect to the surface of the semiconductor substrate surrounding the trench, or a layer disposed thereon. In a subsequent CMP step, the HDP oxide is removed from the surrounding surface. In an isotropic etching step, the HDP oxide is removed from the sidewalls. The result is a horizontal insulation layer with a layer thickness that varies only to a slight extent over the semiconductor substrate.Type: ApplicationFiled: March 21, 2003Publication date: March 4, 2004Inventor: Martin Popp
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Publication number: 20040038463Abstract: The present invention provides a semiconductor device capable of preventing deterioration in carrier mobility of a semiconductor layer, which is a quality of the interface between the semiconductor layer and an insulating layer, and a method of manufacturing the semiconductor device. In the semiconductor device, an interface layer is provided between a semiconductor layer made of active polycrystalline silicon and an insulating layer made of silicon oxide. The nitrogen element in silicon nitride diffuses into the semiconductor layer made of active polycrystalline silicon to compensate for lattice strain of the active polycrystalline silicon film, to satisfy the desired quality of the interface between the semiconductor layer and the insulating layer.Type: ApplicationFiled: August 20, 2003Publication date: February 26, 2004Inventor: Chae Gee Sung
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Patent number: 6686232Abstract: A thin silicon nitride layer is deposited at an ultra low deposition rate by PECVD by reducing the NH3 flow rate and/or reducing the SiH4 flow rate. Embodiments include depositing a thin layer of silicon nitride, e.g., 100 Å or less, on a thin silicon oxide liner over a gate electrode, at an NH3 flow rate of 100 to 800 sccm, a SiH4 flow rate of 50 to 100 sccm and a reduced pressure of 0.8 to 1.8 Torr. Embodiments of the present invention further include depositing the silicon nitride layer in multiple deposition stages, e.g., depositing the silicon nitride layer in five deposition stages of 20 Å each.Type: GrantFiled: June 19, 2002Date of Patent: February 3, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Robert A. Huertas, Dawn Hopper, Hieu Pham
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Publication number: 20040018750Abstract: Disclosed are processes for depositing a silicon carbonitride (Si—C—N) material and resulting films. The process involves plasma enhanced chemical vapor deposition (PECVD), in which chemical precursors for silicon and carbon are supported by nitrogen gas (N2). Nitrogen gas not only supports the other chemical precursors and plasma species during the PECVD process, but also participates in the film formation. The nitrogen carrier gas is activated by plasma energy as other chemical precursors. Excited species of nitrogen gas react with excited species of silicon and carbon to deposit the Si—C—N material on a substrate. The use of nitrogen gas improves the stability of the plasma and eliminates arcing during the PECVD process. Further, the resulting Si—C—N material showed improved properties, such as less aging effects and improved thermal stability, as compared to processes using other carrier gases.Type: ApplicationFiled: July 2, 2002Publication date: January 29, 2004Inventors: Auguste J.L. Sophie, Fumitoshi Ozaki