Substrate Surface Preparation Patents (Class 438/974)
-
Patent number: 7052927Abstract: A PIN detector device (190) is fabricated on a substrate (10). The substrate (10) includes a handle wafer portion (208), an implanted oxide layer (206), a backside contact layer (204) and an active wafer portion (202). The substrate (10) serves as a foundation to increase stability and facilitate handling during fabrication of electrical circuitry (248) on a surface of the active wafer portion (202). After the electrical circuitry fabrication processing is substantially complete, the handle wafer portion (208) and implanted oxide layer (206) are removed to expose the implanted backside contact layer (204).Type: GrantFiled: January 27, 2004Date of Patent: May 30, 2006Assignee: Raytheon CompanyInventors: Christopher Lee Fletcher, Andrew G. Toth, Jerry R. Cripe
-
Patent number: 7041178Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.Type: GrantFiled: June 13, 2003Date of Patent: May 9, 2006Assignee: Ziptronix, Inc.Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
-
Method for treating substrates for microelectronics and substrates obtained according to said method
Patent number: 7029993Abstract: The invention relates to a method for treating substrates (50) for microelectronics or optoelectronics, whereby said substrates comprise a useful layer (52) on at least one of the surfaces thereof. The inventive method includes a mechanical/chemical polishing step occurring on a bare surface (54) of the useful layer and is characterized in that it also comprises a post-curing step in a reductive atmosphere (100) before said polishing step occurs.Type: GrantFiled: August 17, 2000Date of Patent: April 18, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Thierry Barge, André Auberton-Herve, Hiroji Aga, Naoto Tate -
Patent number: 7011717Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1–60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 ?m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.Type: GrantFiled: August 31, 2004Date of Patent: March 14, 2006Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
-
Patent number: 7008886Abstract: A process treats a surface of a semiconductor material in order to put the surface into a predetermined electrical state. The semiconductor material is preferably monocrystalline. The process includes (a) preparing the surface of the semiconductor material such that the surface has a controlled organization at an atomic scale such that the surface is capable of combining with a chosen material, and (b) combining the surface thus prepared with a material chosen from among hydrogen, molecules containing hydrogen, metals, organic molecules and inorganic molecules, wherein the preparing and the combining the surface with the material cooperate to obtain the predetermined electrical state of the surface.Type: GrantFiled: April 17, 2002Date of Patent: March 7, 2006Assignee: Commissariat a l'Energie AtomiqueInventors: Vincent Derycke, Patrick Soukiassan
-
Patent number: 7005368Abstract: The present invention provides a bump forming apparatus (101, 501) which can prevent charge appearance semiconductor substrates (201, 202) from pyroelectric breakdown and physical failures, a method carried out by the bump forming apparatus for removing charge of charge appearance semiconductor substrates, a charge removing unit for charge appearance semiconductor substrates, and a charge appearance semiconductor substrate. At least when the wafer is cooled after the bump bonding is connected on the wafer, electric charge accumulated on the wafer (202) because of the cooling is removed through direct contact with a post-forming bumps heating device (170), or the charge is removed by a decrease in temperature control so that charge can be removed in a noncontact state. Therefore, an amount of charge of the wafer can be reduced in comparison with the conventional art, so that the wafer is prevented from pyroelectric breakdown and damage such as a break or the like to the wafer itself.Type: GrantFiled: August 29, 2003Date of Patent: February 28, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shoriki Narita, Yasutaka Tsuboi, Masahiko Ikeya, Takaharu Mae, Shinji Kanayama
-
Patent number: 7001845Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.Type: GrantFiled: April 26, 2004Date of Patent: February 21, 2006Assignee: Micron Technology, Inc.Inventors: Scott E. Moore, Trung Tri Doan
-
Patent number: 6995077Abstract: A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface, wherein the surface of the epitaxial layer has a maximum density of 0.14 localized light scatterers per cm2 with a cross section of greater than or equal to 0.12 ?m, and the front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 ?m×1 ?m reference area. There is also a process for producing a semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface.Type: GrantFiled: December 9, 2003Date of Patent: February 7, 2006Assignee: Siltronic AGInventors: Wolfgang Siebert, Peter Storck
-
Patent number: 6991944Abstract: This invention relates to a process for treatment of a multi-layer wafer with materials having differential thermal characteristics, the process comprising a high temperature heat treatment step that can generate secondary defects, characterised in that this process includes a wafer surface preparation step before the high temperature heat treatment step.Type: GrantFiled: August 10, 2004Date of Patent: January 31, 2006Assignees: S.O.I.Tec Silicon on Insulation Technologies S.A., Commissariat à l'Energie Atomique (CEA)Inventors: Olivier Rayssac, Beryl Blondeau, Hubert Moriceau, Christelle Lagahe-Blanchard, Franck Fournel
-
Patent number: 6992016Abstract: Air trapped in a blind hole during processing of the blind hole with a liquid is eliminated by circulating the liquid along a surface-to-be-processed in substantially a single direction at all times and by setting a velocity gradient of the liquid over the surface to at least 300/second.Type: GrantFiled: December 2, 2004Date of Patent: January 31, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takeo Nakamoto, Katsuya Kosaki, Masaru Kinugawa
-
Patent number: 6969670Abstract: At the time of selective growth of an active layer on a substrate, crystal is previously grown in an active layer non-growth region, and the active layer is grown in an active layer selective growth region. With this configuration, a source supplied to the non-growth region is incorporated in the deposited crystal from the initial stage of growth, so that the supplied amount of the source to the active layer selective growth region is kept nearly at a constant value over the entire period of growth of the active layer, to eliminate degradation of characteristics of the device due to a variation in growth rate of the active layer. In particular, the selective growth method is effective in fabrication of a semiconductor light emitting device including a cladding layer, a guide layer, and an active layer, each of which is formed by selective growth, wherein the active layer has multiple quantum wells.Type: GrantFiled: January 14, 2003Date of Patent: November 29, 2005Assignee: Sony CorporationInventors: Goshi Biwa, Hiroyuki Okuyama
-
Patent number: 6902987Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process the method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.Type: GrantFiled: February 16, 2000Date of Patent: June 7, 2005Assignee: Ziptronix, Inc.Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
-
Patent number: 6900113Abstract: The present invention provides a method for producing a bonded wafer comprising at least an ion implantation process where at least either hydrogen ions or rare gas ions are implanted into a first wafer from its surface to form a micro bubble layer (implanted layer) in the first wafer, a bonding process where the surface subjected to the ion implantation of the first wafer is bonded to a surface of a second wafer, and a delamination process where the first wafer is delaminated at the micro bubble layer, wherein the ion implantation process is performed in divided multiple steps, and a bonded wafer. Thus, there are provided a method for producing a bonded wafer, which is for reducing micro-voids generated in the ion implantation and delamination method and a bonded wafer free from micro-voids.Type: GrantFiled: May 29, 2001Date of Patent: May 31, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masatake Nakano, Isao Yokokawa, Kiyoshi Mitani
-
Patent number: 6884732Abstract: A method of fabricating a device having a desired non-planar surface or profile and device produced thereby are provided. A silicon wafer is first coated with silicon nitride, patterned, and DRIE to obtain the desired etch profile. Silicon pillars between trenches are then etched using an isotropic wet etch, resulting in a curved well. The wafer is then oxidized to ?2 ?m to smooth the surface of the well, and to protect the well from an ensuing planarization process. The nitride is then selectively removed, and the wafer surface is planarized by removing the Si left in the field regions using either a maskless DRIE or CMP. Finally, the oxide is etched away to produce a wafer with a curved surface.Type: GrantFiled: October 11, 2002Date of Patent: April 26, 2005Assignee: The Regents of the University of MichiganInventors: Khalil Najafi, Chou Tsung-Kuan
-
Patent number: 6855994Abstract: A semiconductor device including a gate oxide of multiple thicknesses for multiple transistors where the gate oxide thicknesses are altered through the growth process of implanted oxygen ions into selected regions of a substrate. The implanted oxygen ions accelerate the growth of the oxide which also allow superior quality and reliability of the oxide layer, where the quality is especially important, compared to inter-metal dielectric layers. A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during oxidation growth process by implanting nitrogen into selected regions of the substrate, which the nitrogen ions retard the growth of the silicon oxide resulting in a diminished oxide quality. Therefore it is desirable to fabricate a semiconductor device with multiple thicknesses of gate oxide by the implanted oxygen ion technique.Type: GrantFiled: November 29, 1999Date of Patent: February 15, 2005Assignee: The Regents of the University of CaliforniaInventors: Ya-Chin King, Tsu-Jae King, Chen Ming Hu
-
Patent number: 6849555Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.Type: GrantFiled: May 30, 2003Date of Patent: February 1, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-myeong Lee, Byung-hee Kim, Myoung bum Lee, Ju-young Yun, Gil-heyun Choi
-
Patent number: 6833279Abstract: Provided is a method of fabricating and repairing ceramic components for semiconductor fabrication, through which erosion and polymer deposition occurring on ceramic components for semiconductor fabrication are decreased by modifying the dielectric surface of a component having an electrical insulation characteristic so that the ceramic components can be repaired after being used. The method includes activating a surface layer of a component, which is manufactured by sintering a ceramic, and depositing a dielectric coating layer on the surface layer of the ceramic component using a plasma spray process; when the dielectric coating layer is damaged as the ceramic component is used for semiconductor fabrication, removing the dielectric coating layer; and repairing the ceramic component by depositing a dielectric coating layer on the surface layer of the ceramic component from which the damaged dielectric coating layer has been removed.Type: GrantFiled: December 4, 2002Date of Patent: December 21, 2004Assignee: Komico Co., Ltd.Inventor: Jin-Sik Choi
-
Patent number: 6809015Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.Type: GrantFiled: January 9, 2003Date of Patent: October 26, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
-
Patent number: 6790777Abstract: The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again.Type: GrantFiled: November 6, 2002Date of Patent: September 14, 2004Assignee: Texas Instruments IncorporatedInventors: Glenn J. Tessmer, Ju-Ai Ruan, Mercer Lusk Brugler, Sarah Hartwig
-
Patent number: 6784020Abstract: A package structure and method for making devices of system-in-a-package (SiP). Substrates with integrated and assembled elements can be aligned and pre-bonded together, and fluidic encapsulating materials is applied to seal the rest opening of pre-bonded interface of substrates. Three dimensional and protruding microstructures, elements, and MFMS devices can be accommodated and protected inside a spatial space formed by the bonded substrates. By applying the technologies of flip-chip, chip-scale-packaging, and wafer-level-packaging in conjunction with present invention, then plural elements and devices can be packaged together and become a system device in wafer-level-system-in-a-package (WLSiP) format.Type: GrantFiled: October 30, 2002Date of Patent: August 31, 2004Assignee: Asia Pacific Microsystems, Inc.Inventors: Chengkuo Lee, Yi-Mou Huang
-
Patent number: 6780737Abstract: A method of manufacturing semiconductor devices with buried conductive lines is disclosed. The method uses an ion implantation process to form buried conductive lines under isolation regions such as shallow trench isolations. The buried conductive lines connect neighboring active regions and replace conventional contacts and lead lines connecting the active regions.Type: GrantFiled: December 19, 2002Date of Patent: August 24, 2004Assignee: Macronix International Co., Ltd.Inventor: Chao-Yang Chen
-
Patent number: 6734121Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.Type: GrantFiled: September 2, 1999Date of Patent: May 11, 2004Assignee: Micron Technology, Inc.Inventors: Scott E. Moore, Trung Tri Doan
-
Patent number: 6720640Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.Type: GrantFiled: May 29, 2003Date of Patent: April 13, 2004Assignees: Shin-Etsu Handotai Co., Ltd., S.O.I. Tec Silicon on Insulator TechnologiesInventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville
-
Patent number: 6674502Abstract: A liquid crystal display includes an insulative substrate having a surface treated with an oxygen plasma and a nitrogen-plasma-treated layer formed over said surface of said substrate. A surface of said nitrogen-plasma-treated layer has a nitrogen concentration of about 10 mol % or more.Type: GrantFiled: November 16, 2000Date of Patent: January 6, 2004Assignee: Hitachi, Ltd.Inventors: Masatomo Terakado, Toshiki Kaneko, Takuya Takahashi, Kenichi Chahara, Kenichi Onisawa
-
Patent number: 6660653Abstract: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a quartz layer of the PSM is patterned according to a semiconductor design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the alternating PSM design by using beam writing. This initially forms deep trenches of the PSM. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the deep trenches and the shallow trenches of the alternating PSM design by using backside ultraviolet exposure. This completely forms shallow trenches and the deep trenches of the PSM. The second photoresist layer is then removed.Type: GrantFiled: May 21, 2002Date of Patent: December 9, 2003Assignee: Taiwan Semiconductor Manufacturing Co. LtdInventors: San-De Tzu, Chang-Ming Dai, Ching-Hsing Chang
-
Patent number: 6645852Abstract: A process for fabricating a semiconductor device, which comprises forming a recess portion in an insulating film covering a wiring made of copper or a copper alloy so that the recess portion reaches the wiring, wherein, after forming the recess portion, a plasma treatment using a gas containing hydrogen gas and nitrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion, or a plasma treatment using a gas containing hydrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion while cooling a substrate on which the wiring is formed. By the process of the present invention, a problem of redeposition of copper on the sidewall of a via hole in the argon sputtering and a problem of an etching process of the organic insulating film in the hydrogen plasma treatment can be solved, thus realizing excellent cleaning of the bottom portion of the via hole.Type: GrantFiled: October 17, 2000Date of Patent: November 11, 2003Assignee: Sony CorporationInventors: Mitsuru Taguchi, Shingo Kadomura, Miyata Koji
-
Publication number: 20030194844Abstract: A semiconductor substrate stock/transfer vessel is an openable/closeable sealed vessel used in a semiconductor device manufacturing process and adapted to store or transfer a semiconductor substrate. The semiconductor substrate stock/transfer vessel incorporates at least one adsorbent capable of adsorbing an organic substance, and the adsorbent is mounted detachably.Type: ApplicationFiled: May 12, 2003Publication date: October 16, 2003Inventor: Tatsuya Suzuki
-
Patent number: 6632688Abstract: A method for evaluating the concentration of impurities in gases used in depositing an epitaxial layer on a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels in an epitaxial reactor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.Type: GrantFiled: November 14, 2001Date of Patent: October 14, 2003Assignee: SEH America, Inc.Inventor: Sergei V. Koveshnikov
-
Patent number: 6602762Abstract: A laser sintering system is provided for sintering a die having a serrate edge. The laser sintering system comprises a laser generator for generating a laser beam and a movable carriage for carrying said die. The laser beam sinters the serrate edge of said die into a smooth edge. A method of sintering a die, the die having a serrate edge, comprises the following steps of providing a die and using a laser beam sintering the serrate edge of said die into a smooth edge. A die has a smooth edge sintered by a laser beam.Type: GrantFiled: March 25, 2002Date of Patent: August 5, 2003Assignee: Chipbond Technology CorporationInventors: Lu-Chen Hwan, Dang-Cheng Yiu
-
Patent number: 6599758Abstract: A method for reducing microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate by post-epitaxial thermal oxidation. The method produces very smooth semiconductor wafers by performing the steps of depositing an epitaxial layer on a wafer substrate, oxidizing a top portion of the expitaxial layer, and removing the oxidized top portion. As a result, the wafer's surface presents little or no microsteps thereon.Type: GrantFiled: August 16, 2002Date of Patent: July 29, 2003Assignee: MOS EPI, Inc.Inventors: Danny Kenny, Keith Lindberg
-
Patent number: 6596610Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.Type: GrantFiled: July 25, 2001Date of Patent: July 22, 2003Assignees: Shin-Etsu Handotai Co. Ltd., S.O.I. Tec Silicon on Insulator TechnologiesInventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville
-
Patent number: 6593161Abstract: A method has been provided for the removal of oxidation from a substrate surface formed as the result of an ozone cleaning process in the fabrication of a liquid crystal display (LCD). A first method uses a dry etchant, such as CL2 gas, to remove the ozone oxidation layer. A second method uses a counter sputtering process to remove the ozone oxidation layer.Type: GrantFiled: December 12, 2001Date of Patent: July 15, 2003Assignee: Sharp Laboratories of America, Inc.Inventor: Hirohiko Nishiki
-
Patent number: 6589875Abstract: In one illustrative embodiment, the method includes providing a wafer including at least one non-production area, forming a process layer above the wafer, forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and performing a process operation on the exposed portion of the process layer formed above the at least one non-production area. In another aspect, the present invention is directed to a system that includes a controller for identifying at least one non-production area of a wafer, a photolithography tool for forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and an etch tool for performing an etching process on the exposed portion of the process layer formed above the at least one non-production area.Type: GrantFiled: August 2, 2001Date of Patent: July 8, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Christopher A. Bode, Alexander J. Pasadyn
-
Patent number: 6586340Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.Type: GrantFiled: March 13, 2002Date of Patent: July 1, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-myeong Lee, Byung-hee Kim, Myoung bum Lee, Ju-young Yun, Gil-heyun Choi
-
Patent number: 6563133Abstract: A process for bonding oxide-free silicon substrate pairs and other substrates at low temperature. This process involves modifying the surface of the silicon wafers to create defect regions, for example by plasma-treating the surface to be bonded with a or boron-containing plasmas such as a B2H6 plasma. The surface defect regions may also be created by ion implantation, preferably using boron. The surfaces may also be amorphized. The treated surfaces are placed together, thus forming an attached pair at room temperature in ambient air. The bonding energy reaches approximately 400 mJ/M2 at room temperature, 900 mJ/M2 at 150° C., and 1800 mJ/M2 at 250° C. The bulk silicon fracture energy of 2500 mJ/m2 was achieved after annealing at 350-400° C. The release of hydrogen from B—H complexes and the subsequent absorption of the hydrogen by the plasma induced modified layers on the bonding surfaces at low temperature is most likely responsible for the enhanced bonding energy.Type: GrantFiled: August 9, 2000Date of Patent: May 13, 2003Assignee: Ziptronix, Inc.Inventor: Qin-Yi Tong
-
Patent number: 6558964Abstract: In one method for monitoring a semiconductor wafer during a spin drying operation, a capacitance value between a capacitance sensor and the wafer is measured as the wafer is being spun to dry a surface thereof. When it is determined that the measured capacitance value has reached a substantially constant level, a signal is generated indicating that the surface of the semiconductor wafer is dry. In another method, light is directed toward a surface of the wafer as the wafer is being spun to dry a surface thereof. The light is directed such that the light that reflects off of the surface of the wafer is substantially perpendicular to the surface of the wafer. The intensity of the light reflected off of the surface of the semiconductor wafer is measured.Type: GrantFiled: December 27, 2000Date of Patent: May 6, 2003Assignee: Lam Research CorporationInventor: Randolph E. Treur
-
Patent number: 6548387Abstract: A method for reducing hole defects in the polysilicon layer. The method at least includes the following steps. First of all, a semiconductor substrate is provided, a polysilicon layer is formed over the semiconductor substrate. Then, no hole defects bottom anti-reflective coating process is performed, wherein the no hole defect bottom anti-reflective coating process is selected from the group consisting of dehydration baking, hydrophobic solvent treatment, and steady baking. Finally, a bottom anti-reflective coating is formed over the polysilicon layer.Type: GrantFiled: July 20, 2001Date of Patent: April 15, 2003Assignee: United Microelectronics CorporationInventors: Chung-Jung Hsu, Chih-Hsien Huang
-
Patent number: 6531416Abstract: A method for heat treatment of a silicon wafer in a reducing atmosphere through use of a rapid thermal annealer (RTA) is provided. In the method, the silicon wafer is heat-treated at a temperature of 1150° C. to 1300° C. for 1 sec to 60 sec in a mixture gas atmosphere of hydrogen and argon. Hydrogen is present in the mixture gas atmosphere in an amount of 10% to 80% by volume. Hydrogen is preferably present in the mixture gas atmosphere in an amount of 20% to 40% by volume. The method decreases COP density on the surface of the silicon wafer to thereby improve electrical characteristics, such as TZDB and TDDB, of the silicon wafer, suppresses the generation of slip dislocation to thereby prevent wafer breakage, and utilizes intrinsic advantages of the RTA, such as improvement in productivity and reduction in hydrogen gas usage.Type: GrantFiled: October 23, 1998Date of Patent: March 11, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Toshihiko Miyano, Satoshi Oka
-
Publication number: 20030027429Abstract: The present invention relates to a process for removing post-etch residues or polymers from the surface of semiconductor devices which comprises treating the semiconductor device with an aqueous ammonia or ammonium hydroxide solution, optionally containing ozone for a time sufficient to effectively remove said post-etch residues or polymers from the surface of the semiconductor device and rinsing the semiconductor device with ozonized water, i.e. water enriched with ozone, in which water is preferably deionized (ozone-DIW).Type: ApplicationFiled: July 2, 2002Publication date: February 6, 2003Applicant: STMicroelectronics S.r.I.Inventors: Enrico Bellandi, Francesco Pipia, Mauro Alessandri
-
Patent number: 6509275Abstract: In pre-treating a surface of a substrate in a process of forming a narrowed thin film pattern on the surface of the substrate from a solution such as a plating liquid, a mask with an opening corresponding to the thin film pattern to be formed later is formed on the surface of the substrate. Then, by micronizing a pre-treating liquid such as a water, a plating liquid, an acidic liquid ad an alkaline liquid, an atmosphere containing microparticles having diameters smaller than the minimum distance of the opening of the mask is produced. The substrate is positioned into the atmosphere, and the microparticles of the pre-treating liquid are stuck on the surface of the substrate exposing to the lower part of the opening of the mask. In using a water as the pre-treating liquid, the substrate is positioned into an atmosphere containing moisture vapor and the water particles are stuck on the surface of the substrate through their condensation.Type: GrantFiled: October 7, 1999Date of Patent: January 21, 2003Assignee: TDK CorporationInventor: Akifumi Kamijima
-
Patent number: 6500747Abstract: A method of manufacturing a semiconductor substrate is provided. The method includes a first step of forming a rugged portion in a GaN substrate, and a second step of forming a GaN thin film on the GaN substrate at a lateral growth rate fast enough to cover the GaN thin film vertically grown with the GaN thin film laterally grown, so that the rugged portion is covered with the GaN thin film.Type: GrantFiled: October 12, 2001Date of Patent: December 31, 2002Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Won-seok Lee, Ok-hyun Nam, Cheol-soo Sone
-
Patent number: 6489180Abstract: A flip-chip packaging process is proposed, which can help assure reliable electrical bonding between chip-side solder bumps and substrate-side bond pads without being made open-circuited by the electrically-insulative material being used for flip chip underfill. The proposed flip-chip packaging process is of the type utilizing a no-flow underfill technique to prevent short-circuiting between neighboring solder bumps, and is characterized in the fabrication of electrically-conductive sharp-pointed studs over substrate-side bond pads to prevent open-circuiting between chip-side solder bumps and substrate-side bond pads.Type: GrantFiled: October 10, 2000Date of Patent: December 3, 2002Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ying Chou Tsai, Shih Kuang Chiu
-
Patent number: 6482659Abstract: A method for reducing microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate by post-epitaxial thermal oxidation. The method produces very smooth semiconductor wafers by performing the steps of depositing an epitaxial layer on a wafer substrate, oxidizing a top portion of the epitaxial layer, and removing the oxidized top portion. As a result, the wafer's surface presents little or no microsteps thereon.Type: GrantFiled: April 2, 2002Date of Patent: November 19, 2002Assignee: GlobiTech IncorporatedInventors: Danny Kenny, Keith Lindberg
-
Patent number: 6465272Abstract: The present invention relates to reflective masks and their use for reflecting extreme ultraviolet soft x-ray photons to enable the use of extreme ultraviolet soft x-ray radiation projection lithographic methods and systems for producing integrated circuits and forming patterns with extremely small feature dimensions. The projection lithographic method includes providing an illumination sub-system for producing and directing an extreme ultraviolet soft x-ray radiation &lgr; from an extreme ultraviolet soft x-ray source; providing a mask sub-system illuminated by the extreme ultraviolet soft x-ray radiation &lgr; produced by the illumination sub-system and providing the mask sub-system includes providing a patterned reflective mask for forming a projected mask pattern when illuminated by radiation &lgr;.Type: GrantFiled: July 13, 2000Date of Patent: October 15, 2002Assignee: Corning IncorporatedInventors: Claude L. Davis, Jr., Kenneth E. Hrdina, Robert Sabia, Harrie J. Stevens
-
Patent number: 6432824Abstract: In the semiconductor wafer manufacturing method of the present invention, a deteriorated layer on the surface of a semiconductor wafer which has been made flat by lapping or polishing is removed by the following dry etching. Plasma which contains a neutral active species is generated within a discharge tube. The neutral active species is separated from the plasma thus generated and is then conveyed to an orifice side of a nozzle portion of the discharge tube. The orifice is opposed to the wafer surface and the nozzle portion moves along the wafer surface while the neutral active species is sprayed from the nozzle orifice toward the wafer surface which is pre-heated. By such dry etching, the deteriorated layer on the wafer surface is removed without the occurrence of any etch pit.Type: GrantFiled: February 20, 2001Date of Patent: August 13, 2002Assignee: Speedfam Co., Ltd.Inventor: Michihiko Yanagisawa
-
Patent number: 6423650Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor substrate, involving the steps of providing the semiconductor substrate having an upper surface; roughening the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate has an Rtm of about 10 Å or more; and depositing an ultra-thin photoresist on the upper surface of the semiconductor substrate, the ultra-thin photoresist having a thickness of about 2,000 Å or less.Type: GrantFiled: August 9, 1999Date of Patent: July 23, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Marina V. Plat, Christopher F. Lyons, Michael K. Templeton, Bhanwar Singh
-
Patent number: 6423556Abstract: A method for evaluating the concentration of impurities in gases and equipment used in heat treatment of a semiconductor substrate is provided. The method includes processing a semiconductor substrate of known impurity levels in a heat treatment furnace, and measuring the impurity levels after the heat treatment processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the heat treatment process.Type: GrantFiled: November 14, 2001Date of Patent: July 23, 2002Assignee: SEH America, Inc.Inventors: Sergei V. Koveshnikov, Douglas G. Anderson
-
Patent number: 6417118Abstract: A method for improving the moisture absorption of porous low dielectric film in an interconnect structure is disclosed. The porous low-k dielectric layer such as porous hydrosilsesquioxane (porous HSQ) or porous methyl silsesquioxane (porous MSQ) is spun-on the etching stop layer. After plasma process, the porous low dielectric film has a plurality of dangling bonds. Then, the wafer is placed in the supplementary instrument with hydrophobic reactive solution. Next, the hydrophobic protection film is formed on surface and sidewall of porous low-k dielectric film to improve the moisture absorption of porous low-k dielectric film and the leakage current is reduced in subsequently processes.Type: GrantFiled: June 26, 2001Date of Patent: July 9, 2002Assignee: United Microelectronics Corp.Inventors: Jung-Chih Hu, Lih-Juann Chen
-
Patent number: 6417015Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features.Type: GrantFiled: May 29, 2001Date of Patent: July 9, 2002Assignee: Micron Technology, Inc.Inventors: Michael Nuttall, Garry A. Mercaldi
-
Publication number: 20020052096Abstract: In a cleaning method and a cleaning apparatus of a silicon substrate, after wet cleaning or etching of the substrate having a silicon surface is carried out, and during or after a pure water rinse of the substrate, an oxide film with a thickness of 10 to 30 Å is formed on the silicon surface by rinsing the substrate by pure water added with an oxidizer, and then the substrate is dried. Since drying is carried out after the oxide film is formed on the silicon surface, the occurrence of a water mark can be prevented.Type: ApplicationFiled: April 12, 2001Publication date: May 2, 2002Inventors: Hongyong Zhang, Masayuki Sakakura, Yuugo Goto