Abstract: The present invention relates to a method of manufacturing an opening through a dielectric layer. The method comprises treating a polished dielectric layer with a wet etch selectively enchancing composition, such as buffered HF, prior to the formation of a patterned photoresist to improve the lateral-to-vertical wet etch ratio.

Abstract: This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution. Both the front and back sides of the etched wafer are polished using a double sided polishing apparatus so that the front side is a mirror surface and an unevenness remains on the back side to distinguish the front and back sides, thereof. The polished wafer is cleaned.

Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C.

Abstract: A method of manufacturing a semiconductor device comprises a step of forming a transition metal layer at least on an impurity diffusion layer of a semiconductor substrate, a step of forming a transition metal silicide in a self-aligned manner on the impurity diffusion layer by applying a heat treatment and a step of removing the transition metal layer other than that on the impurity diffusion layer, wherein the native oxide film on the impurity diffusion layer is removed by a plasma etching device capable of obtaining plasmas at a density of not less than 1.times.10.sup.11 /cm.sup.3 and not more than 1.times.10.sup.14 /cm.sup.3 prior to the step of forming the transition metal layer and the transition metal layer is formed successively.

Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.

Abstract: A method for producing a small feature in a semiconductor device includes depositing a mask material on an unpatterned layer in which an ultra-narrow opening is to be formed, and then masking and etching the mask material to form a narrow opening. A spacer material is then deposited on the mask material, with spacer material settling into and covering the narrow opening. Thereafter, a portion of the spacer material is removed by etching, leaving some spacer material in the opening but exposing an ultra-narrow region of the first layer at the bottom of the opening in the mask material. The ultra-narrow region left uncovered by the spacer material is smaller than the narrow region in the mask material. Once the ultra-narrow region is uncovered, material in the first layer is removed through the ultra-narrow region, by anisotropic etching, for example, to form an ultra-narrow opening in the first layer.

Abstract: The present invention discloses a process for forming a photoresist pattern in a semiconductor device. In this process, first, a semiconductor substrate where an objective layer for the formation of a pattern is formed thereon, is provided. Afterwards, an alkaline aqueous solution is formed on the semiconductor substrate using either spray, coating, or deposition method. Thereafter, a priming step is performed. Lastly, a photoresist pattern is formed on the semiconductor substrate.

Abstract: A wafer processing method which can polish the chamfered portion of a wafer quickly, is disclosed. The processing method comprises the steps of: chamfering a peripheral portion of a wafer obtained by slicing an ingot, by grinding; lapping the wafer; etching the chamfered or lapped wafer; thereafter honing the entirety of the chamfered peripheral portion of the wafer by using a grinding stone while applying a predetermined load to the grinding stone; and thereafter polishing the entirety of the chamfered peripheral portion and the front and rear surfaces of the wafer.

Abstract: A method for preparing an epitaxial silicon wafer in a reactor is provided. The method comprises the steps of depositing an epitaxial layer on a surface of a silicon wafer contained in the reactor at an elevated temperature; purging the reactor with hydrogen after the epitaxial deposition; and cooling the reactor to an appropriate temperature which allows hydrogen passivation of the surface of the epitaxial layer. This prevents the formation of an oxide layer on the surface of the epitaxial layer for a sufficient amount of time to allow an accurate measurement of a carrier density profile of the epitaxial silicon wafer.

Abstract: An impurity adsorption layer is formed on a substrate surface and solid-phase thermal diffusion is carried out to form source and drain regions for a metal-insulator-semiconductor field-effect-transistor having lightly doped drain structure or double doped drain structure. The thus formed impurity-doped region is ultrashallow, thereby producing high speed semiconductor devices of small dimensions.

Abstract: A method for fabricating a semiconductor wafer to reduce the number of processing steps and produce low-cost wafers in a short time is disclosed. The method involves surface grinding both the front surface and back surface of a single-crystal silicon wafer which has been sliced from a rod and chamfered. In the surface grinding step, the size numbers of abrasive grains are larger than #2000 for front surface grinding, and smaller than #600 for back surface grinding. The front surface is then chemical polished as a mirror surface which satisfies the requirement of a later photolithography step. Moreover, a deformation layer formed on the back surface of the semiconductor wafer is partially etched and left to provide an extrinsic gettering function. An epitaxial layer can be formed on the front surface to make the wafer an epitaxial wafer. The method of the present invention requires fewer process steps as compared with conventional methods, thereby reducing manufacturing time and cost.

Abstract: A method for selectively applying CVD copper to metallic surfaces, that are co-located with non-metallic surfaces, is provided. The method prepares both the metal and non-metallic surfaces with a low energy ion etch of an inert gas through the use of an ion gun. The etching promotes the growth of copper on the metallic surface, and inhibits the growth on the non-metallic surface. Following an application of CVD copper, the surfaces are etched again to clean any residual copper from the non-metallic surface, and to again prepare the surfaces for another deposition of copper. Through repeated cycles of etching and copper deposition, the copper overlying the metallic surface is accumulated to achieve the desired thickness, while the non-metallic surface remains free of copper. A method is also provided for the selective deposition of copper on metallic surfaces to fill interconnects in damascene IC structures.

Abstract: A surface processing method for evaluating semiconductor substrate is intended to clean a semiconductor substrate, which has the surface of a silicon layer exposed by removing the epitaxial layer by an acid mixture, by buffered HF and then to perform SC-1 cleaning. Placing the substrate for about 2 hours after the processing, then the varying rate of the SPV value is quite stable at about 5%, so that the minor carrier diffusion length can be measured with high precision. Furthermore, the lead time of evaluating a semiconductor substrate can be significantly reduced over the prior-art method.

Abstract: A method processes a semiconductor wafer by etching the wafer, which has been smoothed by rough lapping, with alkaline solution. A rod is sliced into a plurality of wafers. The peripheral edges of the wafers are chamfered. The processed strain layers over the wafers due to chamfering are smoothed and planarized. The processed strain layers are then removed by etching with alkaline solution. The etched wafers are mirror polished. Lastly, the mirror-polished wafers are cleaned.

Abstract: Semifinished products designed as composite bodies for electronic or opto-electronic semiconductor components are known. The composite bodies are made of a disk-shaped, transparent quartz glass substrate and a wafer made of a semiconductor material. The directly bonded surfaces of the quartz glass substrate and wafer are polished before being mutually bonded. In order to create a semifinished product that resists temperatures above 900.degree. C., such as those used to produce semiconductor circuits in industrially feasible times, without raising fears of a substantial reduction of the adhesive forces, chipping of the wafers away from each other or an undesirable deformation of the composite body, the substrate quartz glass is a synthetic quartz glass with at least 10.sup.14.0 poise viscosity at 950.degree. C. which does not fall below 10.sup.12 poise at 1050.degree. C.

Abstract: On treating a substrate surface of a single crystal silicon substrate, Ge ions are preliminarily implanted into the substrate surface to be formed as a Ge-implanted silicon film on the single crystal silicon substrate. A film surface of Ge-implanted silicon film is treated by oxidizing the film surface to form a spontaneous oxide film. Subsequently, the spontaneous oxide film is subjected to a heat treatment in a reduced-pressure atmosphere to remove the spontaneous oxide film. Alternatively, the spontaneous oxide film is subjected to a heat treatment with a reducing gas of, for example, a hydrogen gas, a silane-based gas, or a GeH.sub.4 gas supplied onto the spontaneous oxide film to remove the spontaneous oxide film. Preferably, the Ge ions are preliminarily implanted into the substrate surface to be formed as Ge-implanted silicon film which consists, in atomic percent, essentially of at least 1% Ge.

Abstract: The present invention is directed to a process for fabricating a semiconductor integrated circuit device, and specifically, a process for cleaning a silicon substrate before gate silicon dioxide is formed on the silicon substrate. The gate silicon dioxide is used to form transistor gates. The process of the present invention provides a silicon/silicon dioxide interface and the bulk silicon dioxide with advantageous electrical properties. In the present process, the silicon substrate is first subjected to a stream of hydrofluoric acid (HF) vapor. The vapor HF stream is a mixture of anhydrous HF, methanol, and nitrogen. Following this, the substrate is subjected to gaseous chlorine that has been irradiated with broad band UV radiation. After the substrate has been cleaned according to the present process, a layer of silicon dioxide is grown thereon using conventional techniques such as rapid thermal oxidation (RTO).

Abstract: A method is achieved for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.

Abstract: A method of producing a high quality silicon surface prior to carrying out a selective epitaxial growth of silicon process for forming an active device region on a substrate. The process flow of the present invention eliminates the need for the sacrificial oxidation layer typically used in such processes. After the etching of a seed hole through the isolation oxide layer using a reactive ion etch a short, low power C.sub.2 F.sub.6 etch is performed. The present invention provides a simple and cost-effective way to eliminate reactive ion etch damage prior to SEG growth because the dry C.sub.2 F.sub.6 etch can be done in the same etch reactor in which the seed hole oxide etch is performed. In addition, the re-oxidation (sacrificial oxide) step is eliminated, reducing the number of process steps.

Abstract: A silicon carbide substrate is dry-polished using chromium oxide Cr.sub.2 O.sub.3, ion oxide Fe.sub.2 O.sub.3, or cerium oxide CeO.sub.2 to obtain a good polished surface free of mechanical defects and with less crystal distortion. Films are then formed on the surface to create an improved electronic device.

Abstract: A method of planarizing an interlayer dielectric layer in a semiconductor integrated circuit device is provided, which method can remove remaining parts of the dielectric layer without removing the surface of the layer itself at a high throughput. After an insulating layer is formed on a chief surface of the semiconductor substructure, an interconnection layer having interconnection lines is formed on the insulating layer. An interlayer dielectric layer is formed on the insulating layer so as to cover the interconnection layer. The dielectric layer has steps or protrusions at positions corresponding to the underlying interconnection lines of the interconnection layer. Next, a patterned resist film is formed on the interlayer dielectric layer so as to have an inverted geometric shape relative to that of the interconnection layer. Then, using the patterned resist film as a mask, the interlayer dielectric layer is selectively etched to thereby partially remove the top of the protrusions by a predetermined depth.

Abstract: A method of making semiconductor wafers can prevent processing strain on peripheral portions of wafers caused by non-wax polishing using a template. This involves mirror chamfering or etching the peripheral portions of the wafers after the non-wax polishing step.

Abstract: There is provided a high quality epitaxial water on which the density of microscopic defects in the epitaxial layer is reduced to keep the GOI thereof sufficiently high and to reduce a leakage current at the P-N junction thereof when devices are incorporated, to thereby improve the yield of such devices. In an epitaxial wafer obtained by forming an epitaxial layer on a substrate, the density of IR laser scatterers is 5.times.10.sup.5 pieces/cm.sup.3 or less throughout the epitaxial layer.

Abstract: With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom.

Abstract: A method for manufacturing a semiconductor device can reduce a micro-roughness and does not change a construction and electric characteristics of elements formed in the semiconductor device. In the method for manufacturing the semiconductor device including a pre-oxidation process in which an oxide layer is first formed on a silicon wafer, and the oxide layer is secondly eliminated to eliminate impurities on a surface of the silicon wafer, a formation of the oxide layer in the pre-oxidation process is performed in an oxidization atmosphere including H.sub.2 O and gas including germanium hydride (german --GeH.sub.4 --). Since german (GeH.sub.4) is included in the oxidization atmosphere, it is possible to reduce a softening temperature of the silicon dioxide formed in pre-oxidation, thereby decreasing the micro-roughness on the surface of the silicon wafer.

Abstract: A method for forming a crystal comprises implanting ions on the surface of a substrate to change the ion concentration in the depth direction of said substrate surface by said ion implantation, subjecting a desired position of said substrate surface with a sufficient area for crystal growth from a single crystal to exposure treatment to/he depth where an exposed surface having larger nucleation density than the nucleation density of the surface of said substrate is exposed, thereby forming a nucleation surface comprising said exposed surface exposed by said exposure treatment and a nonnucleation surface comprising the surface of the substrate remaining without subjected to said exposure treatment, applying a crystal growth treatment for crystal growth from a single nucleus on said substrate to grow a single crystal from said single nucleus or form a polycrystal of a mass of single crystals grown from said single nucleus.

Abstract: An improved method for applying a primer to a wafer surface prior to coating the wafer with photoresist is provided. The method comprises priming a wafer with HMDS, removing the wafer from the priming chamber, and closing the chamber. Next, the chamber, piping and primer source are evacuated. The bubbler canister, piping and wafer chamber are held at a pressure of about 15 inches H.sub.2 O while the priming tool is idle between wafer priming operations. By maintaining the vaporizer, piping and wafer chamber at a partial vacuum, the primer will be prevented from condensing and forming harmful droplets on the wafer surface. The invention prevents primer condensation from forming on the wafer, thus improving photolithographic yields and device yields.

Abstract: Significant reduction in the cost of fabrication of shallow junction, Schottky or similar semiconductor devices without sacrifice of functional characteristics, while at the same time achieving the advantages is achieved, after the non-polishing cleaning step is essentially performed, by subjecting the substrate to conditions which move disadvantageous factors within said substrate into a space substantially at said surface, followed by substantially removing said factor-containing space from said substrate chemical removal step, followed etching and vapor deposition steps. Although these new steps add time, and therefore cost, to the overall process, the devices under discussion when produced by known industry processes require yet more time, and involve yet more expense, so that the total process represents a substantial reduction in the cost of their manufacture while producing devices which are the equivalent or superior in electrical performance to such devices which are made by known industry processes.

Abstract: A method for making an improved metal silicide layer on a silicon substrate by plasma bombardment of the substrate with Ne ions to remove the native oxide without damage or significant implantation of Ne atoms into said silicon, depositing a metal layer over the Ne etched surface and then rapidly thermally causing the metal layer to react with the underlying silicon.

Abstract: Contaminant particles in a vacuum plasma processing chamber can be removed from the surface of a substrate in the chamber by first reducing the pressure in the chamber so as to elevate the particles above any obstruction about the substrate, including a clamping ring and the like, maintaining a plasma from a gas fed to the chamber so that the particles are in the plasma, and then increasing the gas flow to the chamber so as to sweep the particles out of the chamber through the exhaust system of the processing chamber while maintaining a plasma in the chamber.