Abstract: An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

Abstract: A method comprising adjusting a first relative position between a substrate and a fabrication unit by a first shift value, forming a first pattern relative to a first pattern instance on the substrate subsequent to adjusting the first relative position by the first shift value, and calculating a second shift value using a first displacement between the first pattern and the first pattern instance and a second displacement between a second relative position of the first pattern instance with respect to a second pattern instance is provided.

Abstract: A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at an ISO level, and forming a dummy active region pattern substantially adjacent to a vernier key pattern in the scribe lane during formation of the vernier key pattern, wherein the dummy active region pattern is spaced apart from the vernier key pattern by a known distance. Preferably, the active region pattern and the dummy active region pattern are formed prior to the STI CMP process.

Abstract: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is exposed to an ion implantation beam including a dopant species to dope and change an etching rate of the first subset. The substrate is annealed to activate the dopant species, and the semiconductor surface is etched to remove the sacrificial oxide layer and to level the first subset to a first level and to create a topology such that the first subset has a first level differing from a second level of a surface portion of the marker structure different from the first subset.

Abstract: In a method according to one embodiment of the invention, a plurality of markers are printed in resist on a substrate at a range of angles relative to a crystal axis of the substrate. The markers are etched in to the substrate using an anisotropic etch process, such that after the etch the apparent positions of the markers are dependent on their orientation relative to the crystal axis. The apparent positions of the markers are measured, and from this information the orientation of the crystal axis is derived.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate and forming a projecting alignment mark. The substrate includes an insulating layer and a semiconductor layer on the insulating layer, and the substrate includes device areas and a scribe line area which surrounds the device area in the semiconductor layer. The projecting alignment mark is formed on the scribe line area.

Abstract: The invention relates to a method for creating a pattern on a substrate comprising a first alignment structure, using an elastomeric stamp comprising a patterning structure and a second alignment structure. The method comprises a moving step for moving the elastomeric stamp towards the substrate, and a deformation step for deforming the patterning structure with a tensile or compressive force generated by cooperation of the first alignment structure and the second alignment structure.

Abstract: In forming a mask pattern on a circuit board, a mask pattern of N-layer structure is formed in a region where the mechanical strength of the circuit board needs to be increased. N photosensitive layers are first stacked on a substrate so that they becomes lower in sensitivity from the first photosensitive layer toward the Nth photosensitive layer. In the first photosensitive layer (bottom layer), a first pattern is formed and has the same shape as a predetermined pattern to be formed on the circuit board. In the Kth photosensitive layer (N?K?2), a Kth pattern is formed so that the Kth pattern is smaller than a (K?1)st pattern formed in the (K?1)st photosensitive layer and arranged inside the (K?1)st pattern.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

Abstract: An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

Abstract: An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on the first layer. Portions of the second and/or third layer are selectively removed from regions in and around the first overlay mark. A second overlay mark is formed and aligned to the first overlay mark. The alignment between the second overlay mark and first overlay mark may be measured with an attenuated error due to reflection and refraction or due to an edge profile shift of the first overlay mark.

Abstract: A robust single-chip hydrogen sensor and a method for fabricating such a sensor. By utilizing an interconnect metallization material that is the same or similar to the material used to sense hydrogen, or that is capable of withstanding an etchant used to pattern a hydrogen sensing portion, device yields are improved over prior techniques.

Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.

Abstract: The present invention is a process for transfer of a pattern of material from a donor substrate to a receiver substrate by lamination. The pattern of the transferred material is defined by an aperture in a mask interposed between the donor and receiver during lamination. The technique is compatible with flexible polymer receiver substrates and is useful in fabricating thin film transistors for flexible displays.

Abstract: Flip-chips are aligned by making a fiducial in the “top” chip that is translucent/transparent to light of a wavelength shorter than infrared, and at least one corresponding fiducial in the “bottom” chip. The top-chip fiducial may be made of a transparent or translucent material, its shape may be outlined by an opaque material, or it may be formed by etching through the top chip. The bottom-chip fiducial may be reflective of the light which is transparent/translucent to the fiducial in the top chip, in which case alignment can be achieved by employing at least one video camera which is located above the top chip. Alternatively, the fiducial in the bottom chip may also be transparent/translucent to the light, in which case alignment can be achieved by having the video camera located below the bottom chip. The chips are aligned by aligning the fiducials as seen by the video camera.

Abstract: A method for forming uniform, sharply defined periodic regions of reversed polarization within a unidirectionally polarized ferroelectric material proceeds as a two-step process. First, alignment keys are formed on upper and lower planar surfaces of a unidirectionally polarized ferroelectric material by producing a spaced pair of alignment key shaped domain reversed regions and etching alignment key shaped notches in the upper and lower surfaces where the domain reversed regions intersect the surface planes. These notches, being vertically aligned between the upper and lower surfaces, are then used to align photomasks over a surface coating of photoresist formed directly on the material surface or on SiO2 layers coating the material surface.

Abstract: A thin-film semiconductor substrate includes an insulative substrate, an amorphous semiconductor thin film that is formed on the insulative substrate, and a plurality of alignment marks that are located on the semiconductor thin film and are indicative of reference positions for crystallization.

Abstract: The present invention relates to a wafer alignment method.

Abstract: A method of forming an overlay mark is provided. A first material layer is formed on a substrate, and then a first trench serving as a trench type outer mark is formed in the first material layer. The first trench is partially filled with the first deposition layer. A second material is formed over the first trench and the first deposition layer. A second trench is formed exposing the first deposition layer within the first trench. The second trench is partially filled with a second deposition layer forming a third trench. A third material layer is formed on the substrate to cover the second deposition layer and the second material layer. A step height is formed on the third deposition layer between the edge of the first trench and the center of the first trench. A raised feature serving as an inner mark is formed on the third deposition layer.

Abstract: A semiconductor chip is formed by dividing a semiconductor wafer by use of the laser dicing technique. The semiconductor chip has a laser dicing region on the side surface thereof. A dummy wiring layer is formed along the laser dicing region on the surface layer of the laser dicing region. A laser beam is applied to the dummy wiring layer to divide the semiconductor wafer.

Abstract: A method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method is disclosed. To fabricate the apparatus, a device chip including a substrate and at least one circuit element on the substrate is fabricated. Also, a cap is fabricated. The cap is attached to the device chip using single phase metal alloy to achieve sealed cavity over the circuit element. The single phase metal alloy allows the cap to be diffusion bonded to the device chip at a higher diffusivity thus allowing diffusion at a lower temperature, lower pressure, shorter period, or a combination of these.

Abstract: This invention generally relates to semiconductor devices, for example lasers and more particularly to single frequency lasers and is directed at overcoming problems associated with the manufacture of these devices. In particular, a laser device is provided formed on a substrate having a plurality of layers (1,2,3,4,5), the laser device comprising at least one waveguide (for example a ridge) established by the selective removal of sections of at least one of the layers. Wherein alignment features are provided on the device to facilitate subsequent placement.

Abstract: A tape carrier package with a widow that is capable of confirming an alignment extent between the tape carrier package and a print wiring board in bonding the tape carrier package mounted with an integrated circuit on the liquid crystal panel and the print wiring board. In the package, the integrated circuit is mounted onto a base film. Input pads are connected to the integrated circuit and formed on the base film. Dummy pads are formed at the left and right side thereof not to be connected to the integrated circuit. Windows are provided by opening the base film adjacent to the dummy pads to expose at least two of said dummy pads.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: In a method and system for placing an IC (integrated circuit) die onto a package substrate, a first reference is determined after locating a first fiducial on the package substrate, and a second reference is determined after locating a second fiducial on the package substrate. The IC die is placed onto the package substrate to be aligned with respect to the first and second references of the first and second fiducials that are comprised of a plurality of markings such as a plurality of dots.

Abstract: A semiconductor integrated circuit device includes: Si substrate; multilevel interconnect layer formed on the Si substrate; and dielectric layer formed on the multilevel interconnect layer. External-component-connecting wire, ordinary wire, fuse wire, stepper alignment mark, and target mark are formed out of an identical copper film in the uppermost metal layer. External-component-connecting pad electrode, testing-processing alignment mark, and stepper alignment mark are formed out of an identical aluminum alloy film on the dielectric film. In laser-machining the fuse wire, alignment using the target mark formed in the metal layer including the fuse wire reduces alignment errors caused from the machining.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: A method for manufacturing a semiconductor substrate including a mask aligning trench. The method includes forming the mask aligning trench and an element partitioning trench. The element partitioning and mask aligning trenches are filled with insulation. The insulation in the element partitioning trench is masked and the insulation in the mask aligning trench is etched. As a result, a residue of the insulation in the mask aligning trench is below the upper edge of the mask aligning trench. The mask aligning trench is easily detected. Thus, positioning a patterning mask on the substrate can be performed accurately.

Abstract: A semiconductor substrate having an upper layer and an alignment mark structure formed on a surface region of the upper layer, the surface region defined by opposite first and second parallel sides extending along the upper layer, outer side walls extending upwardly from the upper layer and extending lengthwise along the side, and are defined lengthwise by alternating first and second wall portions, each of the first wall portions is spaced farther from the first side of the surface region than is each of the second wall portions, and an alignment pattern defined by openings in the alignment mark structure.

Abstract: Disclosed is a substrate for semiconductor package and a wire bonding method using thereof. The substrate is provided with at least one reference mark on its surface to check a loading position and a shift state of a solder mask. The reference mark is composed of a combination of a reference pattern and a solder mask opening and is positioned in any location on an outer peripheral edge of a die attachment region. The reference mark may take various shapes. A method for checking a solder mask shift using the reference mark includes comparing a design value of the reference pattern and the solder mask opening with the reference pattern and the solder mask opening, which are formed in an actual material. After the solder mask shift is calculated, a wire bonding coordinate is newly constructed in consideration of the solder mask shift. This minimizes the wire bonding error.

Abstract: In a method and system for inspecting alignment between an IC (integrated circuit) die and a package substrate, a plurality of fiducials are located on the package substrate for determining a plurality of references. A center point of the package substrate is determined from the plurality of references. In addition, whether a center point of the IC die is aligned to the center point of the package substrate within an acceptable range is determined.

Abstract: The invention relates to a method of manufacturing an electronic component (1), in particular a semiconductor component (1), which is provided with electric connection regions (2), wherein a mark (M), such as a type number, is provided on a surface thereof by means of laser radiation (3). In a method according to the invention, the component (1) is attached with one (4) of its sides (4, 7) to a foil (5) by means of an adhesive layer (6), and the component is provided, on said side (4), with the mark (M) through the foil (5) and the adhesive layer (6). In this manner, a large number of components (1) can be readily provided with a mark (M) without undue handling, and the marking operation can be readily integrated in the complete manufacturing process of the components. Surprisingly it has been found that marking through a radiation-absorbing double layer (5, 6) is very well feasible.

Abstract: The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.

Abstract: A structure is obtained having a semiconductor substrate, the structure having an upward protruding feature (140). A first layer (160) is formed on the structure. The first layer (160) has a first portion (170.1) protruding upward over the protruding feature (140). Then a second layer (1710) is formed over the first layer (160) such that the first portion (170.1) is exposed and not completely covered by the second layer (1710). The first layer (160) is partially removed selectively to the second layer to form a cavity (1810) at the location of the first feature (140). A third layer (1910) is formed in the cavity. Then at least parts of the second layer (1710) and the first layer (160) are removed selectively to the third layer (1910). In some embodiments, self-aligned features are formed from the first layer (160) over the sidewalls of the first features (140) as a result.

Abstract: A mark configuration for the alignment and/or determination of a relative position of at least two planes in relation to one another in a substrate and/or in layers on a substrate during lithographic exposure, in particular, in the case of a wafer during the production of DRAMs, includes a mark structure, and at least one layer of a definable thickness underneath the mark structure for adjusting the physical position of the mark structure relative to a reference plane in or on the substrate. Also provided is a wafer having such a configuration and a process for providing such a configuration. The invention allows a mark configuration to have mark structures exhibiting good contrast regardless of the design or the process conditions.

Abstract: A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: A method of maintaining photolithographic precision alignment for a wafer after being bonded, wherein two cavities are formed at the rear surface of a top wafer at the position corresponding to alignment marks made on a bottom wafer. The depth of both cavities is deeper than that of a final membrane structure. The top wafer is then bonded to the bottom wafer which already has alignment marks and a microstructure. This bonded wafer is annealed to intensify its bonding strength. After that, a thinning process is applied until the thickness of the top wafer is reduced to thinner than the cavity depth such that the alignment marks are emerged in the top wafer cavities thereby serving as alignment marks for any exposure equipment.

Abstract: A method of manufacturing bonded substrates. The method includes providing a metallic substrate. The metal substrate has a predetermined thickness. The method also includes bonding a first thickness of compound semiconductor material overlying the metallic substrate and reducing a thickness of the first thickness of compound semiconductor material to a second thickness. The method includes forming one or more via structures through a portion of the second thickness of compound semiconductor material to a portion of the underlying metal substrate, whereupon the via structure electrically connects to the metal substrate.

Abstract: Disclosure is a method for forming an alignment pattern of a semiconductor device.

Abstract: A method of manufacturing an alignment mark structure and aligning a substrate includes providing a semiconductor substrate having an upper layer, the alignment mark structure being formed on a surface region of the upper layer. The method includes providing the surface region as having opposite first and second parallel sides extending along the upper layer, with outer side walls extending upwardly from the upper layer and extending lengthwise along the side. The outer side walls are provided lengthwise with alternating first and second wall portions, each of the first wall portions being spaced farther from the first side of the surface region than each of the second wall portions. An alignment pattern is defined by providing openings in the alignment mark structure.

Abstract: An alignment mark section on a semiconductor substrate has two grooves which are filled with silicon oxide. The surface of the portion of the semiconductor substrate sandwiched by these grooves is lower than other portions of the semiconductor substrate to produce a step having a predetermined depth in the alignment mark section.

Abstract: A method of removing organic particles from a registration mark on a semiconductor wafer. The method comprises providing a semiconductor wafer comprising at least one registration mark at least partially filled with organic particles. The at least one registration mark has a trench width from approximately 1.0 ?m to approximately 3.0 ?m. The semiconductor wafer is exposed to a cleaning solution comprising tetramethylammonium hydroxide and at least one surfactant, such as an acetylenic diol surfactant. The semiconductor wafer is exposed to an ultrasonic or megasonic vibrational energy. A semiconductor wafer previously subjected to a chemical mechanical planarization treatment and having a reduced amount of organic particles in a registration mark is also disclosed.

Abstract: One embodiment of the present invention provides a system that facilitates measuring an alignment between a first semiconductor die and a second semiconductor die. The system provides a plurality of conductive elements on the first semiconductor die and a plurality of conductive elements on the second semiconductor die. The plurality of conductive elements on the second semiconductor die have a different spacing than the plurality of conductive elements on the first semiconductor die, so that when the plurality of conductive elements on the first semiconductor die overlap the plurality of conductive elements on the second semiconductor die, a vernier alignment structure is created between them. The system also provides a charging mechanism configured to selectively charge each of the plurality of conductive elements on the first semiconductor die, wherein charging a conductive element on the first semiconductor die induces a charge in one or more conductive elements on the second semiconductor die.

Abstract: An overlay mark for determining the relative position between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The overlay mark includes a plurality of coarsely segmented lines that are formed by a plurality of finely segmented bars. In some cases, the coarsely segmented lines also include at least one dark field while being separated by a plurality of finely segmented bars and at least one clear field. In other cases, the coarsely segmented lines are positioned into at least two groups. The first group of coarsely segmented lines, which are separated by clear fields, are formed by a plurality of finely segmented bars. The second group of coarsely segmented lines, which are separated by dark fields, are also formed by a plurality of finely segmented bars.

Abstract: The present invention includes a residue-free overlay target, as well as a method of forming a residue-residue free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers, and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

Abstract: A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.

Abstract: In this invention a coating of unexposed photoresist is used to protect from semiconductor processing the area immediately above a zero layer alignment mark used for a wafer stepper alignment. The entire surface of a wafer is coated with photoresist and all shot sites on the surface of a wafer including those containing the zero layer alignment marks are exposed with circuit patterns. Before the exposed areas of photoresist are removed, a protective coating of unexposed photoresist is applied to the surface of the wafer immediately above the alignment marks but within the boundaries of the shot site. The wafer is processed in the areas outside of the protective coating of photoresist including the shot site containing alignment marks. The area under the protective coating is not processed. This maintains a clear and concise view of the alignment marks. The area beyond the protective coating is processed along with the other shot sites.

Abstract: A photomask or reticle including a unique set of alignment attributes at separate and distinguishable field points is put in the reticle plane of a photolithographic projection system. The reticle pattern is exposed onto a resist coated wafer or substrate and processed through the final few steps of the photolithographic process. The resulting array of alignment attributes are then measured using a standard optical overlay metrology tool. The overlay tool is driven by a set of software instructions. By comparing the resulting overlay data to the placement error encoded on the reticle it can determined if the data has been read or displayed in the correct order.

Abstract: An alignment or overlay mark with improved signal to noise ratio is disclosed. Improved signal-to-noise ratio results in greater depth of focus, thus improving the performance of the alignment mark. The alignment mark comprises a zone plate having n concentric alternating opaque and non-opaque rings. Light diffracted by either the odd or even rings are cancelled while light diffracted by the other of the odd or even rings are added.