Abstract: A system and method of determining alignment error between lithographically produced integrated circuit fields on the same and different lithographic levels comprises creating a first and second level field layers each having a plurality of integrated circuit fields and associated set of metrology structures adjacent and outside each integrated circuit field. In each level, a metrology structure associated with one integrated circuit field is located to nest with another metrology structure associated with an adjacent circuit field when both are properly aligned on the same lithographic level. Overlay metrology structures are provided on one level to nest with metrology structures of another level when the integrated circuit fields are properly aligned on different lithographic levels.

Abstract: A method of producing an exposure mask by carrying out at least two times of exposure on a mask substrate, wherein at a first time of pattern exposure, alignment marks to be reference for positioning at a second time of exposure are exposed onto a position on the mask substrate with positional error by substrate deformation obtained in advance with an exposure apparatus to be used corrected, and at a second time of pattern exposure, positional error by substrate deformation obtained in advance with the exposure apparatus to be used is corrected and thereby the position of the alignment marks are detected, and on the basis of the detected position of the alignment marks, the positions between exposure patterns are aligned.

Abstract: Method and apparatus for suction-holding a semiconductor pellet on a positioning stage of a bonding apparatus without causing the pellet to be misaligned after positioning thereof including a suction force control device. The suction force control device comprises a suction-switching electromagnetic valve, a suction force-adjusting electromagnetic valve, a vacuum source, a compressed air source and a throttle valve so that a semiconductor pellet is held on a positioning stage by a suction force that is weak enough that a positioning claw can move the semiconductor pellet for positioning; and upon completion of the positioning, the semiconductor pellet is held to the positioning stage by a suction force that is stronger than the weak suction force used for positioning.

Abstract: The method for controlling layers alignment in a multi-layer sample (10), such a semiconductors wafer based on detecting a diffraction efficiency of radiation diffracted from the patterned structures (12, 14) located one above the other in two different layers of the sample.

Abstract: A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.

Abstract: A substrate and a method for fabricating variable quality substrate materials are provided. The method comprises: selecting a first mask having a first mask pattern; projecting a laser beam through the first mask to anneal a first area of semiconductor substrate; creating a first condition in the first area of the semiconductor film; selecting a second mask having a second mask pattern; projecting the laser beam through the second mask to anneal a second area of the semiconductor film; and, creating a second condition in the second area of the semiconductor film, different than the first condition. More specifically, when the substrate material is silicon, the first and second conditions concern the creation of crystalline material with a quantitative measure of lattice mismatch between adjacent crystal domains. For example, the lattice mismatch between adjacent crystal domains can be measured as a number of high-angle grain boundaries per area.

Abstract: In the three-dimensional integration of integrated circuits, a thinned semiconductor substrate is arranged on a second semiconductor substrate and is mechanically and electrically connected thereto. To that end, in the second, thinned semiconductor substrate, continuous contact holes are formed proceeding from a substrate rear side as far as a first metal wiring plane on a substrate front side. In order to align the contact holes with the structures arranged on the front side, a structure is arranged on the front side of the substrate, which can be used as an alignment mark on the front side. The structure is overgrown with a useful layer and uncovered proceeding from the rear side of the substrate, so that the structure can also be used as an alignment mark from the rear side. This avoids an alignment error between the structures arranged on the front side and the rear side.

Abstract: The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive metal layer and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.

Abstract: A method for manufacturing a highly reliable alignment mark in which by-products do not form at an aligning mark position during patterning. In this method, an intermediate layer is disposed on an upper layer of a first wiring to protect the first wiring. Then, a filling material is coated thereon to fill in a through hole. Thereafter, a plug is formed by etch-backing, and a second wiring is formed.

Abstract: A resist pattern for alignment measurement being shrunk by a heat flow comprises a plurality of positive type or negative type line patterns. Widths of spaces between the line patters are greater than twice those of the line patterns. Alternatively, the resist pattern comprises a box-shaped or slit-shaped measurement pattern and a pair of box-shaped or slit-shaped auxiliary patterns provided inside and outside the measurement pattern, respectively.

Abstract: A semiconductor device with an enhanced registration accuracy photo-mask used for manufacturing the device and a registration accuracy enhancement method are provided, by detecting lens aberration which causes problems in the process of manufacturing a semiconductor device. The semiconductor device includes an auxiliary mark including an inner mark having stepped portions with four sides as stepped portions to be detected and an outer mark having stepped portion as stepped portions to be detected, provided approximately parallel to stepped portions along four sides of the inner mark.

Abstract: A method for preventing thermal stress and the shifting of alignment marks during semiconductor processing including providing a semiconductor wafer having a first selected portion for fabricating integrated circuitry and a second non-fabrication portion including alignment marks, introducing dopant into said first and second portions, when dopant is required to be introduced in said first portion, thereby increasing radiant energy absorptivity and decreasing radiant energy transmissivity in both portions such that the thermal emissions detected.at the portions result in no significant temperature variation between portions during heating. Therefore thermal stress and shifting of alignment marks are prevented.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: An alignment device for permitting a deposition mask having a plurality of magnetic mask segments to be positioned relative to a substrate to facilitate simultaneous deposition of organic material on to the substrate which will be part of an organic light emitting device.

Abstract: High contrast alignment marks that can be flexibly located on a semiconductor wafer are disclosed. The wafer has a first layer and a second layer. The first layer has a light-dark intensity and a reflectivity. The second layer is over the first layer, and has a light-dark intensity substantially lighter than that of the first layer, and a higher reflectivity than that of the first layer. The first layer may be patterned to further darken it. The second layer contrasts visibly to the first layer, and is patterned to form at least one or more alignment marks within the second layer. The first layer may be a metallization layer, such as titanium nitride, whereas the second layer may be a metallization layer, such as aluminum or copper.

Abstract: A method for making a semiconductor structure, includes patterning a photoresist layer to form both a zero marks pattern and a well implant mask pattern. The photoresist layer is on a region of a substrate.

Abstract: A linear image sensor integrated circuit has a semiconductor substrate having a pixel region and a scribe region adjacent to the pixel region. A diffusion layer is disposed in the pixel region of the semiconductor substrate. A PN junction is formed between the semiconductor substrate and the diffusion layer for receiving light. A passivation film covers the PN junction and is disposed over a surface of the semiconductor substrate except for a portion of the surface thereof in the scribe region.

Abstract: A method of forming fine patterns in a semiconductor device through a double photo lithography process. A layer to be etched and a hard mask layer are sequentially formed on a semiconductor substrate. A first photo resist pattern is formed on the hard mask layer. A first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After the first photo resist pattern is removed, a second photo resist pattern is formed on the resultant structure. A second hard mask layer pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. The layer to be etched is then etched using the second hard mask layer pattern after the second photo resist pattern has been removed, resulting in patterns have line edges without rounding.

Abstract: An exposure apparatus is provided for a semiconductor wafer, which includes a light source, a body containing the light source, and an illumination optical system for directing light from the light source to the semiconductor wafer. A holder in the body holds a reticle and a zero layer reticle is disposed between the illumination optical system and the light source for masking light from the light source. The zero layer reticle has a pellicle frame and a pellicle film with a zero layer image placement indicator thereon.

Abstract: Alignment marks and a method of forming the alignment marks are provided. The method includes the steps of forming a first alignment mark in an alignment mark forming area on the substrate, forming an opaque layer that is opaque to the alignment light above the alignment mark forming area where the first alignment mark is formed, substantially flattening a surface of the opaque layer, and forming a second alignment mark on a side where the alignment light is incident with respect to the flattened opaque layer.

Abstract: A method for forming a protrusive alignment-mark in semiconductor devices is disclosed. A photolithography process is performed to form a photoresist layer on a substrate wherein the substrate has an element region and an alignment region, and the photoresist layer has an element photoresist region and an alignment photoresist region. Afterwards, a first dielectric layer is deposited on the element photoresist region and the alignment photoresist region. The excess portion of first dielectric layer above the photoresist layer is removed such that the photoresist layer is coplanar with the first dielectric layer and thus the photoresist layer is exposed. The photoresist layer on the element region and said alignment region is stripped to form a protrusive alignment-mark on the alignment region.

Abstract: A method is disclosed for aligning structures on first and second opposite sides of a wafer. First one or more transparent islands are formed on the first side of the wafer at an alignment location. The transparent islands have an exposed front side and a rear side embedded in the wafer. At least one alignment mark is formed on the front side of the transparent island. An anisotropic etch is performed through the second side of said the to form an opening substantially reaching the back side of the transparent island. A precise alignment is then carried out on the alignment mark through the opening and the transparent island. In this way a very precise alignment can be carried out on the back side of the wafer for manufacturing MEMS structures.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: The present invention advantageously provides a method for retaining a substantially transparent dielectric above alignment marks during polishing of the dielectric to ensure that the alignment marks are preserved for subsequent processing steps. According to an embodiment, alignment marks are etched into a semiconductor substrate. Thereafter, a pad oxide layer is deposited across the substrate surface, followed by the deposition of a first nitride layer. Isolation trenches which are deeper than the alignment mark trenches are formed spaced distances apart within the substrate. Optical lithography may be used to define the regions of the first nitride layer, the pad oxide layer, and the substrate to be etched. The isolation trenches thus become the only areas of the substrate not covered by the pad oxide layer and the first nitride layer. A substantially transparent dielectric, e.g., oxide, is then deposited across the semiconductor topography to a level spaced above the first nitride layer.

Abstract: Disclosed is a thin film deposition apparatus for depositing a thin film on a display panel including a deposition source having a groove in one surface wherein the groove is filed with a thin film material to be deposited on the panel, a heater applying heat to the deposition source so as to sublimate the thin film material, and a mask loaded on the deposition source so as to cover the groove of the deposition source, the mask having a plurality of holes to adjust a deposition quantity of the thin film material deposited on the panel.

Abstract: In a phase shift mask blank comprising a transparent substrate and a phase shift film thereon, after the phase shift film is formed on the substrate, it is surface treated with ozone water having an ozone concentration of at least 1 ppm. The resulting phase shift film is of quality in that it experiences minimized changes of phase difference and transmittance upon immersion in chemical liquid during subsequent mask cleaning step or the like.

Abstract: A soldering ball fabrication method includes the steps of: (1) drawing a metal wire rod into the desired thickness, (2) cutting the metal wire thus obtained into pieces subject to the desired length, (3) washing the pieces of metal wire to remove dust, (4) processing the pieces of metal wire into balls, (5) washing the balls thus obtained, (6) using a screen to select the balls, (7) inspecting selected balls, and (8) obtaining approved soldering balls.

Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.

Abstract: A semiconductor wafer has an alignment mark for use in aligning the wafer with exposure equipment during the manufacturing of a semiconductor device. The wafer is made by forming a chemical mechanical polishing target layer over an alignment mark layer, chemically-mechanically polishing the target layer to planarize the same, and prior to forming the chemical mechanical polishing target layer over the alignment mark layer, forming a dense pattern of lands or trenches in the alignment layer of dimensions and an inter-spacing preselected to inhibit a dishing phenomenon from occurring in the target layer as the result of its being chemically-mechanically polished. The lands or trenches may be disposed in at least a 2×2 array of rows and columns.

Abstract: Within a chemical mechanical polish (CMP) planarizing method for forming a planarized layer there is first provided a microelectronic substrate having a topographic mark formed therein. There is then formed over the microelectronic substrate and covering the topographic mark a blanket conformal layer which forms a replicated topographic mark at the location of the topographic mark. There is then formed over the blanket conformal layer and the replicated topographic mark a patterned negative photoresist layer of areal dimensions minimally sufficient to encapsulate the replicated topographic mark. There is then chemical mechanical polish (CMP) planarized the patterned negative photoresist layer and the blanket conformal layer to form a chemical mechanical polish (CMP) planarized patterned negative photoresist layer and a chemical mechanical polish (CMP) planarized blanket conformal microelectronic layer.

Abstract: A method of arraying self-scanning light-emitting element array chips is provided, in which it is possible to remove defective chips completely. A plurality of self-scanning light-emitting array chips in a zigzag manner on a substrate, each chip being rectangular and comprising an array of light-emitting elements arrayed in a line facing to one end of the chip and a plurality of bonding pads provided on the other end of the chip. The plurality of chips are arrayed in such a manner that one ends of neighboring chips are arranged without overlapping in an array direction of chips so that an array pitch of chips is constant, and the other ends of the chips are arranged with overlapping in a direction perpendicular to an array direction of chips so that an array pitch of chips is constant.

Abstract: The present invention is directed to a method of performing alignment during processing of a semiconductor device. The method is comprised of: performing alignment registration on a plurality of layers on said semiconductor device; measuring misregistration of said alignment registration in relation to a predetermined standard alignment key; and generating an offset for a subsequent process layer on said semiconductor using said measure misregistration.

Abstract: A semiconductor structure and a method for reducing charge damage during plasma etch processing are disclosed. Structures (22, 26, 28) for accumulating charge during plasma etch processing are provided on a semiconductor wafer (10), the structures (22, 26, 28) being electrically connected to device structures (30, 32).

Abstract: The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20′) is disclosed. The information may be marked by way of laser marking at one or more locations (10) along a flat portion (14) or bevel (12t, 12b) of the edge (E) of the wafer (20, 20′). The wafer marking (10) may be encoded, for example by way of a 2-D bar code. A system (30) for reading the identification information from wafers (20, 20′) in a carrier (32) is also disclosed. The system (30) includes a sensor (36) for sensing reflected light from the wafer markings (10) along the wafer edge (E), and for decoding identification and orientation therefrom. A motor (38), under the control of feedback (RFB) from the sensor (36), rotates the wafers (20, 20′) by way of a roller (39) until the wafer marking (10) is in view by the sensor (36). A processing system (40), which includes a rotatable chuck (41) upon which the wafer (20, 20′) is placed, is also disclosed.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: A method for the fabrication of a semiconductor device which prevents the occurrence of a defective die and an erroneous alignment otherwise invoked by a difference in polishing level between an edge and a central portion of a wafer. The method comprises steps of forming a group of dummy patterns around an alignment key of edges of a wafer, wherein the wafer is obtained by forming the capacitor on the cell region, and the dummy pattern has the same elevation as the capacitor formed on the cell region; disposing an interlayer insulating film on a resulting structure obtained after the forming process; and performing a chemical-mechanical polishing on the interlayer insulating film. Further, the process of forming the group of dummy patterns may be performed while forming the capacitor on the cell region.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: An overlay key includes a first overlay key having a first main overlay pattern and a first auxiliary pattern, and a second overlay key having a second main overlay pattern and a second auxiliary overlay pattern, the second auxiliary overlay pattern formed at a location corresponding to the first auxiliary overlay pattern.

Abstract: A shot configuration measuring mark transferred onto a resist film formed on a semiconductor wafer includes four straight-line marks arranged in parallel to each other and a centerline between outer two of the four straight-line marks is coincident with a centerline between inner two of the four straight-line marks.

Abstract: A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a notch (11) having a wall disposed in the wafer and extending to the perimeter which includes a preferably rounded apex (5) interior of the perimeter and a pair of rounded intersections (7, 9) between the wall and the perimeter. The notch is formed with a tool (23) for forming rounded corners in the semiconductor wafer which includes a body of a material having a hardness greater than the semiconductor wafer which has a generally rounded or paraboloidally shaped front portion having a forwardmost tip (25) portion and a wing portion (27) extending outwardly from the body and having a taper narrowing in the direction of the forwardmost tip portion. The wing portion can be one or more spaced apart wing members or the wing portion can be a single member which extends completely around the tool axis.

Abstract: A process for device fabrication, including coating a wafer with a layer including SiO2, SiNx, and a first resist, defining shallow trench isolation and alignment patterns in the first resist, transferring the first resist pattern into the SiO2 and SiNx, removing the first resist, etching trenches to a depth suitable for shallow trench isolation, coating the wafer with a second photoresist, defining open areas around alignment-marks, etching alignment mark trenches to a depth greater than the trench depth, suitable for alignment mark detection, removing the second resist and the SiNx, depositing SiO2 to fill the trenches for shallow trench isolation and partially fill the alignment mark trenches for alignment mark detection; and performing chemical mechanical polishing, leaving shallow trench isolation features and topographical alignment marks.

Abstract: An alignment mark design has a metal plateau and a metal material formed over a substrate. The metal plateau is within a first dielectric layer. Openings within a second dielectric layer above the first dielectric layer are filled with a metal material. The metal material and the second dielectric layer alternate so that a part of the exposure light passing through the second dielectric layer between sections of the metal material can be reflected into an alignment system by the metal plateau.

Abstract: A new processing sequence is provided for the creation of openings in layers of dielectric. Over a semiconductor surface are successively deposited an etch stop layer, a layer of dielectric and a hard mask layer. An opening is etched in the hard mask layer, the main opening is etched through the layer of dielectric and the etch stop layer. The surface is wet cleaned, after which a thin layer of silicon oxide is CVD deposited over the inside surfaces of the created opening. This thin layer of CVD oxide is subjected to argon sputter, providing of the critical dimensions of the upper region of the opening. Then the process continues with the deposition of the barrier metal, the filling of the opening with a conducting material to create the metal plug and the polishing of the surface of the deposited conducting material.

Abstract: In the construction of electronic devices with one or more flip chips and, in some cases, one or more leadless components, mounted on a substrate, the interconnections are made with conductive adhesive deposited using specialized masks. A magnetic metal mask fabricated of a membrane of magnetic material is placed temporarily onto the face of a semiconductor wafer or of a circuit or other substrate. When properly positioned with respect to the wafer or substrate, such as by relational guide holes, the mask is held in place by the magnetic forces produced by a controllable electromagnet. Contact pad openings in the magnetic metal mask are formed by suitable means such as laser cutting or photo-etching. The magnetic metal mask may include a flexible interface layer on the side facing the wafer or substrate to assure tight sealing thereto, so as to reduce smearing and bridging of the conductive adhesive paste and avoid bridging between contact pads that might otherwise occur during deposition of the paste.

Abstract: In order to align a mask to a specific crystal plane in a wafer, a first mask having at least one alignment structure is deposited on the wafer surface. The alignment structure is coarsely aligned with the specific crystal plane and has an array of components that are offset relative to each other by known angles defining the degree of precision with which said mask can be finely aligned with said crystal plane. Next, an anisotropic etch is performed through the first mask to etch the alignment structure into the wafer surface. The components of the alignment structure produce different etch patterns in the wafer surface according to their relative orientation to the specific crystal plane. Finally, a second mask is formed on the wafer surface having a reference structure thereon. The reference structure on the second mask is aligned relative to an etch pattern identified as being finely aligned with the specific crystal plane.

Abstract: A semiconductor device capable of preventing yield reduction and a method of manufacturing the same can be obtained. The method of manufacturing a semiconductor device including an element formation region arranged on a semiconductor substrate and an external region arranged on the semiconductor substrate and surrounding the element formation region, includes the steps of: providing the external region with an interlayer insulating film having a marking recess; providing a covering film extending from an internal portion of the marking recess to an upper surface of the interlayer insulating film; providing a filling film located on the covering film and filling at least the marking recess; and chemically mechanically polishing and moving the covering film on an upper surface of the interlayer insulating film, with the filing film filling at least the marking recess.

Abstract: The present invention discloses a method for forming an overlay vernier that can prevents deformation of the mother vernier. The method comprises the steps of: forming a planarization film on a wafer where a predetermined basic substructure has been formed; etching the planarization film to expose a predetermined region of a scribe line of the wafer where the overlay vernier will be formed; depositing a first polysilicon layer on the planarization film and the exposed wafer region; polishing the first polysilicon layer until the surface of the planarization film is exposed; forming an interlayer insulating film on the planarization film and the remained first polysilicon layer; etching the interlayer insulating film to expose a region of the first polysilicon layer where the mother vernier of the overlay vernier will be formed; depositing a second polysilicon layer on the interlayer insulating film and the exposed first polysilicon layer; and patterning the second polysilicon layer to form the mother vernier.

Abstract: The present invention provides a method of manufacturing halftone phase shift masks in less steps to save time and cost and to increase the yield, and a halftone phase shift mask with higher phase—and size controllability. To achieve this, the halftone phase shift mask includes a structure having a shade band of resist film formed on the halftone film delineating fine patterns and around the area of fine pattern.

Abstract: A method of manufacturing a semiconductor device, in which a contact alignment mark (18A) is formed in an interlayer insulating film (17), and a wiring alignment mark (19A) is formed above a gate alignment mark (15A) so that the size of the wiring alignment mark (19A) is slightly larger than the gate alignment mark (15A). At the same time, all the other alignment marks at the lower side are shielded by a shield film (19S). Opaque alignment mark and opaque shield film are formed to shield all the alignment marks at the lower side, whereby the alignment marks can be successively formed while stacked on one another.