Abstract: A driving mechanism and method are provided for driving a detachment tool adapted to detach a chip from an adhesive tape to which the chip is mounted. The mechanism includes a first actuator coupled to the detachment tool and operative to drive the detachment tool to move along a first axis substantially perpendicular to a surface of the chip, and a second actuator coupled to the detachment tool and operative to drive the detachment tool to move adjacent to a width of the chip along a second axis perpendicular to the first axis. The first actuator is configured for programmable movement along the first axis with respect to the chip in conjunction with the second actuator for movement adjacent the width of the chip to provide controlled lifting of the chip for propagation of delamination between the chip and the adhesive tape.

Abstract: Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of microelectronic components in a batch fashion. In one embodiment, an adhesive payer is applied on a rear surface of a wafer. A plurality of spaced-apart adhesive pads are defined within the adhesive layer. Each adhesive pad may cover less than the entire back surface area of the component to which it is attached. A mounting member (e.g., dicing tape) may be attached to the adhesive layer and, in some embodiments, the adhesive layer may be treated so that the mounting member is less adherent to the adhesive pads than to other parts of the adhesive layer, easing removal of the adhesive pads with the microelectronic components.

Abstract: An ion doping method to form source and drain is disclosed. First form a gate structure and a gate spacer on a semiconductor substrate, and then use dielectric layer having trenches therein to define heavily ion-doped positions and use a Y-shaped polysilicon layer formed in the trenches. Perform an ion implantation, by using the polysilicon layer, gate spacer and dielectric layer as a barrier layer, to naturally form ion doped regions of source/drain, so as to make components, which are minimized in the increased packing density, still have a gate structure keeping an enough channel length.

Abstract: A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification.

Abstract: A system for peeling semiconductor chips from tape is provided with a nose on a housing. The nose has transverse dimensions smaller than the transverse dimensions of a target chip. Apertures are provided through the nose from the housing. Vacuum ports are provided in the housing adjacent the nose. A vacuum source controllably connects to the apertures and the vacuum ports. The nose is positioned adjacent a tape attached on the opposite side thereof to the target chip. Vacuum is applied to attract the tape against the nose and the adjacent portions of the housing to peel the tape from the peripheral edges of the target chip while supporting the tape in the center of the target chip.

Abstract: In a method for producing a protective cover for a device formed in a substrate, at first a sacrificial structure is produced on the substrate, wherein the sacrificial structure comprises a first portion covering a first area of the substrate including the device and a second portion extending from the first portion into a second area of the substrate including no device. Then a first cover layer is deposited that encloses the sacrificial structure such that the second portion of the sacrificial structure is at least partially exposed. Then the sacrificial structure is removed, and the structure formed by the removal of the sacrificial structure is closed.

Abstract: Methods, systems, and apparatuses are described for expanding an area of a semiconductor wafer, an enhancing die transfer capability. A wafer is attached to a support structure. The wafer is separated on the support structure into a plurality of dies. An area of the support structure is increased to increase a space between adjacent dies of the plurality of dies. Dies may be transferred from the expanded support structure.

Abstract: A semiconductor manufacturing apparatus includes: a peeling mechanism to peel a pressure sensitive adhesive (PSA) tape from a semiconductor wafer constituted by a plurality of semiconductor chips which are separated therefrom, the semiconductor wafer having an element formation surface to form an element thereon and a rear surface opposite to the element formation surface, the PSA tape adhering to the element formation surface of the semiconductor wafer, each of the semiconductor chips having an adhesive layer formed on the rear surface; wherein the peeling mechanism has a sucking section which have a porous member to hold the semiconductor wafer by suction, the porous member being segmented into at least two sucking areas in the direction in which the PSA tape is peeled.

Abstract: The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device.

Abstract: A peeling device 11 includes an adsorber 15 having an adsorbing face 20A that adsorbs and retains a wafer W, and a peeling element 17 that holds a protective sheet H stuck to the wafer W, and peels off the protective sheet H from the wafer W through moving relatively to the adsorber 15. The adsorber 15 and the peeling element 17 are arranged so as to peel off the protective sheet H from the wafer W intermittently through moving relatively to each other while a peeling operation and a counter-peeling operation are performed alternately.

Abstract: Consistent with an example embodiment according to the invention, a material for the intermediate layer is chosen which can be selectively etched with respect to the dielectric layer. Before the deposition of the first conductor layer, the intermediate layer is removed at the location of the first channel region, and after the deposition of the first conductor layer and the removal thereof outside the first channel region and before the deposition of the second conductor layer, the intermediate layer is removed at the location of the second channel region. Thus, field effect transistors (FETs) are obtained in a simple manner and without damage to their gate dielectric. Preferably, a further intermediate layer is deposited on the intermediate layer which can be selectively etched with respect thereto.

Abstract: In a method for joining an adhesive tape to a back face of a semiconductor wafer after a process of working the back face of the semiconductor wafer, the semiconductor wafer is held at a state where a face having a pattern formed thereon is directed upward, and the adhesive tape is joined to the back face of the semiconductor wafer from below.

Abstract: An adhesive sheet for affixation of a wafer includes a first substrate, first adhesive layer arranged on the first substrate, second substrate arranged on the first adhesive layer, and second adhesive layer arranged on the second substrate. A chemical reaction which causes reduction in the adhesion of the first adhesive layer and a chemical reaction which causes reduction in the adhesion of the second adhesive layer are different. A method for processing using this sheet includes the steps of affixing the sheet to a wafer, dicing the wafer with the sheet affixed thereto, peeling the first substrate and first adhesive layer away from the diced wafer by reducing the adhesion of the first adhesive layer and, thereby, dividing the wafer into a plurality of chips, and peeling the second substrate and second adhesive layer away from each of the chips by reducing the adhesion of the second adhesive layer.

Abstract: Firstly, a supporting frame is produced, whose opening is spanned by an auxiliary layer flush on one side. Following the production of microstructures, flat parts or membranes on the common plane defined by the auxiliary layer and the supporting frame, the auxiliary layer is removed, preferably by etching. In a preferred application, the self-supporting microstructures produced in accordance with the method of the invention are used as electrically heatable resistance grids in a device for measuring weak gas flows.

Abstract: A system and method are disclosed for coupling a replacement micro-actuator to a drive arm suspension after a micro-actuator, such as a defective micro-actuator, has been detached from the suspension.

Abstract: Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

Abstract: A method for forming a dual damascene structure in a semiconductor device manufacturing process including providing a process wafer including a via opening extending through at least one dielectric insulating layer; blanket depositing a negative photoresist layer to include filling the via opening; blanket depositing a positive photoresist layer over and contacting the negative photoresist layer; photolithographically patterning the positive photoresist layer to form a trench opening etching pattern overlying and encompassing the via opening; etching back the negative photoresist layer to form a via plug having a predetermined thickness; and, etching a trench opening according to the trench opening etching pattern.

Abstract: A method for the fabrication of an integrated semiconductor component, in which at least one isolation trench is formed, a first layer of a nonconductive material is applied by a nonconformal deposition method, and a second layer of a nonconductive material is applied by a conformal deposition method at least to the back surface of the semiconductor component.

Abstract: A method is provided for planarization of structures which minimizes step heights, reduces process steps, improves cleanliness, and provides increased ease of debond. Structures are placed with working surfaces facing down onto an adhesive layer such that structures remain fixed during heating. A bi-layer encapsulating film is used to achieve planarization. A carrier is bi-laminated with a thermoplastic film layer followed by a chemically inert protective polymer film layer that can withstand etch and cleaning processes. The thermoplastic layer is laminated on top of the carrier; the polymer layer is laminated on top of the joined thermoplastic layer and carrier. The carrier with bi-layer film is then placed onto the backside of the structures to resist chemical attack from the front side during photostrip and enable planarization. When heat is applied, the bi-layer encapsulating film melts and pushes the polymer layer into the gaps between structures thereby achieving complete planarization.

Abstract: A method of making a semiconductor device comprising: providing a semiconductor substrate having a plurality of discrete devices formed therein, and a plurality of metal layers and support layers, the support layers comprising an uppermost support layer and other support layers, and wherein each metal layer has an associated support layer having at least a portion underlying the metal layer, and wherein the plurality of metal layers includes an uppermost metal layer including a sealing pad having an opening therethrough, and a passivation layer having at least one opening therein exposing a portion of the sealing pad including the opening therethrough, and the uppermost support layer having a portion exposed through the opening in the sealing pad; exposing the uppermost support layer to an etching material through the opening in the sealing pad and etching away the support layers; and sealing the opening in the sealing pad.

Abstract: The invention provides a separation method for object and glue membrane, and it is characterized: an external force such as tearing apart is pre-applied for appropriately separating the glue membrane and the object, such that the binding ability between the object and the glue membrane is reduced, and a taking-and-placing head then sucks up the object; to achieve said objective, it can arrange a vacuum sucking-up seat that is moveable and has vacuum adsorption hole under the glue membrane, and the sucking force of the vacuum sucking-up seat may generate an external force such as tearing apart to the glue membrane, and the object is then sucked up by the taking-and-placing head; it is also possible to arrange a connection rod to lower down and lift up the taking-and-placing head simultaneously and, before the taking-and-placing head is lowered down to contact the object, it may bring along the connection rod to press down the glue membrane and generate an external force such as tearing apart to the glue membra

Abstract: A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.

Abstract: The invention provides a separation method for object and glue membrane, and it is characterized: an external force such as tearing apart is pre-applied for appropriately separating the glue membrane and the object, such that the binding ability between the object and the glue membrane is reduced, and a taking-and-placing head then sucks up the object; to achieve said objective, it can arrange a vacuum sucking-up seat that is moveable and has vacuum adsorption hole under the glue membrane, and the sucking force of the vacuum sucking-up seat may generate an external force such as tearing apart to the glue membrane, and the object is then sucked up by the taking-and-placing head; it is also possible to arrange a connection rod to lower down and lift up the taking-and-placing head simultaneously and, before the taking-and-placing head is lowered down to contact the object, it may bring along the connection rod to press down the glue membrane and generate an external force such as tearing apart to the glue membra

Abstract: An electronic-component handling apparatus includes a) an electronic-component retainer provided with an adhesive layer for retaining multiple electronic components by an adhesion force at the bottom surface thereof and b) a blade which is used for removing the electronic components from the adhesive layer. A driving mechanism moves the blade relative to the adhesive layer along the surface of the adhesive layer while forming a dent in the bottom surface of the adhesive layer by a tip of the blade.

Abstract: In a semiconductor device manufacturing process, a semiconductor wafer is diced into a plurality of semiconductor chips, which are then peeled, from a dicing tape, using a peeling device. The peeling device includes a plurality of annular contact members arranged one after another from the outside to the inside, and the annular contact members are operated so that the semiconductor chip is successively peeled from the tape from the outer circumferential portion thereof toward the central portion thereof.

Abstract: A method for forming a self-aligned contact hole includes forming a plurality of conductive structures on a semiconductor substrate, each conductive structure including a conductive film pattern and a protection pattern formed on the conductive film pattern, forming a first insulation film to fill a space between adjacent conductive structures, successively etching the first insulation film and the protection patterns until each of the protection patterns has an exposed level upper surface, forming a second insulation film on the resultant structure, and selectively etching portions of the second insulation film and the first insulation film using a photolithography process to form the self-aligned contact hole exposing a portion of the semiconductor substrate between adjacent conductive structures.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a high-k gate dielectric layer that includes impurities, then forming a silicon containing sacrificial layer on the high-k gate dielectric layer. After the silicon containing sacrificial layer has gettered the impurities from the high-k gate dielectric layer, the silicon containing sacrificial layer is removed, and a gate electrode is formed on the high-k gate dielectric layer. The method optionally includes exposing the high-k gate dielectric layer to a silicic acid containing solution until a silicon dioxide capping layer forms on the high-k gate dielectric layer, prior to forming a gate electrode on the capping layer.

Abstract: The present invention provides a method for preserving an oxide hard mask for the purpose of avoiding growth of epi Si on the gate stack during raised source/drain formation. The oxide hard mask is preserved in the present invention by utilizing a method which includes a chemical oxide removal processing step instead of an aqueous HF etchant.

Abstract: Provided is a semiconductor apparatus manufacturing method capable of severing a base material without producing burrs. A multiplicity of semiconductor apparatuses are produced as follows. A multi-segment base material is obtained by mounting a multiplicity of semiconductor chips on a substrate having a wiring pattern, followed by sealing the semiconductor chips with resin, further followed by attaching a terminal portion having a terminal hole to a back surface of the substrate. A filler is charged in each terminal hole, and, after curing the filler, the base material is severed along a cutting line covering the terminal hole, whereupon the multi-segment base material is divided into separate semiconductor apparatuses. The terminal hole is left exposed along the cut surface of the semiconductor apparatus. Chilled water is applied to the filler filled in the terminal hole to remove it from the terminal hole.

Abstract: A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming an insulating film on a conductive pattern formed on a substrate; forming a resist pattern on the insulating film; performing etching to the insulating film using the resist pattern as a mask to form in the insulating film an opening at which part of the surface of the conductive pattern is exposed; forming an antioxidant layer on the part of surface of the conductive pattern exposed while removing the resist pattern; and depositing a conductive film on the conductive pattern from which the antioxidant layer has been removed.

Abstract: A method for sawing a wafer having a large number of semiconductor devices, e.g., image sensor devices is provided. In one embodiment, a protective layer covers micro-lenses of the image sensor devices to protect the lenses from being damaged or polluted by, for example, silicon dust during wafer sawing. The silicon dust remaining in a gap between the devices is removed together with an adhesive tape on the backside surface of the wafer. Accordingly, the silicon dust cannot affect the micro-lenses during the wafer sawing process or subsequent die-attach, so that image defects caused by the silicon dust can be reduced and the yield of the image sensor devices is increased.

Abstract: Disclosed herein is a pressure sensitive adhesive sheet for fixing a semiconductor wafer during semiconductor wafer processing in vacuum, comprising a substrate and, superimposed on one side or both sides thereof, a layer of ultraviolet curable pressure sensitive adhesive composition comprising an ultraviolet curable copolymer having ultraviolet polymerizable groups as side chains and a phosphorous photopolymerization initiator. The pressure sensitive adhesive sheet for semiconductor wafer processing, even in the processing of a semiconductor wafer in vacuum, is free from generating gases from the pressure sensitive adhesive sheet, thereby avoiding wafer deformation attributed to evaporated gas components and adhesive transfer caused thereby.

Abstract: A method is disclosed for making a device having one or more deposited layers and subject to a post deposition high temperature anneal. Opposing films having similar mechanical properties are deposited on the front and back faces of a wafer, which is subsequently subjected a high temperature anneal. The opposing films tend to cancel out stress-induced warping of the wafer during the subsequent anneal.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A semiconductor chip pickup jig which separates semiconductor chips affixed to an adhesive sheet from the adhesive sheet includes first and second thrust pin groups and a pin holder on which base portions of the first and second thrust pin groups are mounted. The thrust pins of the first thrust pin group are arranged in positions corresponding to corner portions of the semiconductor chip and thrust up the semiconductor chip by use of first front end portions thereof with the adhesive sheet disposed therebetween. The thrust pins of the second thrust pin group are arranged in positions corresponding to a nearby portion of a central portion of the semiconductor chip with second front end portions thereof being set lower than the first front end portions and thrust up the semiconductor chip by use of the second front end portions thereof with the adhesive sheet disposed therebetween.

Abstract: A plurality of posts 12 having electrical conductivity are formed on a side of a plate member 11. A buffer layer 14 is formed on the side of the plate member 11 so that top ends of the posts 12 are protruded from the buffer layer 14. The semiconductor pellet 17 is mounted on a predetermined position on the top ends of the posts 12. The electrodes of the semiconductor pellet 17 are connected to the top ends of the posts 12 by means of wires 18. A resin portion 20 is formed on the buffer layer 14 so that the resin portion 20 encapsulates the posts 12, the wires 18 and the semiconductor pellet 17. The plate member 11 is removed from the buffer layer 14 and the posts 12, so that the posts 12 are electrically separated from each other. Solder balls 23 are bonded to the bottom ends 21 of the posts 12.

Abstract: A fabricating method for a semiconductor package is proposed, in which a chip carrier accommodates at least one semiconductor chip, which is attached with an interface layer formed on a covering module plate consisting of at least one covering plate, while the interface layer is poor in adhesion to the chip and a molding compound used for forming an encapsulant. So that after completing molding, ball implantation and singulation processes, the interface layer, the covering plate and a portion of the encapsulant formed on the covering plate can be easily removed by heating the singulated semiconductor package. This allows the molding compound not to flash on the chip, and prevents the chip from being damaged by stress generated in the molding process.

Abstract: A process uses two layers of polysilicon for fabricating high-density nonvolatile memory, such as mask ROM or SONOS memory, integrated with advanced peripheral logic on a single chip. The method includes covering a gate dielectric layer with a sacrificial layer of silicon nitride; using a masks for defining line structures in the layer of silicon nitride for the bit line implant processes; depositing a dielectric material among the line structures to fill gaps among the line structures; planarizing the deposited oxide and said layer of silicon nitride; removing the silicon nitride and applying a layer of polysilicon material; patterning wordlines in the array portion, and transistor gate structures in said non-array portion, and applying LDD, silicide and other logic circuit processes.

Abstract: A substrate support rim used in the fabrication of devices such as organic light emissive diodes (OLEDs) is disclosed. The support rim, which is located at the edge of a substrate, serves to reinforce the substrate, facilitating handling during and after the fabrication process to reduce damage to the device. The support rim comprises, for example, epoxy, adhesives or other materials that adhere to the substrate.

Abstract: Demounting workpieces attached to an adhesive surface of an adhesive film with a workpiece demounting apparatus having a base and a plurality of substantially parallel blades mounted to the base. Each of the blades has a substantially linear blade edge, each blade edge lying within a blade-edge plane that is substantially perpendicular to the blades. The spacing between the blades is small enough to support said workpieces and large enough to permit the adhesive film to pass between the blades after being cut by said blade edges during a workpiece demounting operation. The plurality of blade edges thus provides a substantially planar blade-edge surface, in the blade-edge plane, for cutting the adhesive film and for supporting the workpieces while the adhesive film is pulled free from said workpieces.

Abstract: A method of detaching an article (B) from a laminate unit (C), the laminate unit (C) comprising a support plate (A) and, fixed thereto, the article (B), the fixing effected through a pressure sensitive adhesive double coated sheet (1) deformable by heating to thereby exert a peeling effect, which method comprises heating at least one outer part of the laminate unit so that at least part of an outer region of the laminate unit is initially heated up, with other regions heated up later, and detaching the article (B) from the pressure sensitive adhesive double coated sheet (1) in a direction from the outer region toward the other regions. Thus, there are provided a detaching method and a detacher apparatus which enable efficiently detaching an article, such as an extremely thin wafer, having been fixed through a heat shrinkable pressure sensitive adhesive double coated sheet without cracking of the article.

Abstract: A semiconductor device mounting method and system and an IC card fabricating method which can fabricate high quality products by dicing a thin semiconductor wafer, in a state where it is adhered to an adhesive sheet, into thin semiconductor devices, peeling the group of diced thin semiconductor devices from the adhesive sheet at high speed without damaging or cracking the semiconductor devices, conveying the group of peeled semiconductor devices on a unit basis in serial order, and mounting them onto a mounting board.

Abstract: A method of forming a low resistance metal silicide layer on a narrow width, conductive gate structure, has been developed. After formation of a metal silicide layer on a conductive gate structure via a self-aligned metal silicide (salicide), procedure, unreacted metal is removed via a selective wet etch procedure. Components of the wet etch procedure incorporated in the metal silicide layer, are next removed via a medium temperature—high vacuum anneal procedure. Removal of the wet etch components incorporated in the metal suicide layer allow a final anneal procedure to convert the metal silicide layer to a lower resistance metal silicide layer, without voids or agglomerated regions of metal silicide which may have formed during the final anneal if the incorporated wet etch components had not been removed.

Abstract: In a method of fabricating a semiconductor device, a semiconductor wafer is provided with a plurality of semiconductor elements formed thereon. An insulating adhesive is selectively provided over respective predetermined areas of the semiconductor elements. The semiconductor wafer is then separated into the semiconductor elements, each having corresponding portions of the insulating adhesive thereon.

Abstract: A method for fabricating a resonator, and in particular, a thin film bulk acoustic resonator (FBAR), and a resonator embodying the method are disclosed. An FBAR is fabricated on a substrate by introducing a mass loading top electrode layer. For a substrate having multiple resonators, the top mass loading electrode layer is introduced for only selected resonator to provide resonators having different resonance frequencies on the same substrate.

Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises pretreating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures.

Abstract: A method of forming a metal silicide layer with low resistance, with minimal consumption of silicon, includes depositing a first metal layer over a silicon-containing region, depositing a second metal layer over the first metal layer, forming an antioxidation layer over the second metal layer, and performing a first heat treatment on the structure to form a metal silicide preliminary layer from the silicon-containing region and the first metal layer and to form an alloy layer including a first metal and a second metal from the second metal layer and the first metal layer. The antioxidation layer and then the alloy layer and a portion of the remaining first metal layer are removed. A second heat treatment on the metal silicide preliminary layer at a higher temperature than the first heat treatment is performed, to change the metal silicide preliminary layer into a metal silicide layer.

Abstract: The present invention teaches a sawn wafer with ultra clean bonding pads on die which enhance the strength of wire bond and results in higher yield and improved reliability of packaged semiconductor die. Clean wafers ready for dicing are coated with a removable insulating water soluble non-ionic film which enhances clean saw cuts and reduces buildup. The protective film is hardened by heat and resists removal by cooling water used in dicing saws. However, after dicing the protective film is removable in a wafer washer using high pressure warm D.I. water. After removal of the protective film the electrode pads are virtually as clean as before dicing. The film may be used as a protective layer until the sawn wafer is ready for use.