Abstract: A method for opening contacts of different depths in a semiconductor wafer after salicide processing. A sacrificial layer is formed over the wafer wherein the wafer further includes a first silicide layer and a second silicide layer formed thereon. The sacrificial layer is selectively removed such that only a portion of the sacrificial layer remains on the first silicide layer. An interlayer dielectric layer is formed over the wafer. The interlayer dielectric layer is planed. Contact windows are patterned. Contacts are opened to reveal the first silicide layer and the second silicide layer as contacts wherein the position where the first silicide layer is formed is higher than that where the second silicide layer is formed. Further, the thickness Y of the sacrificial layer is determined according to the following relation: Y=.DELTA.X.times.R.sub.SAC /(R.sub.ILD -R.sub.SAC), wherein .DELTA.X is the height difference between the first silicide layer and the second silicide layer, and R.sub.SAC and R.sub.
Abstract: A method of producing a semiconductor device includes the step of: preparing a wafer on which a protective film is formed except for the area of an aluminum electrode formed on the wafer; etching an oxide film present on the aluminum electrode formed on the wafer thereby removing the oxide film; forming a metal film on the wafer; put an adhesive tape on the wafer so that the adhesive tape adheres to the wafer; and peeling off the adhesive tape. Since the adhesion between the metal film and the protective film is weak and the adhesion between the metal film and the aluminum electrode is strong, the metal film on the protective film is peeled off while the portion of the metal film present on the aluminum electrode remains unremoved. The metal film remaining on the aluminum electrode has good conformability with a solder bump, and thus it is possible to obtain good wettability between the solder bump and the aluminum electrode in the process of forming the solder bump on the aluminum electrode.
Type:
Grant
Filed:
August 14, 1997
Date of Patent:
December 8, 1998
Assignee:
Matsushita Electric Industrial Co., Ltd.
Abstract: A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the arsenic layer, the second layer having an outer surface; c) first annealing the wafer at a temperature of at least about 600.degree. C. for a time period sufficient to impart growth of polycrystalline silicon grains in the second layer and providing a predominately polysilicon second layer, the first annealing step imparting diffusion of arsenic within the second layer to promote growth of large polysilicon grains; and d) with the second layer outer surface being outwardly exposed, second annealing the wafer at a temperature effectively higher than the first annealing temperature for a time period sufficient to outgas arsenic from the polysilicon layer.