Abstract: A structure for protecting a special-purpose area of an image sensor die or a micromachine die during singulation of the die from a wafer includes a protective layer that has a polymerized upper zone and an unpolymerized lower zone. At least part of the unpolymerized lower zone has an adhesive lower surface that is attached to a top surface of the wafer so that the protective layer overlies and protects the special-purpose area during either frontside or backside sawing. The unpolymerized lower zone is then entirely polymerized to make the adhesive lower surface nonadhesive to facilitate removal of the protective layer from the die.

Abstract: A method for fabricating a via openings, comprising the following steps. A semiconductor structure is provided. A low-k layer is formed upon the semiconductor structure. A via opening is formed within the low-k layer. An inert polymer liner layer is formed upon the low-k layer and within the via opening. A photoresist layer is formed upon the inert polymer liner layer, filling the inert polymer lined via opening. The inert polymer liner layer preventing adverse chemical reactions between the photoresist layer and portions of the low-k layer. The photoresist layer is patterned to expose the inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening. The exposed inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening and the portions of the inert polymer liner layer upon the via opening and portions of the inert polymer lined low-k layer adjacent the via opening are etched to form a structure opening.

Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure. Plasma may be used to treat a surface of the release layer or the dielectric film to produce a plasma-treated surface to lower the peel strength of any film or layer bound to the plasma-treated surface.

Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.

Abstract: Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

Abstract: The invention includes methods of forming microstructure devices. In an exemplary method, a substrate is provided which includes a first material and a second material. At least one of the first and second materials is exposed to vapor-phase alkylsilane-containing molecules to form a coating over the at least one of the first and second materials.

Abstract: A method and article of manufacture of an ultra-thin base oxide or nitrided oxide layer in a CMOS device. The method and article of manufacture are formed by providing a silicon wafer with an initial oxide layer which is removed from the silicon wafer by a hydrogen baking step. A new oxide layer or nitrided oxide layer is formed by thermal growth on the silicon wafer surface. A portion of the new oxide layer is removed by hydrogen annealing. A MOSFET can be created by forming a gate electrode structure on a high-k dielectric material deposited on the new oxide layer.

Abstract: The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

Abstract: An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.

Abstract: A method for forming isolation regions on a semiconductor substrate, comprises partially covering the surface of the semiconductor substrate 10 with oxidation inhibiting films 12a, and heat-treating the portions of the semiconductor substrate which are exposed from the oxidation inhibiting films. The heat treatment consists of a wet-type heating step in a gaseous atmosphere containing oxygen and hydrogen and a dry-type heating step in an atmosphere without hydrogen, which is performed after the wet-type heating step.

Abstract: Methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer on substrate, and then forming a conductive laminate on the release layer. After the release layer is formed, the conductive laminate can be easily separated by the substrate to eventually form a flexible circuit structure.

Abstract: A method for manufacturing a micromechanical component, in particular, a surface-micromechanical yaw sensor, includes the following steps: providing a substrate having a front side and a back side; forming a micromechanical pattern on the front side; applying a protective layer on the micromechanical pattern on the front side; forming a micromechanical pattern on the back side, a resting on the micromechanical pattern on the front side taking place at least temporarily; removing the protective layer on the front side; and optionally further processing the micromechanical pattern on the front side and/or the micromechanical pattern on the back side.

Abstract: A method for manufacturing the floating gate of a flash memory. First, a substrate is provided. A gate oxide layer, a polysilicon layer and a silicon nitride layer are sequentially formed over the substrate. Gate position is defined and then the silicon nitride layer above the gate position is removed. Th exposed polysilicon layer is oxidized to from a floating gate oxide layer. A buffer layer is formed over the silicon nitride layer and the floating gate oxide layer. A first spacer is formed on the sidewall of the buffer layer. Thereafter, a second spacer is formed. Using the second spacer as a mask, the exposed floating gate oxide layer is removed. The buffer layer, the first spacer and the second spacer above the polysilicon layer and the floating gate oxide layer are removed. Finally, the polysilicon layer not covered by the floating gate oxide layer is removed to form a complete floating gate of a flash memory.

Abstract: Methods of protecting from atmospheric contaminants, or removing atmospheric contaminants from, the bonding surfaces of copper semiconductor bond pads by coating a bond pad with a layer of a ceramic material having a thickness that is suitable for soldering without fluxing and that is sufficiently frangible during ball or wedge wire bonding to obtain metal-to-metal contact between the bonding surfaces and the wires bonded thereto. Coated semiconductor wafers are also disclosed.

Abstract: A selected passivating layer is purposely formed on an exposed surface of a Cu and/or Cu alloy interconnect member, thereby avoiding the adverse consequences stemming from formation of a thick copper oxide layer thereon. The passivating layer is formed by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) with a copper corrosion-inhibiting chemical; or (b) by electroless plating a metal layer on the surface of the Cu or Cu alloy layer; or (c) depositing a metallic compound on the surface of the Cu or Cu alloy layer by CVD. The passivating layer can then be removed. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in an ILD, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the passivating, layer thereon, and depositing a silicon nitride diffusion barrier layer thereon.

Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film containing a coating insulating film having a low dielectric constant. In construction, there are provided the steps of preparing a substrate 20 on a surface of which a coating insulating film 26 is formed by coating a coating liquid containing any one selected from a group consisting of silicon-containing inorganic compound and silicon-containing organic compound, and forming a protection layer 27 for covering the coating insulating film 26 by plasmanizing a first film forming gas to react, wherein the first film forming gas consists of any one selected from a group consisting of alkoxy compound having Si—H bonds and siloxane having Si—H bonds and any one oxygen-containing gas selected from a group consisting of O2, N2O, NO2, CO, CO2, and H2O.

Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).

Abstract: First, a conductive layer is formed on a semiconductor substrate having an alignment mark formed thereon. Next, a photoresist is selectively formed on a region of the conductive layer in which a wiring layer is to be formed and on the alignment mark. Subsequently, the conductive layer is etched by using the photoresist as a mask.

Abstract: A method and system for dicing semiconductor components, such as bare dice and chip scale packages, are provided. Initially, the semiconductor components are contained on a wafer or a panel. Next, an insert that includes a base and an adhesive layer, is used to support the substrate for separation into separate components by sawing or other process. The insert with the separated components retained thereon, is then transferred to a carrier tray constructed according to JEDEC standards. The carrier tray is adapted for stacking and for handling by conveyors, magazines and other standard equipment. The system includes the substrate, the insert, and the standardized carrier tray.

Abstract: There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/minor less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Abstract: The present invention is directed to a metal oxide semiconductor transistor having a fully overlapped lightly doped drain (LDD) structure which offers the advantages of conventional fully overlapped LDD transistors but which significantly reduces the drain-to-gate overlap capacitance associate therewith. To achieve fully overlapped LDD construction and reduced drain-to-gate overlap capacitance, the metal oxide semiconductor transistor of the present invention employs a gate electrode comprising a main gate region formed from heavily doped polysilicon and depleted sidewall polysilicon spacers formed from undoped or depleted polysilicon. In the MOS transistor of the present invention, the lightly doped regions are fully over-lapped by the combination of the depleted sidewall polysilicon spacers and the main gate region.

Abstract: The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor.

Abstract: A system is provided for removing large semiconductor work pieces from an adhesive film. A pick and place apparatus is provided with a collet bar with elongated sides and opposed ends. A channel extends into a cavity on a lower surface of the collet bar. The channel receives a vacuum. The collet bar is angled from a longitudinal axis of the larger work piece to be removed. The work piece may be aligned with a cylindrical roller located under the adhesive film. The angle is chosen to extend the bar across a majority of the width of the work piece. By lowering the collet bar, a first end contacts the work piece, which may be tilted on the roller. Further lowering of the collet bar tilts the semiconductor work piece up into the same plane as the lower surface of the collet bar.

Abstract: Self-aligned silicidation (e.g., Ti, Co, or Ni silicides) for silicon integrated circuits with an HF-based final etch of the silicide to remove filaments. Either ultradilute HF solution or HF vapor may be used.

Abstract: The present invention provides a method of preventing corrosion of a titanium layer in a semiconductor wafer. The semiconductor wafer comprises a dielectric layer, a column-shaped tungsten plug embedded in the dielectric layer and having its top surface cut to be at the same level as that of the dielectric layer, a titanium layer positioned on the top of the dielectric layer and covering a portion of the top surface of the tungsten plug, a main conductive layer positioned on the surface of the titanium layer, a photoresist layer positioned on the surface of the main conductive layer, and a polymer layer scattered on the surface of the semiconductor wafer. The method is first to utilize a dry cleaning process to strip off the photoresist layer and the polymer layer, then to perform a nitridizing process to make the surface of the titanium layer exposed on the surface of the semiconductor wafer generate a titanium nitride layer.

Abstract: This invention relates generally to a new method of forming semiconductor substrates with defect-free surface metallurgical features. In particular, the invention related to a method for providing surface protected ceramic green sheet laminates using at least one thermally depolymerizable surface layer. More particularly, the invention encompasses a method for fabricating semiconductor substrates wherein a thermally depolymerizable/decomposable surface film is placed over a ceramic green sheet stack or assembly prior to lamination and caused to conform to the surface topography of the green sheet during lamination. The invention also encompasses a method for fabricating surface protected green sheet laminates which can be sized or diced without causing process related defects on the ceramic surface.

Abstract: A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.

Abstract: A method that teaches the formation of deep trenches within the surface of a semiconductor wafer, these deep trenches are used to separate the wafer into individual chips by applying stress to the wafer. The formation of the deep trenches uses exposing a thick layer of photoresist followed by etching. The etching is a two step etch, a stabilization etch and a main etch. The stress used to separate the wafer into individual chips can be invoked by applying physical force to the wafer.

Abstract: Methods of forming semiconductor substrates include the steps of bonding a first semiconductor substrate to a second semiconductor substrate. The first semiconductor substrate has a first adhesion layer thereon extending opposite a first surface thereof and a first diffusion barrier layer extending between the first adhesion layer and the first surface. The second semiconductor substrate has a second adhesion layer thereon. The first diffusion barrier layer prevents impurities from within the first adhesion layer from diffusing directly into the first semiconductor substrate during subsequent thermal treatment steps (e.g., annealing). A second diffusion barrier layer is then formed to encapsulate the bonded wafers and the adhesion layers and diffusion barrier layer therebetween. The second diffusion barrier layer prevents impurities from within the adhesion layers from out-diffusing (from the lateral edges of the adhesion layers) during the subsequent thermal treatment steps (e.g., annealing steps).

Abstract: An apparatus and method for transferring a semiconductor die from an adhesive film to an output carrier is disclosed. The adhesive film and associated hoop assembly on which the die are secured are inverted so that die face downward, p-side down, from the film. And an output pack is positioned beneath the die. An ejector pin exerts a force on a side of the adhesive film opposite the side on which the semiconductor die is secured to release the die. A vacuum is provided through a port in the output pack, pulling the released die into the output pack. The transfer occurs in a single step and orients the die p-side down in the output pack, thus eliminating the control arm/vacuum collet assembly and associated handling steps of conventional transfer mechanisms.

Abstract: A method for fabricating a non-volatile memory cell for a substrate includes the following steps: forming an isolation structure to define an active region on the substrate; forming a channel oxide layer on the active region; forming a conducting layer and a silicon nitride layer over the substrate; defining the polysilicon layer and the silicon nitride layer to form a floating gate on the active region and to form an opening exposing a portion of the isolation structure; conformally forming an etching protection layer which extends from the isolation structure inside the opening up to the silicon nitride layer; forming an oxide layer over the substrate; planarizing the oxide layer to the surface of the silicon nitride layer so that the remainder of the oxide layer is left within the opening; removing the silicon nitride layer; forming conducting spacers on the sidewalls of the remainder of the oxide layer; removing the remainder of the TEOS oxide layer; conformally forming an ONO layer; forming a controlling

Abstract: An apparatus and method for demounting parts from the adhesive upper surface of a film has a base with a tool mounted thereon. A portion of the tool has a fluted surface extending above the base upper surface. The film lower surface is positioned above the base with a part on the film overlying and opposite the fluted surface of the tool. A vacuum is supplied through at least one passage in the base to the film lower surface to draw the film around and over the tool flute and force the part to at least partially separate from the film adhesive upper surface. The part that has been separated from the adhesive upper surface of the film is stripped from the film adhesive upper surface such as by applying a vacuum force directly to the part through a collet and moving the collet and base relative to one another.

Abstract: An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.

Abstract: An object of the invention is to provide a preparation process of a semiconductor wafer, in which breakage of the wafer on grinding the back surface of the wafer and on peeling the adhesive tape is prevented, and the operation time can be reduced. The preparation process of a semiconductor wafer comprises the steps of: adhering an adhesive tape on a front surface of a semiconductor wafer; grinding a back surface of the semiconductor wafer by a grinding machine; peeling the adhesive tape; and cleaning the front surface of the semiconductor wafer, wherein an adhesive tape having heat shrinkability is used as the adhesive tape, and after grinding the back surface of the semiconductor wafer, warm water at a temperature of from 50 to 99.degree. C. is poured to peel the adhesive tape in a wafer cleaning machine, and the front surface of the semiconductor wafer is cleaned in the wafer cleaning machine.

Abstract: An apparatus and method is disclosed for removing a selected semiconductor chip from a semiconductor wafer. The selected semiconductor chip is elevated by the use of an X--Y--Z assembly by having a rounded tip portion of a round probe member assembly that is part of the X--Y--Z assembly contact a back portion of a flexible, transparent backing layer beneath the selected semiconductor chip so that removal of the semiconductor chip can be completed by using a vacuum type pencil.

Abstract: A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.

Abstract: An adhesive sheet for wafer setting, comprising a wafer setting part composed of an expansible film and an adhesive layer for wafer setting and a marginal part outside the wafer setting part,wherein the marginal part has an antiexpansibility greater than that of the wafer setting part. This enables secure expansion in a process for producing an electronic component.

Abstract: A method and apparatus for removing a component retained to a film carrier by an adhesive bonding force exerted on the component by the film carrier. The method includes the steps of supporting a section of the film carrier lying beneath the component; pulling a portion of the supported film carrier section away from the component to substantially reduce the adhesive bonding force exerted on the component by the film carrier; and lifting the component off the film carrier. The apparatus for performing the method includes a convex-shaped base element having a slot which applies at least a partial vacuum that pulls the portion of the film carrier away from the component and a component pickup element for lifting the component off the film carrier.

Abstract: A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.

Abstract: A method for manufacturing a metal-oxide-semiconductor (MOS) transistor is described. In the invention, doped regions of the local pocket type are formed in the substrate after the source/drain terminals of a MOS transistor in the logic circuit area are formed. The method includes the steps of forming an insulation layer over the entire substrate. Then, a portion of the insulation layer is removed to expose the spacers on the sidewalls of the gate electrode. Subsequently, the spacers are removed, and then an ion implantation operation is conducted to implant dopants into the substrate through the windows formed by the uprooted spacers. Ultimately, doped regions of the local pocket type are formed in the substrate under the lightly doped drain source/drain terminals of a MOS transistor.

Abstract: Shallow LDD junctions are obtained by depositing a thin screening oxide layer prior to moderate or heavy ion implantations. The use of a thin deposited screening oxide, as by plasma enhanced chemical vapor deposition, instead of a thermally grown oxide, minimizes transient enhanced diffusion during annealing to activate the source/drain regions, thereby decreasing the junction depth.

Abstract: Our semiconductor device is an IC chip 10 whose back surface is affixed to a mounting section 81 by means of a thermoplastic adhesive (for example, thermoplastic polyimide) 84. Package cracks are eliminated or markedly reduced and the problems with productivity for mounting curing and mounting alleviated. Even when a padless special lead frame or one with a small die pad is used, package cracks are eliminated or markedly reduced, and the lead frame can be mounted easily and with good reliability on top of the lead frame.

Abstract: This invention aims to facilitate observation and structural analysis of crystal grains of aluminum wiring. In the process, a protective film of a semiconductor device is removed by dry etching. Next, said semiconductor device is inclined and rotated and an aluminum alloy film or laminated aluminum alloy film of the semiconductor device is scanned with a focused ion beam. Then, said aluminum alloy film or laminated aluminum alloy film is scanned with a cantilever, atomic force between said aluminum alloy film or laminated aluminum alloy film and the cantilever is measured, and the surface of said aluminum alloy film or laminated aluminum alloy film is observed in vacuum.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A method for etching access opening to aluminum alloy wire bonding pads of integrated circuit chips is described wherein a polymer layer is in-situ deposited into the opening after the bonding pad has been exposed by dry etching of a passivation layer. The passivation layer, is first etched with fluorocarbon etchants and then a TiN ARC layer is removed from over the aluminum bonding pad with etchants which may contain chlorine either as etch components or as a contaminant in an etchant such as SF.sub.6 non-volatile chlorine containing residues including AlCl.sub.3 and trapped Cl.sub.2, are left behind after the ARC layer has been removed. These cause corrosion of the bonding pad when exposed to atmospheric moisture. The polymer layer deposited immediately after the pad surface is exposed by the etchant, provides a temporary seal over the aluminum bonding pad, protecting it from exposure to moisture during subsequent processing steps.

Abstract: An improved method of forming thin film transistors includes depositing a gate dielectric material over a gate electrode and subsequently depositing a polysilicon layer over the dielectric layer. Prior to applying a photoresist material, the polysilicon layer is coated with a protective layer of, for example, silicon oxide. A photoresist material is then applied and the polysilicon layer subsequently selectively etched to form the transistor body. Finally, any masking material is removed. The protective silicon dioxide layer prevents ion contamination of the polysilicon transistor body which can occur during the masking procedure, during the etch procedure, or during subsequent removal of any foreign mask and cleaning procedures. This will, in effect, enable one to prepare transistors with a better-defined threshold.

Abstract: The formation of a cobalt silicide layer of uniform thickness over the source/drain regions and the polysilicon gate electrode of an MOS structure, which does not thin out adjacent the edges of the top surface of the polysilicon gate electrode, i.e., adjacent the oxide spacers, is achieved by first forming a titanium capping layer over a cobalt layer deposited over the MOS structure prior to formation of the cobalt silicide, and while excluding oxygen-bearing gases from the cobalt surface prior to the deposition of the titanium capping layer.

Abstract: The present invention discloses a process for forming a photoresist pattern in a semiconductor device. In this process, first, a semiconductor substrate where an objective layer for the formation of a pattern is formed thereon, is provided. Afterwards, an alkaline aqueous solution is formed on the semiconductor substrate using either spray, coating, or deposition method. Thereafter, a priming step is performed. Lastly, a photoresist pattern is formed on the semiconductor substrate.

Abstract: A method of forming an integrated structure that comprises a self-aligned via/contact and metal line is described. The via/contact is formed out of part of a first spacer made of a first dielectric and surrounded by a second dielectric in a first sandwich structure. The metal line is formed out of a second spacer made of the first dielectric and surrounded by the second dielectric in a second sandwich structure. The second sandwich structure is disposed over the first sandwich structure. At the point of contact between the first and second spacer, an angle of 90.degree. exists in a preferred embodiment. The via/contact and metal line form a self-aligned integrated structure that is created in one etch step. The integrated structure is subsequently filled with a conductive material.

Abstract: A process for bulk micromachining a silicon wafer to form a silicon micromachined structure. The process involves the application of a protective film on one or more surfaces of the silicon wafer to protect metallization and circuitry on the wafer during the bulk micromachining process, during which a wet chemical etchant is employed to remove bulk silicon from a surface of the silicon wafer. The protective film is divinylsiloxane bisbenzocyclobutene (BCB), which has been found to be highly resistant to a wide variety of wet chemical etchants, and retains such resistant at elevated temperatures commonly preferred for bulk silicon etching. The degree to which this material is cured prior to etching is advantageously tailored to promote its resistance to the etchant and promote its adhesion to the silicon wafer.