Abstract: Imminent control instability is detected in a system that applies a stimulus to an object. The system provides a parameter signal that represents a system parameter indicating oscillation of the object while the stimulus is being applied to the object. The method comprises monitoring maximum amplitude of a dominant tone in a selected frequency band of the parameter signal; and taking an action to avoid imminent control instability if the maximum amplitude persists over a specified period of time.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.

Abstract: A trimming circuit for a semiconductor memory apparatus includes a trimming code generator configured to provide a trimming code signal group by performing one of addition and subtraction using a test mode signal and a fuse coding signal, and an internal voltage generator configured to provide trimmed voltage in response to the trimming code signal group as output voltage.

Abstract: A time qualified frequency mask trigger triggers on signals that violate a frequency mask for at least a specified time duration. A frame of digital data representing an input signal is transformed into a frequency spectrum having at least one frequency bin, with each frequency bin having a power amplitude value. A trigger signal is generated when any of the power amplitude values violates an associated reference power level for at least a specified time duration.

Abstract: A power trigger is provided having time qualified and sequential event capability. Digital data representing an input signal is converted into a power signal. The power signal is compared to a trigger level. A trigger signal is generated when the power signal violates the trigger level for either at least or less than a specified time duration. Alternatively, the trigger signal may be generated on the occurrence of a sequence of such violations.

Abstract: Embodiments of the present disclosure provide a method that includes producing an integrated circuit device configured to include a system on a chip (SOC) and accessing test code within the SOC during the producing. The method further includes self-testing the integrated circuit device with the test code.

Abstract: An Arbitrary Waveform Generator has a controller programmed to generate a sequence of test waveforms using previously-defined waveform data files. The controller generates this series of test waveforms by direct synthesis to cause each waveform to contain a respective different predetermined amount of Rj, Sj and ISI jitter components. In this way, the Arbitrary Waveform Generator produces a sequence of waveforms incorporating varying amounts of ISI to sweep the ISI jitter components from an initial amount of ISI, for example, zero ISI, and continually increment the amount of ISI to a full unit interval of ISI in predetermined increments, for example, 0.1 UI steps.

Abstract: A system and method to measure a delay of an individual logic gate in an unmodified form on a chip using a digitally reconfigurable ring oscillator (RO) that is on the chip is provided. A system of linear equations is established for different configuration settings of the ring oscillator and solved to determine a delay of an individual gate.

Abstract: A method and system for obtaining the characteristic impedance of an electrical winding by measuring the input and output voltages and the currents within a winding across a low frequency range, and applying transmission line properties to model the winding. The characteristic impedance (Zc) is directly proportional to the capacitance of the winding, and is independent of external circuits. Thus any changes to Zc will reflect movements of the winding that would affect the capacitance. Because Zc has a smooth and robust monotonical relationship with frequency of the applied signal, the resulting curve is exponential in shape. A relative comparison between Zc curves will provide a clear indication of the overall axial or radial winding movements, or winding faults, which can be used to assess the overall health of the winding.

Abstract: A method of the present invention includes: inputting a state transition diagram that represents first transitions between a plurality of states; inputting a mapping function that maps a given state to a value within a certain range; mapping each of the states with the mapping function to obtain mapping values, and perform grouping of the states into a plurality of groups based on the mapping values; for each of pairs of two groups obtained by combining two of the groups, setting a second transition from one group of the two groups to the other group when there is at least one first transition between therein; generating a representative transition path which is a sequence of the second transitions by tracing sequentially the second transitions; converting the representative transition path to a transition path in the state transition diagram; outputting the transition path as the test case.

Abstract: Some embodiments of the present invention provide a system that generates a load for a computer system in accordance with a predetermined load profile. During operation, the load for the computer system is generated by modulating the load using pulse-width modulation, wherein the load is periodically cycled between at least two different test load levels so that a moving window average of the modulated load follows the predetermined load profile.

Abstract: A frequency mask trigger having frequency selective amplitude discrimination capability is provided for triggering when selected frequency components of an input signal fail to reach a desired power level. A frame of digital data representing an input signal is transformed into a frequency spectrum having at least one frequency bin, each frequency bin having a power amplitude value. Each power amplitude value is compared to an upper lower reference power levels and a lower reference power level. A trigger signal is generated when the power amplitude value in any frequency bin is above the lower reference power level and below the upper reference power level for a specified time duration.

Abstract: A signal generator produces a victim signal having crosstalk emulation by filtering and combining a victim signal waveform record file and an aggressor signal waveform record file generated using parameters selected by a user. A signal channel or a cascaded signal channel is characterized using one or more S-parameter arrays. The S-parameter array or arrays represent a mixed-mode multiple-port device under test. Coefficients of a NEXT filter, a FEXT filter and a forward transmission filter are derived from selected S-parameters of the S-parameter array. The aggressor signal is filtered individually by the NEXT and FEXT filters. The victim signal is summed with the filtered aggressor signal from the NEXT filter with the resulting summed signal being filtered by the forward transmission filter. The filtered signal from the forward transmission filter is summed with the filtered aggressor signal from the FEXT filter to generate a victim signal having crosstalk emulation.

Abstract: Provided is a semiconductor test apparatus that tests a device under test, comprising a test unit that tests a device under test; and a serial transmitting section that transmits transmission data back and forth between the test unit and a control section controlling the test unit. The serial transmitting section includes a data sending section that sends a plurality of pieces of the transmission data in a predetermined order; a resending control section that resends the transmission data; and an expected acknowledgement ID storage section that stores an expected acknowledgement ID indicating identification data that is expected to be attached to an acknowledgement signal received on a transmission side. The resending control section judges whether resending is necessary based on (i) whether resend count information indicates that a piece of transmission data is resent data and (ii) the expected acknowledgment ID in the expected acknowledgement ID storage section.

Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

Abstract: A radio-wave propagation characteristic prediction assisting system includes a storage section, an attribute information input section, and an output section. The storage section stores attribute information of a region and reference information useful for predicting a radio-wave propagation characteristic in the region in association with each other. The attribute information input section inputs attribute information of a region whose radio-wave propagation characteristic is to be predicted. The output section searches information stored in the storage section to specify a region having an attribute which matches with the attribute information input by the attribute information input section, and outputs reference information associated with the specified region.

Abstract: A method of automating a process for controlling a voltage waveform applied to an object is provided. A first waveform for applying to the object is received. A first FFT of the first waveform is calculated. A second waveform for input to the waveform generator is determined based on the first waveform. The determined second waveform is sent to a waveform generator. A third waveform is received that is measured across the object based on a waveform generated by the waveform generator. A second FFT of the received third waveform is calculated. The third waveform is compared with the first waveform to determine a convergence status of the third waveform. If the determined convergence status is not converged, an updated waveform is calculated based on the first FFT and the second FFT and the process is repeated with the updated waveform as the determined second waveform.

Abstract: Provided is a transfer characteristic measurement apparatus that measures a transfer characteristic of a circuit under test between input and output, comprising a test signal input section that generates a test signal by adding together a carrier signal having a prescribed frequency and an additional signal having a frequency that differs from the prescribed frequency, and inputs the test signal to the circuit under test; and a transfer characteristic measuring section that measures the transfer characteristic of the circuit under test at the frequency of the additional signal based on a result from a measurement of an output signal output by the circuit under test. The circuit under test may be formed on a semiconductor chip. The circuit under test may correct a signal input to the semiconductor chip, and outputs the corrected signal. The semiconductor chip may further include a sampling circuit that samples the output signal of the circuit under test at the frequency of the carrier signal.

Abstract: The invention relates to a method for determining a state of health of an electrochemical device in particular having improved reliability. Said method in particular consists of: applying (10) to said electrochemical device an input signal comprising electrical excitations of different categories, and measuring an output signal (20) including the response signals to each electrical excitation; estimating (41) at least one first parameter from an electrical excitation belonging to a first category and the corresponding response signal; estimating (43) said at least one physicochemical parameter representative of the physicochemical behavior of the device from an electrical excitation of a different category, of the corresponding response signal and said first estimated parameter; estimating (50) said state of health of the electrochemical device as deviation between the previously estimated value of the physicochemical parameter and a reference value.

Abstract: Provided is a test apparatus 10, which includes: a plurality of test modules 150, each of which is connected to any of the plurality of devices under test 100 to supply a test signal to the connected device under test 100; a plurality of site controllers 130 that control the plurality of test modules 150 to test the respective plurality of devices under test 100 simultaneously; a connection setting device 140 that sets a connection mode between the plurality of site controllers 130 and the plurality of test modules 150 so that each of the test modules 150 is connected to any of the plurality of site controllers 130; and a plurality of system controllers 110, each of which controls any of the plurality of site controllers 130, in which a predetermined system controller of the plurality of system controllers 110 assigns, in response to a request from another system controller of the system controllers, a site controller of the site controllers, which is to be controlled by the another system controller.

Abstract: An integrated circuit with Built-in Self Test (BiST) is described. The integrated circuit includes a signal generator used to perform a BiST on the integrated circuit. The integrated circuit also includes a local oscillator used by the signal generator to generate one or more test signals used to perform the BiST on the integrated circuit.

Abstract: A realtime display compression for a waveform image uses a priority basis for combining groups of pixels when producing a compressed waveform image in order to preserve intensity information. As an example successive lines of data for the waveform image are demultiplexed into line buffers in a circulating manner, the number of line buffers being a function of the maximum desired integer compression ratio. The outputs from the line buffers are aligned and the corresponding pixels are combined according to a desired compression ratio, one output line for each integer compression ratio. The appropriate compressed line is selected as the output line according to the desired compression ratio, with the totality of the output lines forming the compressed waveform image.

Abstract: The device for simulating a rectified constant impedance load provide by the present invention is to test a power product and comprises an analog-digital converter, a digital signal processor, a digital-analog converter, and an active electrical load module in order to replacing the passive components of a traditional rectified passive load.

Abstract: A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating device via a communication network. The method includes the at least one responding device receiving a trigger message from the initiating device. The trigger message includes a state transition time or a time from which a state transition time is obtainable. The method further includes the at least one responding device jointly making a respective state transition at the state transition time. A responding device, and a system including the initiating device and the responding device are also disclosed.

Abstract: A method and device are disclosed for measuring potentiometric measuring probes. An exemplary method includes feeding two test voltages comprising a harmonic wave Ueg with a base frequency fg and the harmonic wave Uer with a base frequency fr into two cores of a connecting cable through voltage source impedances, respectively. The voltage between an indicating electrode and a reference electrode, and the AC responding signal resulting from the two test voltages are passed to an amplifier and further to a transfer function unit having transfer functions (Hg, Hr), an A/D converter, and a Fourier transformation unit, to calculate a potential Ux and the two test responses Ug and Ur, respectively. Two calibration responses Uehg and Uehr are determined, wherein Uehg includes a product of Ueg and Hg, and wherein Uehr includes a product of Uer and Hr.

Abstract: Methods for generating realistic waveform vectors with controllable amplitude noise and timing jitter, simulatable in a computer-based simulation environment are disclosed. In one implementation, a transition vector is created from a sequence of bits having a rise time and a fall time, in which the transition vector comprises voltage values at timings corresponding to midpoints of transitions in the bit sequence. A jittered transition vector is created from the transition vector, in which the timing of the transitions in the jittered transition vector include timing jitter. An upscaled jittered transition vector is then formed having additional points, in which at least some of the additional points comprise corners of the sequence of bits. The voltages of the additional points are set by the sequence of bits, and the timing of the corners are set in accordance with the rise time and the fall time.

Abstract: There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Abstract: A temperature sensor includes a counting signal generation unit, a counting signal decoding unit, an input reference voltage selection unit, and a latch pulse generation unit. The counting signal generation unit is configured to generate one or more counting signals in response to an oscillation signal. The counting signal decoding unit is configured to decode the one or more counting signals and to generate one or more test selection signals and an end signal. The input reference voltage selection unit is configured to output a first selection reference voltage or a second selection reference voltage as an input reference voltage in response to the one or more test selection signals. The latch pulse generation unit is configured to generate one or more latch pulses in response to the one or more test selection signals.

Abstract: An arrangement to determine at least one electrical feature of an electrical device including a signal injection unit configured to inject first and second test signals into the electrical device, a signal conversion unit configured to measure electrical qualities in electrical circuits resulting from the test signals, and a processing device including at least two input channels configured to receive the measured electrical quantities and to determine the electrical feature based on the measured electrical quantities. The arrangement further may include a mixing unit configured to add the measurements of a first electrical quantity determined from the test signals and based thereon generate a first mixed signal, to add the measurements of a second electrical quantity from the test signals and based thereon generate a second mixed signal, and to supply the first and second mixed signals to first and second input channels.

Abstract: Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then.

Abstract: A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.

Abstract: A method, circuit, and computer program product for receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is a time-shifted version of the first intermediate signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. An anticipated differential change in the output signal is determined, the anticipated differential change to occur based upon a transition in the first reference signal. A realized differential change in the output signal is measured, the realized differential change occurring based upon a transition in the first reference signal. The realized differential change in the output signal is compared to the anticipated differential change in the output signal to determine a nonlinearity indicator.

Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.

Abstract: A circuit arrangement, system, and method to test a device with a plurality of pins for electric overstress and transient induced latch-up characteristics. The circuit arrangement includes an inverting operational amplifier with a unity gain to receive a triggering signal and supply an inverted signal to a power amplifier. The power amplifier transforms the inverted signal into a test signal, which is received by a ratio circuit. The test signal is further operable to test the electric overstress and transient induced latch-up characteristics of the device. The ratio circuit transforms the test signal into a ratio signal. The ratio signal has a voltage magnitude that corresponds to the current magnitude of the test signal. The test signal and ratio signal are measured to determine if, during testing, the device or a component of the device has failed.

Abstract: Methodology and circuitry for determining if a device, such as a cellular phone or personal digital assistant has been tapped is disclosed. The device includes an accelerometer and in response to an acceleration, the accelerometer outputs an acceleration signal. The accelerometer may continuously output an acceleration signal even if no acceleration occurs. A tap detection device receives the temporally sampled acceleration signal and takes the first derivative of the temporally sampled acceleration signal producing one or more derivative values. The tap detection system compares each derivative value to a threshold value and if the derivative value exceeds the threshold a tap is detected. By taking the derivative of the acceleration signal, the noise floor for the acceleration signal is reduced leading to more accurate results with less false positives and less positive negatives.

Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: A method and system for testing a Telephony User Interface is disclosed. Voice prompts of the Telephony User Interface are converted into tone prompts that are representative thereof. Each tone prompt can have a predetermined frequency and/or duration, so that it is readily recognizable by a Telephony User Interface tester. Thus, automation of the testing of Telephony User Interface is enhanced.

Abstract: A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.

Abstract: A quadrature amplitude demodulator demodulates a modulated signal on which quadrature amplitude modulation is performed. Oscillators generate an in-phase carrier signal having a rectangular wave, a trapezoidal wave or a waveform similar to these, and a quadrature carrier signal, the phase of which is shifted by ¼ cycle relative to the in-phase signal. First and second mixers respectively perform mixing of the modulated signal with the in-phase signal and the quadrature carrier signal. First and second integrators respectively integrate output signals of the first and the second mixers, for a predetermined period in accordance with the cycle of the in-phase carrier signal and the quadrature carrier signal. First and second A/D converters respectively convert outputs of the first and the second integrators into digital values.

Abstract: An integrated circuit includes a first storage location, a first generator, a converter, and a second generator. The first storage location is operable to store a first adjustment value. The first generator is coupled to the first storage location, is operable to generate a first signal having a first characteristic, and includes a first adjuster operable to change the first characteristic in response to the first adjustment value. The converter is coupled to the first storage location and is operable to generate from the first adjustment value a modified adjustment value. The second generator is coupled to the converter, is operable to generate a second signal having a second characteristic, and includes a second adjuster operable to change the second characteristic in response to the modified adjustment value.

Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.

Abstract: An apparatus for reading out a modulated time-continuous sensor output signal includes a loop filter, a sample-quantizer and a feedback circuit. The loop filter filters the sensor output signal to provide a filtered sensor output signal, and amplifies frequency proportions present in a frequency range. The sample-quantizer samples and quantizes the filtered sensor output signal to provide a time-discrete, quantized sensor output signal. The feedback circuit feeds a feedback signal based on the time-discrete, quantized sensor output signal back to the loop filter and provides a readout signal.

Abstract: Provided is a test apparatus for testing a device under test, including: a plurality of signal supply sections that output test signals at different timing from each other; and a connection section that connects lines of wiring transmitting the test signals respectively outputted from the signal supply sections with each other, connects the lines of wiring to an input terminal of the device under test, and inputs the test signals to the input terminal after superposing the test signals. The connection section may include a performance board to which the device under test is mounted, where the lines of wiring are connected with each other on the performance board.

Abstract: Stability of a control system for a materials testing system using specified filter parameters is confirmed by inputting to the control system a test signal having a predetermined waveform, automatically monitoring the output of the materials testing system, and automatically comparing the output to a threshold. If the output exceeds the threshold, a first action is taken. If the output does not exceed the threshold, input of a command signal to the control system is permitted.

Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

Abstract: A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so as to execute a test algorithm, so as to generate a transmission signal upon execution of the test algorithm, and so as to generate a test environment with reference to the transmission signal. The platform module is operable so as to conduct testing of the DUT using the test information stored in the test parameter-generating device under the test environment generated by the test parameter-generating device.