Abstract: A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by the device under test in response to the test signal, a voltage measuring section that detects a DC voltage of the signal output by the driver section, and an output side adjusting section that adjusts a duty ratio of the signal output by the driver section according to the DC voltage detected by the voltage measuring section.

Abstract: A computer-implemented method of testing interoperability of a web service against a plurality of web services tools may include steps of providing a web services description language file (WSDL) that describes the web service to be tested; selecting at least one of the plurality of web services tools; generating and compiling sets of proxy files for each selected web service tool based upon the provided WSDL file and loading the generated and compiled proxy files into memory; generating an XML test case for each of the generated and compiled sets of proxy files, the XML test case including dummy variables for each operation of the provided WSDL file; populating the generated XML test case with values for at least some of the dummy variables, and invoking a targeted web service from a selected client platform using the populated XML test case and providing results for each invocation.

Abstract: A method of generating multi-frame test signals, a testing apparatus, and method for testing integrated circuits (ICs) with the multi-frame test signals. An analog source generates an analog source signal at a constant power and a constant frequency that is modulated with a first modulating signal (e.g., I) to output a first test signal having first signal parameters including a power level, a frequency and a modulation scheme. The modulating is repeated with a second modulating signal (e.g., Q) to output a second test signal having second signal parameters including a power level, a frequency and a modulation scheme. At least one of the first and second signal parameters are different. The modulating signals are generated by a digital signal source. The first and second test signal are combined by placing the first test signal on the first frame (frame 1) and the second test signal on the second frame (frame 2) of the multi-frame test signal.

Abstract: Disclosed is provided an apparatus and a method for operating a macro command and inputting a macro command, wherein the apparatus including a storing unit storing control signals received from a control device for selecting of a menu item of a host device, a creating unit creating the macro command combined with the control signals, and an executing unit reading the macro command and executing functions corresponding to the respective menu item of the host device according to a combination sequence of the control signals included in the read macro command.

Abstract: A voltage pulse is transmitted into a test object, and returned reflection pulses are evaluated to determine the location of a fault in the test object. The return signal includes a reflection from the fault and undesired interfering reflection pulses, which are removed or compensated-out from the return signal to produce a corrected pulse diagram. A circuit arrangement for this includes a bi-directional coupler, a separation filter, a measured signal detection circuit with two input channels, a memory storing a database, a computer processor, and a measured signal evaluation unit. A method in this regard includes a first step of measuring the input impedance of the test object, and a second step of measuring the return signal pulses, transforming the return signal to the frequency domain, compensating the frequency domain data to remove interference, transforming the data back to the time domain, and representing or evaluating the pulse diagram.

Abstract: There is implemented an instrument check system for storing check data of an instrument for a long period of time in an instrument body in a stylized format. The instrument check system comprises an instrument provided with an AD converter for converting a voltage value applied to an input terminal into a digital value, a checking PC connected to the instrument so as to communicate with the instrument, a voltage generation unit for applying a checking voltage value to the input terminal, a check data storage unit formed in the instrument, wherein the checking PC comprises an input check means for acquiring data that is converted from the voltage value into the digital value by the AD converter upon giving an instruction to the voltage generation unit, and storing the data in the check data storage unit.

Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.

Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: Methods for determining customized defect detection inspection plans are provided. One method includes fabricating a test chip and generating test chip data from the fabricated test chip. Then, defining systematic signatures from the generated test chip data and identifying a yield relevant systematic signature from the defined systematic signatures. The method includes identifying a layout pattern associated with the yield relevant systematic signature and locating the identified layout pattern on a process module layer of a product chip. Further, the method includes defining a customized defect detection inspection or metrology methodology for detecting systematic defects on the process module layer based on the identified layout pattern associated with the yield relevant systematic signature.

Abstract: In an example embodiment, an integrated circuit comprises a mixer circuit and a local oscillator circuit. During testing a frequency divider circuit in the integrated circuit divides a local oscillator signal to a frequency below a normal operating range of the local oscillator. The integrated circuit applies the divided local oscillator signal to the mixer circuit instead of the local oscillator signal during testing. Signal properties of a signal derived from the mixer circuit are measured while the divided local oscillator signal is applied to the mixer circuit.

Abstract: Described is a system and method for frequency offset testing. The system comprises an electronic device, a first testing device providing a reference clock signal at a first frequency to the electronic device, and a second testing device receiving data from the electronic device at the first frequency and transmitting data to the electronic device at a second frequency. The second frequency is equal to a product of the first frequency and a frequency offset value.

Abstract: The invention discloses a circuit testing apparatus for testing a device under test. The circuit testing apparatus includes a precision measurement unit, a signal transformation module, and a microprocessor. The precision measurement unit is coupled to the device under test for providing a testing signal and receiving a measurement signal generated according to the testing signal. The signal transformation module is coupled to the precision measurement unit for receiving the measurement signal and transforming the measurement signal to a signal measurement result according to a predetermined manner. The microprocessor is coupled to the precision measurement unit and the signal transformation module for examining the signal measurement result to determine a test result for the device under test.

Abstract: The present invention is directed to a method and a system to evaluate operational characteristics of an electronic circuit. The method includes generating a visual display, on a monitor, of an eye diagram viewer. The eye diagram viewer is used to establish a test parameter for the circuit. Accessed is data that includes a graphical file containing eye diagram information corresponding to the test parameter. A visually perceivable image of the eye diagram information is provided in response to the test parameter. Specifically, the eye diagram viewer is used to establish an eye diagram information identifier by displaying in a plurality of test condition selector screens one of a multiple condition values for the test condition parameters. The graphical file containing the eye diagram information corresponding to the eye diagram information identifier is obtained from the server and displayed.

Abstract: Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

Abstract: According to one embodiment, a low phase noise testing system includes a tester providing a high phase noise digital channel output. The low phase noise testing system further includes a crystal filter configured to receive the digital channel output and to pass a narrow frequency range from the digital channel output, whereby the high phase noise digital channel output is converted to a low phase noise clock for use by a device under test. The crystal filter can be, for example, a monolithic crystal filter or a discrete crystal filter.

Abstract: A method and a corresponding system for testing an analog signal under test includes using knowledge of at least one parameter of the signal under test. The method includes generating a reference signal using the knowledge of at least one parameter of the signal under test, combining the generated reference signal with the signal under test, resulting in a combination signal, and evaluating the combination signal for testing the signal under test.

Abstract: Dispersive array acoustic data are acquired. A histogram is determined from the semblance-frequency coherence of the data. The low frequency limit of the data is estimated by matching the statistics of the histogram to the statistics of a modeling function.

Abstract: The present disclosure relates to a system and method for mapping system transfer functions. Accordingly, some operations may include receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is at least partially based upon a second reference signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. A first anticipated differential change in the output signal is determined, the first anticipated differential change to occur based upon a transition in the first reference signal. A second anticipated differential change in the output signal is determined, the second anticipated differential change to occur based upon a transition in the second reference signal. Numerous other operations are also within the scope of the present disclosure.

Abstract: A main driver and a sub-driver control circuit are provided respectively to receive a test pattern signal for testing a device. The main driver drives the test pattern signal to output a first driven signal. The sub-driver control circuit modifies the test pattern signal to output a modified pattern signal. The modified pattern signal is provided to a sub-driver. The first sub-driver drives the modified pattern signal to output a second driven signal. The first and the second driven signals are combined. The combined signal is provided to a terminal of the device as a test signal.

Abstract: The disclosure concerns a semiconductor tester for testing a memory under test. The semiconductor tester comprises a pattern generator generating address information on the pages and generating a test pattern; a waveform shaper shaping the test pattern and outputting a test signal based on the shaped test pattern to the memory cells in the page identified by the address information; a comparator comparing a result signal output from the memory under test receiving the test signal with an expectation value; and a bad block memory storing information on a bad block in the memory under test in advance, when the page identified by the address information is included in the bad block, the bad block memory outputting a bad signal used to skip from the address information on the page included in the bad block to the address information on the page included in a next block under test.

Abstract: A method for detecting a leading edge blanking parameter of a power management chip includes generating a pulse signal and inputting the pulse signal to the power management chip, wherein the amplitude of the pulse signal will cause a PWM signal of the power management chip to change its duty cycle; detecting the PWM signal to generate a detecting result; when the detecting result indicates that the duty cycle of the PWM signal does not change, adjusting a pulse width of the pulse signal to generate an adjusted pulse signal, inputting the adjusted pulse signal to the power management chip and detecting the PWM signal; and when the detecting result indicates that the duty cycle of the PWM signal changes, determining the leading edge blanking parameter of the power management chip according to the pulse width of the pulse signal.

Abstract: There is provided a test apparatus for testing a device under test. The test apparatus includes first and second period generators that respectively generate test period signals indicating test periods for testing the device under test, a plurality of input/output sections that are provided in correspondence with a plurality of terminals of the device under test, wherein each of the plurality of input/output sections, in accordance with a test period supplied thereto, outputs a test signal to a corresponding one of the plurality of terminals and receives an output signal output from the corresponding terminal, and a plurality of selecting sections that are provided in correspondence with the plurality of input/output sections, wherein each of the plurality of selecting sections selects one of the test period signals generated by the first and second period generators so as to be supplied to a corresponding one of the plurality of input/output sections.

Abstract: One embodiment of the present invention provides a system that dynamically adjusts data resolution during proactive-fault-monitoring in a computer system. During operation, the system temporarily stores high-resolution data for a telemetry signal from the computer system in a buffer. The system then generates low-resolution data for the telemetry signal from the high-resolution data. Next, the system monitors the low-resolution data, and while doing so, determines if an anomaly exists in the low-resolution data. If an anomaly exists in the low-resolution data, the system records the high-resolution data from the buffer on a storage device.

Abstract: Provided is a waveform generating apparatus that generates analog signal based on fundamental waveform data including a predetermined number of samples, including: phase difference calculating section that calculates phase difference between the initial phase and final phase of a signal resulting from FSK-modulating, based on first set of modulation frequencies, input data sequence to be modulated onto a signal that the waveform generating apparatus generates; frequency calculating section that calculates correction frequency corresponding to quotient of dividing, by the predetermined number of samples, residue of dividing the phase difference by 2?; waveform producing section that produces fundamental waveform data representing a waveform corresponding to a signal resulting from FSK-modulating the input data sequence based on second set of modulation frequencies obtained by subtracting the correction frequency from the modulation frequencies in the first set; and output section that outputs a signal repeatin

Abstract: There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing compara

Abstract: A three-port TDR front end comprises numerous components. An exemplary three-port TDR front end is a DSL modem. Information-bearing TDR signals are distorted as they pass through these components. With a perfect model of the response of its front-end, a TDR system usually can compensate for the effects of its front-end. In reality, however, the electrical characteristics of each component vary from design-to-design, board-to-board, and slowly over time The result is imperfect knowledge about the true response of the front-end, errors in the model of the front-end, and degraded TDR performance. At least for this reason it is important to precisely calibrate the response of the TDR front-end through the use of a TDR modeling system.

Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.

Abstract: There is provided a test apparatus for testing a device under test, which includes a plurality of drivers which output signals to the device under test, an output control section which controls the plurality of drivers to output a plurality of signals respectively, a calculating section which calculates skews of the plurality of signals output from the plurality of drivers respectively, based on a combination signal obtained by combining the plurality of signals, and an adjusting section which adjusts the timings to output signals to be output from the plurality of drivers, based on the skews.

Abstract: A test definer, a method for automatically determining functional tests for a printed circuit board (PCB) having analog components and a test system. In one embodiment, the test definer includes: (1) a circuit builder configured to generate a representative circuit of the PCB based on schematic information thereof, (2) a circuit organizer configured to partition the representative circuit into testable sub-circuits and (3) a specification generator configured to automatically determine functionality tests for the PCB based on the sub-circuits, obtain expected values from the functionality tests and generate platform-independent specifications representing the functionality tests and the expected values.

Abstract: An object of this invention is to realize a pulse pattern generating apparatus that outputs a test signal of high waveform quality even when the shape of an eye pattern is changed. This invention is an improvement of a pulse pattern generating apparatus that generates a test signal of a predetermined pattern by using plural digital-analog converters and outputs the test signal to a test subject.

Abstract: An amplifier having programmable operational characteristics and a serial communications interface is fabricated on an integrated circuit (IC). The serial communications interface controls the operational characteristics, e.g., gain, frequency response, etc., of the amplifier. A multiplexer (MUX) may also be included on the IC and may be controlled by the serial communications interface. Status of the amplifier may also be obtained through the serial communications interface. The pin count of the IC package may be kept to a minimum by using the serial communications interface.

Abstract: System and method for specifying a signal analysis function. First user input is received, e.g., to a graphical user interface (GUI), indicating a parameter for a first operation implementing at least a portion of the function. The first operation is programmatically included in a sweep loop. Second user input is received specifying a sweep configuration for a sweep on the parameter. The signal includes signal data, e.g., signal plot data or tabular data. The sweep configuration includes: a range of values for the indicated parameter, a number of iterations for the sweep, an interpolation type, step size for the sweep on the indicated parameter, specific values in the range of values for the parameter, source for at least some of the sweep configuration, and/or resultant data. The sweep is performed on the parameter per the sweep configuration, generating resultant data which is stored, and optionally displayed, e.g., in the GUI.

Abstract: Provided is a test apparatus that tests a device under test that outputs a plurality of modulated signals modulated with carrier signals having frequencies identical to each other, including a synthesizing section that synthesizes the plurality of modulated signals to output a synthesized signal; an AD converting section that samples the synthesized signal to output a digital signal corresponding to the synthesized signal; and a judging section that judges acceptability of the plurality of modulated signals output by the device under test, based on the digital signal.

Abstract: A system and method for detecting and identifying electronic devices based on their unintended electromagnetic emissions (“UEE”) signals is presented. During device classification, UEE signals are measured from a plurality of test devices and characteristic data is obtained from the UEE signal emitted from each test device. Using the characteristic data, a threshold value and ideal pulse template can be determined for each test device and stored in a memory. An ideal stimulation signal is also determined for each test device and stored in the memory. During device detection, the ideal stimulation signal is applied to the environment in which a target device is suspected of being located. Stimulated UEE signals are measured from the target device and processed. The processed measurement data is compared to stored power threshold values and ideal pulse templates to determine if the target device is present.

Abstract: Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.

Abstract: A signal generator generates amplitude noise on a selected segment of a test signal. A user interface is used for selecting a segment of the test signal and an associated power level for applying amplitude noise at a selected power level to the test signal segment. A signal processing unit compiles the selected power level of the selected segment with the test signal to generate digital data representative of the test signal with selected segments having amplitude noise. A waveform generator receives the digital data and generating a test signal output having amplitude noise at selected segments of the test signal. The method includes the steps of: selecting a segment of the test signal to add amplitude noise; selecting a power level for the amplitude noise; and applying the amplitude noise at the selected power level to the selected segment of the test signal.

Abstract: An apparatus for assisting the creation of a test program, to be run on a simulator that automatically tests an electronic unit, to thereby reduce the number of preparatory steps and enhance the reliability of the automatic testing. The apparatus is a test apparatus including: a simulating unit for simulating a target to be controlled by a control unit; and a testing unit for testing the operation of the control unit based on a relationship between a pattern signal input to the control unit and an output signal output from the simulating unit in response to the pattern signal, wherein the testing unit tests the operation of the control unit at predetermined timing and, if a decision is not obtained that the control unit is operating properly, retries the decision a predetermined number of times.

Abstract: A time series data dimensional compression apparatus performing dimensional compression for improving the efficiency of searching for time series data without losing the features of data. The compression is made to a determined dimension so that a larger volume of information may be extracted therein. A time series subsequence generating section (112) generates time series subsequences of a specified segment width into which a plurality of pieces of time series data generated at a time series data generating section (110) are divided. A singular value decomposition processing section (113) performs singular value decomposition on all of the time series subsequences. A dimensional compression time series data generating section (114) generates dimensional compression time series data by using high-order elements of the singular value decomposition as a representative value of the time series subsequence.

Abstract: The system and method provide security and cargo handling personnel a versatile tool to rapidly check cargo for hidden radiological materials, explosives, drugs, and chemical weapons material. Gamma ray emission is stimulated by a pulsed neutron source. The gamma ray signature is used to classify the material. Passive gamma ray analysis can be used to detect and identify radiological material. The method of determining the contents of a target includes irradiating a target; detecting at least one spectrum emitted from the target; performing a primary analysis to extract a first set of indicators; and performing a secondary analysis to decide the contents of the target. The primary analysis utilizes either a least squares analysis or principal component analysis. The secondary analysis utilizes a generalized likelihood ratio test or support vector machines.

Abstract: There is provided a test apparatus for testing a device under test. The test apparatus includes first and second period generators that respectively generate test period signals indicating test periods for testing the device under test, a plurality of input/output sections that are provided in correspondence with a plurality of terminals of the device under test, wherein each of the plurality of input/output sections, in accordance with a test period supplied thereto, outputs a test signal to a corresponding one of the plurality of terminals and receives an output signal output from the corresponding terminal, and a plurality of selecting sections that are provided in correspondence with the plurality of input/output sections, wherein each of the plurality of selecting sections selects one of the test period signals generated by the first and second period generators so as to be supplied to a corresponding one of the plurality of input/output sections.

Abstract: An Arbitrary Waveform Generator has a controller programmed to generate a sequence of test waveforms using previously-defined waveform data files. The controller generates this series of test waveforms by direct synthesis to cause said each waveform to contain a respective different predetermined amount of Rj, Sj and ISI jitter components. In this way, the Arbitrary Waveform Generator produces a sequence of waveforms incorporating varying amounts of ISI to sweep said ISI jitter components from a an initial amount of ISI, for example, zero ISI, and continually increment said amount of ISI to a full unit interval of ISI in predetermined increments, for example, 0.1 UI steps.

Abstract: Described are a filter characteristic measuring method and system capable of measuring a gain of an analog filter adapted in a DUT (Device Under Test) and a frequency response at a high speed, wherein the filter characteristic measuring method includes the steps of generating an impulse signal; applying the impulse signal to the DUT having an analog filter through a digital channel; and measuring a gain of the analog filter in the DUT and a frequency characteristic by using an output of the analog filter.

Abstract: An energy measurement system including a radio frequency (“RF”) device powered by a solar panel. The RF device comprising a wireless communication port operative to transmit and receive communication over a wireless network of additional RF devices. The energy measurement system able to transmit energy parameters of the RF device over the wireless network.

Abstract: A system and method for testing an integrated circuit is provided. In one embodiment, a method includes comparing the signal level of the output signal of the integrated circuit to the signal level of a reference signal, wherein a comparison signal is output, which has a first or a second value depending on whether the actual signal level of the output signal is above or below the actual signal level of the reference signal; determining the value of the comparison signal at a certain time; evaluating the value of the comparison signal determined at the time by way of a default; and outputting an error signal if the determined value of the comparison signal does not correspond to the default.

Abstract: A system analyzer may generate an estimated frequency response of a device, system, communication medium, or combination thereof by utilizing a stimulus signal that is robust against IQ modulator impairments. A stimulus generator may be used to generate a plurality of discrete tones according to a frequency spacing and a frequency offset. The frequency spacing and the frequency offset cause spectrally inverted spurs (generated by impairments of the IQ modulator) to occur at frequencies other than frequencies of said modulated signal that are associated with said plurality of discrete tones. Additionally, by implementing a Discrete Fourier Transform (DFT) to possess a frequency resolution equal to the frequency offset, there is no leakage of power associated with the spectrally inverted spurs into frequency bins of the DFT associated with the desired frequency components. Likewise, leakage between the desired frequency components and leakage associated with the local oscillator may be avoided.

Abstract: A method for measuring performance of a noise cancellation system that is operable to cancel noise is provided. The method includes generating a first model of a target noise. The first model represents the target noise in a form that is received at a location remote from a noise source of the target noise and within a defined environment. The method also includes generating a second model of a cancellation noise. The cancellation noise is configured to at least partially cancel the target noise when combined with the target noise. The second model represents the cancellation noise in a form that is received at the location. The method also includes determining, using the first model and the second model, a cancellation error value indicative of only a portion of the target noise that remains when the target noise and the cancellation noise are combined.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.

Abstract: A method for measuring a bandwidth of a signal path between a data source and a data recipient involves sending a block of test data from the data source along the signal path to the data recipient, using that test data to obtain a measured bandwidth of the signal path, and transferring information from the data source along the signal path to the data recipient in accordance with the measured bandwidth. The measured bandwidth value can be calculated each time the data recipient accesses a website or the measured bandwidth value can be retained for future use.