Abstract: An electronic device (120) includes: an input connector (121), including at least three address pins and plural data pins; a function chip (123), including address pins and data pins corresponding to those of the input connector, and directly connected to the input connector by the data pins thereof; an adder disposed between the input connector and the function chip, and including at least three input pins and at least three output pins, the input pins being connected to the address pins of the input connector of the electronic device in one-to-one correspondence, the output pins being connected to the address pins of the function chip; and an output connector (124), including at least three address pins and plural data pins, the address pins being connected to the output pins of the adder in one-to-one correspondence, the data pins being respectively connected to the data pins of the input connector.

Abstract: A system comprising a communication (COM) port server that, together with a COM port client, establishes COM port redirection over a network and communicates data with a serial port, at least one embedded application which is configured to communicate data via a serial port, and at least one virtual serial port application communicatively coupled to the embedded application and the COM port server. The virtual serial port application translates data communicated between the COM port server and the embedded application as if the COM port server and the embedded application were connected by a serial communication link.

Abstract: Serializing and deserializing circuits are provided on an emulator circuit board to group input and output signals of programmable logic devices for routing through a cross point switch. In one instance, the input and output signals of the programmable logic devices are time-multiplexed signals of virtual interconnections. The cross point switch can be configured for static or dynamically scheduled operations.

Abstract: Disclosed is a SCSI target device simulator consisting of a personal computer, a SCSI host adapter board, and simulator software. The SCSI target device simulator is employed to test SCSI host adapter systems by simulating multiple SCSI target devices for test purposes. The simulated SCSI target devices may be configured to imitate a wide variety of different SCSI target device types, with an equally wide variety of configuration settings within a single SCSI target device type. A user may quickly create and change simulated SCSI target devices for a test system. The SCSI target device simulator may also be configured so that the simulated SCSI target devices respond in a specified manner to SCSI commands and SCSI task management commands. Controlling the simulated SCSI target device responses to SCSI commands and SCSI task management commands allows a user to easily configure and test a SCSI host adapter device for specific operational scenarios.

Abstract: A software tool for modeling and generating user windows of a graphical user interface of a software application has a modeling component for creating models of window types and instances thereof, a conversion component for converting model information into ASCII code, a library component for storing reusable code, and a window generation component for generating graphical user interfaces windows. The tool is characterized in that graphical user interface windows are generated in a batch process wherein certain fields shared by the windows are automatically populated with the appropriate application code taken from or inherited from the wintype model.

Abstract: In a definition file, a convention including a definition regulated with respect to a configuration of nodes which are information elements of protocol messages in communication with a communication terminal to be evaluated is described. An interface library is configured so as to include an application program interface which can provide and receive operational information with respect to the nodes of the protocol messages to and from an exterior section. A memory managing section manages various data relating to the nodes of the protocol messages. A decode processing section specifies a data region and a value of data allocated to each node in the protocol messages by processing to decode the protocol messages along the definition regulated in the definition file and in accordance with the operational information from the exterior section to the interface library, and delivers data for each node corresponding to the protocol messages to the memory managing section.

Abstract: An emulator for a multi-mode smart card may include emulation circuitry for performing smart card applications in a plurality of operational modes. The emulator may also include a smart card connector to be connected to a smart card adapter operable in at least one of the plurality of operational modes. The smart card connector may include a plurality of contacts. Moreover, the emulator may further include a plurality of cable assemblies having first ends connected to the emulation circuitry, where each cable assembly is for a respective operational mode. Further, the emulator may also include an interface device connected between second ends of the plurality of cable assemblies and the smart card connector for selectively electrically connecting a selected cable assembly to predetermined ones of the contacts of the smart card connector based upon the at least one operational mode of the smart card adapter.

Abstract: A system and method are provided for accelerating development and debug of a printed circuit board (PCB) designed for use with a platform ASIC in advance of availability of a prototype sample of the platform ASIC. Aspects of the invention include a pin-out adapter card that implements a predefined pin-out of the ASIC and that hosts FPGA logic resources for emulating I/O functionality and some (or all) of the ASIC core logic; a PCB designed for use with the platform ASIC, wherein the PCB includes the predefined ASIC pin-out for eventually mating with the ASIC; and a socket having mating connectors on both sides for mating with the ASIC pin-out on the PCB and to the ASIC pin-out on the adapter card, respectively, for coupling the adapter card to the PCB, thereby enabling development and debug of the PCB prior to availability of ASIC samples.

Abstract: A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present invention include during slice creation, using a software tool to create a test access port (TAP) from slice resources; during instance creation, allowing a customer to design a custom chip using the software tool to select which structures to use on the slice; and based on the customer selections, reconfiguring at the instance level connections between the tap controller and the selected structures.

Abstract: A method for emulating a logic circuit having at least one set of identical logic modules is disclosed. Each logic module in a set has logic elements and memory elements that store a module state of that logic module. The logic circuit is emulated by extracting a logic module from a set of identical logic modules, translating the extracted logic module for iterative representation of the module state of each of the logic modules with a single instance of the logic elements, and configuring a logic device with the translated logic module to emulate the logic circuit.

Abstract: An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.

Abstract: An apparatus, method, and computer program are provided for controller performance monitoring in a process control system. A level of disturbance associated with the process system is determined, and at least one value identifying a stability measure of a controller in the process system is determined using the determined level of disturbance and operating data associated with operation of the process system. The at least one value is compared to at least one threshold value, and a problem with the controller is identified based on the comparison. As an example, the process system could represent a product production system. Also, the operating data could include at least one of: measurement data from one or more sensors and control data for one or more actuators. The controller may be operable to receive the measurement data and generate the control data.

Abstract: Methods, systems, apparatus, and computer-readable media are provided for disabling a BIOS-provided console redirection facility in the presence of an incompatible device. According to the method, a determination is made as to whether a port has been enabled for utilization with a BIOS-provided console redirection facility. If it is determined that a communications port has been enabled for console redirection, the BIOS is operative to determine whether a device is connected to the communications port that is incompatible with the console redirection facility. If an incompatible device is detected, the BIOS will disable the console redirection facility. Otherwise, the BIOS-provided console redirection facility is enabled for operation.

Abstract: Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. A sequence of the second information blocks is output from the data processor via a plurality of terminals thereof.

Abstract: A storage area network simulator, operable to simulate an exchange of calls emanating from a SAN management application to a plurality of manageable entities, allows analyzing SAN management application response to a particular configuration. A capture tool discovers manageable entities interconnected in a particular SAN experiencing undesirable operation. The capture tool provides exemplary calls to an agent, and gathers responses. The exemplary calls enumerate expected responses from the various manageable entities responsive to the agent. The gathered responses take the form of an XML markup script. A simulation plug-in is operative as an interface module (e.g. plug-in) for a test agent in a test environment, such as the management application test facility. The test agent employs the simulation plug-in as the API plug-in for calls emanating from the test agent.

Abstract: A multi-channel client system is provided herein, which makes it possible for a single host to receive/respond to sequence events sent from a plurality of client devices through their corresponding communication channels respectively. A socket module is executed in each client device, and a plurality of session modules each corresponding to a client device are executed in the host respectively, so that the sequence events belonging to the client devices may be received/responded to simultaneously through the channels.

Abstract: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to track performance and reliability statistics per virtual upstream and downstream port, thereby allowing a system and network management to be performed at finer granularity than what is possible using conventional physical port statistics, is provided. Particularly, a mechanism of managing per-virtual port performance metrics in a logically partitioned data processing system including allocating a subset of resources of a physical adapter to a virtual adapter of a plurality of virtual adapters is provided. The subset of resources includes a virtual port having an identifier assigned thereto. The identifier of the virtual port is associated with an address of a physical port. A metric table is associated with the virtual port, wherein the metric table includes metrics of operations that target the virtual port.

Abstract: A method for controlling and emulating the functional and logical behaviors of an array of storage devices is established by loading a software module to an array controller board. The software module is integrated into the array controller subsystem manager by providing the necessary parameters required to insert the device and can control the inbound and outbound activities (commands, data, and status packages) regardless of the type, interface, and protocol of the disk/tape device. This aspect of the method allows the user to control the drive state transition and inject errors on the inbound and outbound drive traffics. Also, the method of this invention allows the drive module to recover in case of an array controller failure and to be removed from a list of devices like a regular drive.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The at least one daughter card and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard and the at least one daughter card is tested.

Abstract: An emulator schedules emulation threads for DMA emulation and other emulation functions in a time-multiplexed manner. Emulation threads are selected for execution according to a load balancing scheme. Non-DMA emulation threads are executed until their execution time period expires or they stall. DMA emulation thread execution is allowed to execute indefinitely until the DMA emulation thread stalls. The DMA emulation thread prefetches additional adjacent data in response to target computer system DMA requests. Upon receiving a target computer system DMA request, the DMA emulation thread first checks to the prefetched data to see if this data matches the request. If so, the request is fulfilled using the prefetched data. If the prefetched data does not match the target computer system DMA request, the DMA emulation thread fetches and stores the requested data and additional adjacent data for potential future use.

Abstract: The present invention is directed to a method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation. Addresses may be provided to multiplexers through configuration pins. The input ports of the multiplexers may be connected to interface pins of the pre-diffused IP blocks, and the output ports of the multiplexers may be connected to I/O pins which provide input and output to the semiconductor device. Through controlling the signals on the configuration pins and thus the outputs of multiplexers, any single pre-diffused IP blocks or any combination of the pre-diffused IP blocks in the semiconductor device may be exposed through corresponding I/O pins for prototyping.

Abstract: Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.

Abstract: A method supports secure input/output (I/O) communications between an I/O device and a data processing system via a keyboard, video, and mouse (KVM) switch. An example embodiment includes the operations of establishing a first secure communication channel between the KVM switch and the I/O device and establishing a second secure communication channel between the KVM switch and the data processing system. In addition, I/O data may be received at the KVM switch from the I/O device via the first secure communication channel. In response to receipt of the I/O data from the I/O device, the I/O data may be transmitted from the KVM switch to the data processing system via the second secure communication channel. Embodiments may also include support for non-secure channels between the KVM switch and non-secured I/O devices, non-secured data processing systems, or both.

Abstract: A system and method are disclosed for crossbar switching in an emulation environment. The switch is designed to coordinate scheduling between different crossbars in the system and to be dynamically reconfigurable during operation. In one aspect, a crossbar switch includes a switching matrix and an array of control cells. The control cells use a high-frequency clock to perform high-speed switching and a low-frequency clock in order to initiate a switching sequence. The low-frequency clock initiates the sequence at a time coordinated with other crossbars in the system to optimize scheduling. In another aspect, the control cells include a memory containing control bits for the switching matrix. The memory may be reconfigured without stopping traffic management through the crossbar switch. In yet another aspect, the high-frequency sequence may provide for the ability to loop.

Abstract: Accessing some storage-area networks (SANs) requires a client computer to include a special electronic component, known as a host bus adapter (HBA). However, the present inventor recognized that conventional host bus adapters add considerable expense to the cost of accessing the storage-area network. Accordingly, the present inventor devised a host bus adapter that is implemented in software and thus referred to as a “virtual” host bus adapter. One exemplary embodiment of the virtual host bus adapter includes a hardware-emulation module that makes the virtual host bus adapter appear to operating system environments as a conventional host bust adapter with dedicated hardware.

Abstract: A removable magnetic storage device uses an optical drive interface to appear to the operating system as an optical drive. Thus, a removable magnetic drive appears to the operating system as a large optical device similar to DVD/CD, and receives similar functionality. By appearing as an optical device, the removable magnetic storage device can use many features not currently available to magnetic storage devices, such as autorun, multiple volume sets, larger capacity, and efficient space allocation.

Abstract: A method and system of emulating serial com port communication. A computer processing system has computer-executable operating system instructions including first instructions that interact with a first serial device according to a predefined input/output (I/O) hardware interface. A first serial device has a receive port and a transmit port and has the predefined (I/O) hardware interface. A second serial device has a receive port and a transmit port. The transmit port of the first serial device is in serial communication with the receive port of the second serial device, and the receive port of the first serial device is in serial communication with the transmit port of the second serial device. Computer-executable instructions emulate serial communication port device communication and include instructions that transmit information over another medium in response to receive requests from the second serial device.

Abstract: According to one embodiment, a system is disclosed. The system includes one or more storage devices, a host bus adapter (HBA) and a bridging device coupled between the one or more storage device and the HBA. The bridging device includes a register having bits corresponding to each of the one or more storage devices. Each bit indicates whether staggered spin-up is enabled at a corresponding storage device.

Abstract: A method for monitoring and emulating privileged instructions of a program that is being executed at a privilege level in a virtual machine is disclosed. A privilege level associated with a received instruction is determined. The instruction privilege level is compared to the program execution privilege level. If the instruction privilege level is valid with respect to the program execution privilege level, the instruction is executed. If the instruction privilege level is invalid with respect to the program execution privilege level: the instruction result is emulated; the number of times the instruction has been received from the program is checked; and if the instruction has been received more than a specified number of times, the instruction is overwritten with one or more instructions with a valid privilege level with respect to the program execution privilege level.

Abstract: A multi-purpose interface between a host computer and an FPGA. This interface uses an IEEE 1284 compliant EPP mode connection. When the host computer is initialized, a reset of the FPGA is carried out to clear the configuration memory of the FPGA. The data lines of the interface are then used to communicate unidirectional configuration data into the FPGA. The data are clocked by the host computer using the data strobe signal line to clock data into the FPGA. When the FPGA has been fully programmed, including programming an IEEE 1284 compliant EPP mode interface into the FPGA, the data lines are used for bidirectional communication between the host computer and the configured FPGA, in this embodiment operating as a virtual microcontroller.

Abstract: An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported by an external recipient into a second predetermined command recognizable/supported by the external recipient. Such arrangement is further arranged to control a predetermined ordering of the converted second predetermined command with respect to other commands. The command translation/ordering unit may be arranged to control ordering such that all commands handled prior to the first predetermined command are completed prior to completion of the converted second predetermined command. Further, the command translation/ordering unit may be arranged to control ordering such that all commands handled after the first predetermined command are completed after completion of the converted second predetermined command.

Abstract: A modified universal asynchronous receiver transmitter (UART) device is provided with an auxiliary high speed parallel channel using supplementary FIFO buffers for the exchange of data. The auxiliary parallel channel is separate from the normal lower speed serial channel which is retained in unmodified form. The retained serial channel provides full compatibility with and support for the National Semiconductor 16550 standard, while the auxiliary parallel channel allows for rapid transfer of large data blocks, such as is needed for a PCMCIA wireless data card for example. The key advantages of this approach lie both in the data transfer speed and in the reduced amount of development time needed to implement a UART interface for communicating between a host computer and a new subsystem. This is because all the UART functions, except large volume data transfer, can be carried out over the standard serial channel using standard device drivers.

Abstract: Dynamic cosimulation is implemented using a cosimulation bridge for data exchange between a primary simulator and a secondary simulator, and a plurality of user selected optimization control signals defined over the cosimulation bridge. At least one user selected optimization control signal is identified for disabling the cosimulation bridge. The primary simulator and secondary simulator are dynamically disengaged for ending data exchange responsive to disabling the cosimulation bridge. Responsive to optimization control signal going inactive, the primary simulator and secondary simulator are dynamically re-engaged for data exchange. The optimization control signals include a single sided disable; a two independent disable; a functional OR disable; a functional AND disable, and suspend signals. The single sided disable and the two independent disable enable disabling one side of the cosimulation bridge and not the other side.

Abstract: The present invention is directed to a system and method for establishing communication between a flight simulator and a secondary control system, such as a Flight Management System (“FMS”). Information can be transmitted between the flight simulator and the secondary control system via a socket in a TCP/IP connection between the two systems. In the event that the secondary control system does not natively communicate in TCP/IP format, the information must be translated to and from the TCP/IP format. In this manner, an actual deliverable version of the secondary control system, possibly operating on can be used.

Abstract: A method and apparatus for managing the configuration of a computing arrangement having a host operating system and an emulator operating system includes establishing host operating system interfaces to computing arrangement components. The computing arrangement is scanned, using the host operating system interfaces, to determine configuration information about computing arrangement components reserved for use by the emulator operating system. At least a portion of the scanned configuration information is communicated to the emulator operating system.

Abstract: The various embodiments of the invention relate to analyzing operations of an emulated input-output processor. Instructions native to the first type of instruction processor are emulated on a second-type instruction processor. The instruction processor emulator executes an operating system that includes instructions native to the first type of instruction processor. The operating system includes instructions that write input/output (IO) requests to the memory arrangement in response to IO functions invoked by a program. An IOP emulator that is executable on the second-type processor emulates IOP processing of IO requests from the memory arrangement. The IOP emulator maintains in the memory arrangement a first set of data structures used in processing the IO requests. State data currently contained in the data structures is stored on a retentive storage device, and in response to user input controls, the state data is read from retentive storage and displayed.

Abstract: An interface to one or more hardware devices includes a configuration library and objects to model the hardware. Software programs using the interface need not understand how to communicate with the hardware. Instead, the software programs may communicate with the interface. In turn, the interface communicates with the hardware. The software may be written when the hardware implementation features are unknown.

Abstract: A general-purpose electronic device, a method of controlling the same, and an information processing system are provided. This electronic device has a function of automatically installing its driver in the information processing system. The driver is stored in the electronic device. The electronic device includes a first device and a second device in which the driver of the first device is stored. The first and second devices generate transactions on a common interface for external connection. The operation of the second device is started before the operation of the first device, and a means is employed to make the driver readable from the second device through the common interface.

Abstract: An improved interface between a host computer and a tape drive emulation system includes software interfaces for communicating control, configuration, and policy data and a hardware interface for providing redundancy and fan-out between the main controller and host channels.

Abstract: A resource board for a circuit emulator holds programmable logic devices (PLDs) and other emulation resources such as random access memories (RAMs) and employs both hard-wired and network-based virtual signal paths to flexibly route signals between the emulation resources on the resource board and resources mounted on other resource boards, workstations and other external equipment. The resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.

Abstract: Before using a netlist description of an integrated circuit as a basis for programming a circuit emulator, a clock analysis tool analyzes the netlist to identify synchronizing circuits including clocked devices (“clock sinks”) such a flip-flops, registers and latches for synchronizing communication between blocks of logic within the IC. The tool initially classifies the clock signal input to each clock sink according to its clock domain, sub-domain and phase. The tool then classifies each synchronizing circuit according to relationships between the classifications of the clock signals it employs to clock its input and output clock sinks. The tool then determines, based on the classification of each synchronizing circuit, whether the emulator can reliably emulate that synchronizing circuit, or whether the tool should automatically modify the netlist description of the synchronizing circuit so that the emulator can emulate it.

Abstract: A wiring harness design is analyzed and module data is created automatically and stored for a plurality of harness modules representing wire and component element requirements for those modules, the modules being capable of assembly in selected combinations to create a complete harness.

Abstract: The present invention discloses a method, system and article of manufacture for performing analytic modeling on a computer system by handling a plurality of predefined system criteria directed to a modeled computer system. The present invention provides means for the user of an analytic model to specify (i.e. enable) any number of predefined system criteria that must all be simultaneously satisfied. The modeling methodology uses a variation of the well-known Mean Value Analysis technique in its calculations. Response times, resource utilizations, and resource queue lengths are initially estimated for a small user arrival rate. An iterative method is used to gradually increase the user arrival rate by a constant value. For each iteration, response times, resource utilizations, and resource queue lengths are calculated. Then for all the criteria, which have been enabled, it is checked to see if the value limits specified for those criteria have exceeded.

Abstract: A system and method which allows complex tasks to be scheduled and/or coordinated on one or more computer systems by focusing the level of autonomy to each phase of a plan. The phases include computational components and may spawn target phases such that the phases are dependent on the target phases. The phases may begin execution upon completion of the target phases. Each phase may determine further execution, including succeeding phases, in an event-driven manner.

Abstract: A data storage system includes memory, a controller, and an Ethernet interface enabling sending and/or receiving Ethernet packets to or from a client system, according to a first protocol. The controller is coupled between the memory and the Ethernet interface and essentially carries out a translation function. Information packets from the client system are translated from a first protocol to a second protocol for use by the memory, and information from the memory is translated from the second protocol to the first protocol for use by the client system as Ethernet packets.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: A cable isolator is provided for automatically performing cable breaks for testing of host bus adapters. A workstation includes a host bus adapter, such as a Fibre Channel storage controller, to be tested. The host bus adapter is connected to one or more storage modules through the cable isolator. The cable isolator includes two transceivers, one of which is connected to the host bus adapter and the other being connected to the storage modules. The two transceivers are also connected to each other internally. The cable isolator also includes a programmable logic device or controller that is used to enable and disable the two transceivers at set intervals. The one or more output disable signals are then provided to the transceivers to perform the cable break. The cable isolator may be an expansion card installed within the workstation. Thus, the workstation may communicate with the cable isolator through an expansion bus.

Abstract: The present invention employs a generative approach for configuring systems such that a system may be configured based on component or resource requests, or input in the form of need. The present invention provides a constraint-based configuration system using a structural model hierarchy. The structural aspects of the model provide the ability to define a model element as being contained in, or by, another model element. In addition, the structural model provides the ability to identify logical datatype and physical interconnections between elements and establish connections between elements. To configure a system, the present invention accepts input in the form of requests (e.g., component or resource) or needs, such as an expression of a need for a desktop computer system to be used in a CAD (i.e., computer-aided design) environment.

Abstract: A method for verifying the design of a disk controller circuit to be incorporated into a targeted hard disk drive system having a read/write channel and a head actuator may include steps of emulating reading and writing of data in the read/write channel based upon a model of the read/write channel, emulating a behavior of the head actuator during track seek and track following operations based upon an electromechanical model of the head actuator, providing a disk controller design base for defining integrated circuit elements comprising the disk controller circuit and providing a controller environment to support execution and debug of firmware for operating the disk controller circuit. A plurality of disk functions may be carried out at a time-scaled rate according to a script. The plurality of disk functions includes interaction of at least the read/write model, the electromechanical model, the disk controller design base and the controller environment.

Abstract: A communication device for a target integrated circuit chip having a digital processor, an on-chip emulator for controlling the digital processor and for collecting operation data from the digital processor for communicating to off-chip circuitry, and a target on-chip universal serial bus interface connected to the on-chip emulator, the communication device including an Ethernet port, an universal serial bus port and a further integrated circuit chip having on-chip universal serial bus interface, the on-chip Ethernet interface being connected to the Ethernet port, the interfaces being connected to the processing circuitry for translating between Ethernet protocol data on an Ethernet bus connected to the Ethernet port and universal serial bus data for the target on-chip universal serial bus interface.