Abstract: This invention is a system for remotely loading and remotely maintaining an electronic card (5) belonging to automation equipment and comprising a minimum of a processing unit (31), an internal bus (30) and a resources controller (10) which has one or more JTAG interface registers (42, 43) accessible for reading/writing by a JTAG server (50) that is external to the automation equipment. The resources controller (10) contains a status engine (11) capable of interpreting and carrying out instructions stored in one or more of the JTAG interface registers (43) and able to use the resources (21a, 21b, 21i) managed by the resources controller (10) and shared with the processing unit (31), without the intervention of the processing unit (31).

Abstract: A method for controlling I/O in a multi-processor environment, comprising the steps of: determining if an I/O instruction requiring an interrupt is being executed by one of the processors in the multi-processor environment to transfer data or a command between the processor and an I/O device; performing an interrupt if such an I/O instruction is detected; determining which of the processors in the multi-processor environment is executing an I/O instruction; if only one of the processors is executing an I/O instruction, setting a Last Processor indicator designating that one processor as the processor executing the I/O instruction; and transferring data or a command between the processor designated in the Last Processor indicator and the I/O device in response to the I/O instruction.

Abstract: A method and apparatus for transferring information between first and second devices, where the first device includes a tape drive having a tape drive head. A tape head interface is removably positionable adjacent the tape drive head to communicate with the tape drive head, and a communications interface communicates signals between the tape head interface and the second device. A tape emulator in communication with the tape head interface emulates a tape in the tape drive.

Abstract: The application discloses a system and method for providing a compact and high speed mechanism for emulating an ASIC or other chip operating within a large computing system environment for diagnostic purposes. A two step process is disclosed for generating data patterns for fully exercising a chip and to then transmit these data patterns at a high frequency to a system under test. In phase one, a pattern generator preferably transmits test pattern data at a first frequency to a memory storage device. In phase two, the memory storage device is enabled to transmit the stored test pattern data at a high frequency to a system under test. Buffering the test pattern data in this manner enables the inventive system to bypass the data transmission speed limitation of the pattern generator while still employing the test patterns created by the pattern generator and to thereby test the system under test under high speed operating conditions.

Abstract: The present invention provides a processor device and technique having the capability of providing a two-processor solution with only one processor. In accordance with the principles of the present invention, a host processor is programmed in its native source and machine code language, and an emulated second processor is programmed in a different native source or machine code language particular to that emulated processor, to allow programming specialists in the different processors to develop common code for use on the same host processor. A multitasking operating system is included to allow time sharing operation between instructions from program code relating to the host processor (e.g., a DSP in the disclosed embodiment), and different program code relating to the emulated processor. The program code relating to the host processor (e.g., DSP) is written in program code which is native to the DSP, while the program code relating to the emulated processor (e.g.

Abstract: A hardware emulation controller permits a high performance processor to be used with system circuitry that is configured for operation with a different processor. The hardware emulation controller is capable of modifying signals from the high performance processor for compatibility with the system circuitry. The hardware emulation controller is also capable of modifying signals from the system circuitry for compatibility with the high performance processor.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.

Abstract: The present invention is used to verify an equivalence between a software for realizing a predetermined function and a hardware data created according to the software and constituting a hardware operating identically as a processing by the software. The LSI verification method of the present invention simulates each of the hardware data and the software and compares, according to a signal I/O condition defining operation of the hardware, an I/O signal state as a simulation result by the hardware data to a software variable as a simulation result of the software for verification of the equivalent.

Abstract: An improved interface between a host computer and a tape drive emulation system includes software interfaces for communicating control, configuration, and policy data and a hardware interface for providing redundancy and fan-out between the main controller and host channels.

Abstract: A memory controller emulator for controlling memory devices in a memory system includes a counter for generating a plurality of address values. A plurality of storage devices for storing memory address information, memory data to be stored in the memory devices, and memory commands for controlling operation of the memory devices, are coupled to the counter. Each of the plurality of storage devices is configured to output data stored therein based upon address values received from the counter.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: Disclosed is a method and apparatus for emulating a fiber channel port. A controller is provided according to the invention that includes a fabric port and a virtual N port. The controller is adapted to buffer incoming data and convert an N port address provided with the data by a host computer to an instruction to the picker to couple the disk drive corresponding to the requested N port address to the virtual N port.

Abstract: Serializing and deserializing circuits are provided on an emulator circuit board to group input and output signals of programmable logic devices for routing through a cross point switch. In one instance, the input and output signals of the programmable logic devices are time-multiplexed signals of virtual interconnections. The cross point switch can be configured for static or dynamically scheduled operations.

Abstract: A flash memory controller translates between manufacturer-specific protocols to allow the flash memories of one manufacturer to be used transparently in a host system programmed for the memory devices of different manufacturer. According to the invention, the controller indicates the manufacturer's ID code the host system requires irrespective of the flash memories used. The scheme employed permits translation even when there is no one-to-one correspondence between the parts of the different protocols being used.

Abstract: A programmable state machine comprising a program memory and a processor is disclosed wherein the state machine operates with the processor accessing the program memory one or fewer times per state transition and wherein the data stored within the programmable memory is substantially optimized to support reduced memory requirements over those necessary according to the prior art. This is achieved by storing data as tables having a number of elements wherein some tables of data occupy less memory than other tables of data.

Abstract: A hardware-based logic emulator uses routing chips to implement a virtual full-crossbar interconnect. Logic gates and some internal interconnection of the emulated design are programmed into field-programmable gate array (FPGA) logic chips. External interconnection of the logic chips is provided by routing chips. When the routing chips are also FPGA chips with a same number of I/O pins, the number of routing chips can be 1.5 times the number of logic chips. For L logic chips, the first L routing chips are column routing chips. The column routing chips connect to the same pin or pins of all the logic chips and make connections within a single column of a routing table. The other L2 routing chips are diagonal routing chips that connect to different pins on different logic chips. The diagonal routing chips make connections among logic chips along diagonals in the routing table.

Abstract: There is disclosed a telephone exchange emulator for POTS and ISDN telephone lines comprising, a main unit including at least one of at least one Plain Old Telephone Service (POTS) line card or at least one Integrated Services Digital Network (ISDN) line card, and at least one V5.1 interface card, each of one of the at least one POTS or the at least one ISDN line card, and the at least one V5.1 interface card in communication with ports. These ports are adapted for receiving signals from communication devices, including for example, POTS and ISDN telephones. There is also a switch simulator in communication with the at least one V5.1 interface card. There is also a controller, typically a workstation with network management software for managing (controlling) the main unit and switch simulator. A method for emulating a telephone exchange is also disclosed.

Abstract: The present invention is directed to an analysis tool for aiding in the design of a process control system which conforms to a standard protocol. Such a tool advantageously allows the efficient design of a process control system while ensuring that the physical characteristics of the system conform to the standard.

Abstract: In a computer system executing a repository program and having a memory, a method is disclosed for identifying UML objects in the repository with objects in an XML file. The method includes the steps of parsing the XML file into XML objects and building an object tree. Next, the object tree is traversed a first time, and for each XML object found that has a name, corresponding UML objects are identified. After this, the object tree is traversed a second time, and for each XML object found that does not have a name, corresponding UML objects are then identified through Compositions and References. The method for traversing said object tree a first time includes the steps of identifying a UML object type for each XML object, and when the XML object name matches the UML object name at the current level, a UML and XML object IDs are saved in a ‘Conversion’ object in the memory.

Abstract: A method and system for converting the output of a communications port (e.g., a serial port or a USB port) into video signals representing the output of a terminal using a KVM switch. Upon receiving characters from the communications port, the system interprets the characters as terminal emulation commands and internally generates a representation of what a resulting terminal screen would look like. From that internal (digital) representation, the system produces analog outputS representing the terminal screen. The analog outputs are output on the monitor attached to the KVM switch.

Abstract: A method and system are provided for use in administering a complex system, such as a distributed computing ensemble. A model of the system being administered is prepared, preferably during runtime of the invention, by a combination of autodiscovery processes and manual input of information as needed. The model represents not only the resources found in the administered system, but also the service-relationships among those resources. The system administrator also can define elements in the model corresponding to arbitrary groupings of already-existing parts of the model. Software agents, which can be reconfigured, started and terminated as desired during runtime, report changes in state of the managed resources to the model, which updates itself and explores portions of the model adjacent (in terms of the service relationships) to the affected resource(s).

Abstract: A system and method are disclosed in which multiple components make demands on a common resource, such as a common memory. When it is desirable to change certain operating parameters of a component, an algorithm is performed which determines whether the common resource can support the new operating parameters. The algorithm first determines the worst case operating environment and then evaluates whether the common resource can support the worst case situation.

Abstract: A recording and reproducing device of the invention comprises a first connector having a plurality of contacts and gate circuits for receiving signals from a computer body. The first connector is connected to the computer body and also to a second connector having a plurality of contacts. The second connector has first contacts grounded on the computer body side and a second contact to which a signal from the computer body is not supplied. The first connector has third contacts connected to the gate circuits and a fourth contact which is connected to the second contact in a first connecting state and is connected to the first contact in a second connecting state. The fourth contact is connected to the control terminals of the gate circuits.

Abstract: A method of checking a parallel port of a personal computer using loopback includes the steps of loopback-connecting pins corresponding to control signals and data signals transmitted to a printer to pins corresponding to status signals transmitted to the computer, checking whether there is a parallel port, stopping the checking when there is no parallel port, generating the control signals and reading looped-back status signals after a predetermined time to check control pins, and generating the data signals and reading looped-back status signals after a predetermined time to check data pins. Accordingly, a parallel port of a personal computer is tested without being connected to a printer, thereby simplifying the a production process. Also, manual printing is not required, thereby reducing test time and production time.

Abstract: In an arcade system (20), an interface circuit (38) is configured for communication with a PC (40) and one or more peripheral devices (59). The interface circuit (38) adapts a PC-based application (64), installed on and executable from the PC (40), to an automated format in order to include arcade-style features, such as video and audio cues, fee prompts, timing cues, and so forth. The interface circuit (38) includes a processor (66) in communication with a plurality of inputs and outputs on the interface circuit (38). A memory (68) is coupled to the processor (66) and includes a user-configurable control program (74) executable on the processor (66). The user-configurable control program (74) selectively translates the data received from the peripheral devices (59) to a data format that is recognized by the PC-based application (64) and selectively enables the transfer of the data from the peripheral devices (59) to the PC (40).

Abstract: A reception/transmission circuit 20 receives and transmits data from and to a keyboard 16 and mouse 18. An output buffer 42 temporarily stores data from the keyboard 16 and mouse 18 while an input buffer 44 temporarily stores data from BIOS 100 and an interrupt handler 110. A status register 46 stores status data, and port registers 48 and 50 transmit a given data to an external means. An interrupt generating circuit 60 generates SMI# for CPU 10. An emulation handler 120 is activated by SMI# for executing a given emulation. Instead of the reception/transmission circuit 20, a USB controller or IEEE1394 controller may be provided. It is desirable that the system emulates processing of a processor in the 8042 or keyboard.

Abstract: Embodiments of the invention can be used to assess whether a software application is compatible with an operating platform. A specification that describes the operating platform is generated using a definitional language. The specification identifies the programming resources of an operating platform. The application's dependencies and programming resources are identified. A compatibility engine is executed to resolve an application's dependencies to the specification. The output of the compatibility engine identifies whether the application conforms to the operating platform and how it deviates from the specification.

Abstract: In verifying a logic operation of an information processing apparatus, an I/O emulator and a test program are operated in cooperation with each other and input data to the I/O emulator is automatically generated to generate more transaction conflict patterns and realize verification of the logic operation at a high precision.

Abstract: Interface apparatus for connection between a data handling device and a data communication medium to enable data to be transferred between the device and the medium, is constituted, inter alia, by a data alignment device (7, 8) coupled in use to the data handling device. A memory (5, 6) is coupled for data transfer to the data alignment device (7, 8) and includes a number of substantially identical subsidiary, First-In-First-Out (FIFO) memories arranged in parallel. The number of subsidiary memories is chosen such that their overall width is at least equal to the longest length of data to be transferred between the memory (5, 6) and the alignment device (7, 8) in a single transfer step and the width of each subsidiary memory is equal to the shortest length of data to be transferred between the memory and the alignment device in a single transfer step.

Abstract: A system and method in accordance with the present invention provides for an embedded CPU system which is upgradeable through the use of an external CPU which can be utilized therewith. In a first aspect, the embedded CPU system includes a CPU and a plurality of devices which are accessible by the CPU, via a device control register bus. The embedded CPU system includes logic coupled to the device control register bus for allowing access to the devices within the embedded CPU system by an external CPU. In a preferred embodiment the present invention provides a highly integrated set top box controller with a processor performance that services the low-end with the added advantage of additional performance with the EMCPU operating as an I/O assist processor to the EXCPU. When the EXCPU operates as the primary processor these two processors serve as a high end set top box controller.

Abstract: A method and an apparatus for simulation of data in a computing system environment having a controlling program, a main memory, a plurality of hosts, at least one adapter and a queued-direct input/output device using a queued-direct input/output protocol. A pageable virtual machine is provided under control of a virtual-machine hypervisor in processing communication with one or more hosts. Simulation is then provided by strictly separating a set of protocol control blocks between those that contain main-memory addresses and those that do not. Copies of those control blocks that contain main-memory addresses is created and their addresses converted by the hypervisor from addresses used by the program in its virtual machine to real-memory addresses usable by the adapter.

Abstract: Disclosed is a system for mapping objects defined in a design model, such as an object oriented design model defined using a design language such as the Universal Modeling Language (UML), to a data model accessible to an application development tool. A design model is provided that includes at least two models. A first model includes a first class and a second model includes a second class. The first class and second class have the same name, and the first class and second class have at least one different attribute and method. The first model, the first class, and attributes and methods therein are mapped to a first data structure that indicates that the first class is included with the first model. The second model, the second class, and attributes and methods therein are mapped to a second data structure that indicates that the second class is included with the second model. In this way, the first class and the second class are distinguished according to their model in the data structures.

Abstract: By means of a user interface the application programs which are accessible through said user interface are visually represented on the display of a computer as icons (IC; P1, P2, P3, P4). It is proposed to assign an identification (DF1, DF2; DF3, . . . , DF8) to such an icon (IC; P1, P2, P3, P4) indicating which data format can be processed by the application program represented by the icon. In a simple and concise manner this identification allows compatibility with another application program which is accessible through the user interface to be determined.

Abstract: A remote terminal emulator (RTE) is provided in which substantially all of the time elapsing during an emulated use of a computer system under test is categorized and reported. The time required by the computer system under test to respond to command signals transmitted by the RTE is recorded as a receive time and is measured from completion of the transmission of the command signals to recognition of a pattern specified by the RTE as signifying completion of the response by the computer system under test. As a result, the receive time recorded reflects the time required by the computer system under test to (a) process and carry out the command transmitted by the RTE and (b) transmit response data back to the RTE.

Abstract: A method and system for indexing adapters within a data processing system where the data processing system contains multiple existing adapters, where each of the multiple existing adapters is identified by particular indexing data. All adapters within the data processing system are scanned. A determination of whether or not any additional adapters have been added to the data processing system in addition to the multiple existing adapters is made. Particular indexing data is assigned to any additional adapters in response to determining that additional adapters have been added to the data processing system, where any additional adapters added to the data processing system are indexed into the data processing system without changing the particular indexing data of each of the multiple existing adapters.

Abstract: The inventive mechanism synthesizes complex software data structures in hardware by using memory transaction translation techniques. The mechanism includes a finite state machine and a bus controller. The state machine has a specific algorithm that defines the dynamic behavior of the synthesized structure. The bus controller manipulates memory control strobes and communicates to the memory bus and bridge. When a transaction references the data structure, the inventive mechanism processes the address of the request into a new address based upon the state of the structure. The finite state machine tracks the current state of the structure and calculates the new state or address. The mechanism the sends out the new address, which is processed by the memory device. The inventive mechanism can also manipulate the read and write aspects to transactions, in addition to the address aspects of the original transaction.

Abstract: A method and apparatus for coupling multiple computer peripherals to a computer system through a single I/O port is disclosed. The inventive apparatus includes an interface device having a first connector for coupling to the I/O interface of a computer system, a second connector for coupling a first computer peripheral to the I/O port and a third connector for coupling a second computer peripheral to the I/O port so that both peripherals are simultaneously coupled to the I/O port. Within the housing of the preferred embodiment of the interface device, control and data lines for receiving data associated with the I/O interface are coupled from the first connector to the third connector and control and data lines for transmitting data associated with the I/O interface are coupled from the first connector to the second connector. By separating the transmit and data functions of the I/O interface so they may be routed to separate connectors, computer peripherals of difference types, i.e.

Abstract: In a cache memory of a super-scalar or VLIW processor to concurrently process a plurality of memory accesses, to provide a memory capable of multi-port access operation, there is provided a unit which subdivides the cache memory into a plurality of memory banks for concurrent operations thereof and which allocates memory ports independently to the respective memory banks. In a first cycle, the first and second memory ports are allocated to the first and second memory banks, respectively. If a hit occurs, the plural accesses are completed in one cycle. If a miss results, the first and second memory ports are allocated respectively to the second and first memory banks in a second cycle.

Abstract: A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses is disclosed. The verification engine comprises a first hardware model and a second hardware model, both configured as a component and having a set of hardware model input/output pins. In addition, a first bus wrapper is connected to the first hardware model and a second bus wrapper is connected to the second hardware model. Further, a set of bus lines are each connected to the first bus wrapper and the second bus wrapper. Each bus wrapper also has switchable communicative circuitry that switchably communicatively connects each hardware model input/output pin to a bus line and has a control block controlling the switchable communicative circuitry. A system controller is connected to at least some of the bus lines and is adapted to transmit a sequence of time synchronization information to each bus wrapper control block by way of the bus lines.

Abstract: A software development supporting system of the ROM emulation type is provided, which facilitates the electrical connection to a target system equipped with no ROM socket. This system is comprised of a ROM controller electrically connectable to a PCI bus of a target system, a ROM emulator for emulating an operation of a target ROM mounted on the target system, and a host computer electrical connected to the ROM emulator. The ROM controller receives a control signal for controlling the target ROM, in which the control signal is transmitted through the PCI bus of the target system. The ROM controller transfers the received control signal to the ROM emulator, thereby controlling the ROM emulator. Preferably, the ROM controller is designed to output an access assertion signal to the PCI bus before a ROM controller of the target system outputs an access assertion signal of the target ROM. Thus, the ROM emulator serves to emulate the target ROM using the control signal.

Abstract: An improved hybrid flow control protocol for providing FIFO capacity to prevent overflow due to bytes arriving after the FIFO indicates it is not ready to receive any more bytes utilizes a combination of a high/low watermark and credit based system. In one embodiment, when the byte count exceed the high watermark fixed credits are sent when N bytes are pulled from the FIFO. In a second embodiment, variable credits are sent depending on the difference between the number of bytes received in and pulled from the FIFO.

Abstract: An improved maintenance system and interface for use in a large-scale data processing system is provided. Within the data processing system, logic is partitioned into multiple logical groups. Each of the groups is associated with a bi-directional port, and each group may be intercoupled to other groups via the associated port. Within each of the groups, an internal condition detection circuit selectively monitors selected logic circuits to detect the presence of certain predetermined conditions or events. When an internal condition is detected, a notification is provided to the bi-directional port and broadcast over the interface to all other logic groups simultaneously. Each logic group further includes an external condition detection circuit interconnected to the respective bi-directional port whereby condition indicators are received from other logic groups as an external condition indicator.

Abstract: An E2PROM controller is provided for an emulation chip. An E2PROM is connected to a CPU via a memory interconnect bus. The E2PROM and the CPU are also connected to each other via a peripheral circuit interconnect bus independent of the memory interconnect bus. During emulation, the emulation chip is connected to an in-circuit emulator via an emulator interconnect bus, and the memory interconnect bus is disconnected. However, the E2PROM controller allows electrical communication through the peripheral circuit interconnect bus and thereby accesses the E2PROM as one of peripheral circuits. Accordingly, it is possible to check out whether or not a reprogramming program stored in the E2PROM is running normally.

Abstract: DOS application programs are accommodated when using a controllerless modem by providing a virtual device driver. The virtual device driver emulates UART to UART communications and handles interrupts by the DOS applications and by a hardware port managed by the controllerless modem. In one implementation, the virtual device driver shares a communications interface in common with 32-bit applications. In a communication system environment, DOS applications can participate in modem to modem communications with remote DTEs and with other devices using the services of the virtual device driver.

Abstract: A multiple use chip socket supporting more than one type of permanent storage chip in a single chip socket is disclosed. The multiple use chip socket provides a plurality of address bit lines which are used to specify an address of a particular location within a memory device installed in the socket. In general, the number of address bit lines directly coupled to the socket correspond to the number of address bit lines required for the smallest memory device to be installed in the socket. Additional address bit lines are coupled to control logic of the present invention. The control logic selectively applies addressing signals to the chip socket depending on the type of memory device inserted in the socket. As part of the initialization process, the processing logic of the present invention first determines if an access to a device installed in the chip socket is required by a circuit board as part of its initialization or boot process.

Abstract: A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased.

Abstract: The microcontroller accesses a battery of hidden registers used essentially in the field of emulation. The fact that there is a large number of hidden registers means that it is not possible to assign them an address by which they can be accessed directly. Since this battery of hidden registers has to be accessible by a host circuit and by a microprocessor, recourse is had to a method of indirect addressing by means of two peripheral control registers. A priority signal obliges the microprocessor to wait for the read and write resources to be released by the host circuit to perform these instructions.

Abstract: The invention provides an inspection adapter board for printed board, which has inspection electrodes of a pitch wider than electrodes to be inspected, permits carrying out the necessary inspection for a printed board by a tester having a small capacity, and can be designed and fabricated with ease, and a method for inspecting the printed board by an inspection adapter board. The invention also provides a method and apparatus for producing information for fabricating such an inspection adapter board. The inspection adapter board is equipped with inspection electrodes corresponding to the electrodes to be inspected. At least one of the inspection electrodes is a common inspection electrode commonly corresponding to two or more electrodes to be inspected. The common inspection electrode is formed in a state that wiring networks do not form a closed circuit.

Abstract: In a computer system having a plurality of peripheral devices, a data transfer system for implementing transparent direct communication between the devices and the computer system. The system of the present invention includes a switch having a plurality of ports. Each of the plurality of ports is adapted to couple to a respective one of a plurality of devices. Each of the plurality of ports is further adapted to accept data from its respective device and transmit data to its respective device in a bi-directional manner.