Abstract: A cable isolator is provided for automatically performing cable breaks for testing of host bus adapters. A workstation includes a host bus adapter, such as a Fibre Channel storage controller, to be tested. The host bus adapter is connected to one or more storage modules through the cable isolator. The cable isolator includes two transceivers, one of which is connected to the host bus adapter and the other being connected to the storage modules. The two transceivers are also connected to each other internally. The cable isolator also includes a programmable logic device or controller that is used to enable and disable the two transceivers at set intervals. When the cable connection is to be broken, the programmable logic device generates one or more output disable signals. The one or more output disable signals are then provided to the transceivers to perform the cable break. An on-time and an off-time may be set using switches or dials.

Abstract: A power management device of electronic card includes a functional module, an interface bus, a bus bridge unit, a power storage unit, an external power input unit and a power control unit. The power control unit controls the bus bridge unit, the external power input unit, and the power storage unit, so as to supply the interface power from the bus interface unit to the functional module and further charge the power storage unit, directly supply the interface power from the bus interface unit to the power storage unit for charging the same, supply the external power from the external power input unit to the functional module and further charge the power storage unit, or directly supply the external power from the external power input unit to the power storage unit for charging the same.

Abstract: A read-write hard disk drive is emulated using a hard disk drive image file on a protected medium such as a CD-ROM, a written disk sector database, and file system filters. A file system filter intercepts file I/O requests from the operating system. Initial read requests are serviced from the hard disk drive image file. Write operations are directed to a database, such as in RAM. Subsequent read requests for previously written data are serviced from the database. Another file system filter monitors attempts to alter the file access attributes, and prevents pre-existing read-only files on the emulated drive from being written or deleted. The maximum size of the written disk sector database is the sum of sectors on the hard disk drive image file allocated to read-write files and free space. The emulated read-write hard disk drive allows for the execution of programs requiring a read-write native media.

Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE Standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Abstract: A method in a data processing system for a program to communicate across a firewall with a host. A browser is simulated by the program in the data processing system, wherein the browser being simulated is able to communicate through the firewall. The program communicates with the host directly using the simulation instead of using the browser.

Abstract: A bridge board connects a TMS470 processor evaluation module and a TMS320C54XX processor evaluation module. The bridge board performs translation of signal formats on both of the boards and also synchronizes the signal formats on both boards so that both boards are able to operate together. With this bridge board, and its specific connections to both of the evaluation modules, a single workstation, preferably connected to the TMS470 module is able to not only control the TMS470 module but also the TMS320 module. Software for the TMS320 can be loaded from the workstation through the TMS470 module, through the bridge board and into the TMS320 module. The software in both of the evaluation modules can then operate and interact with each other through the bridge board.

Abstract: There is disclosed a method of communicating with an integrated circuit chip having plural components thereon, the components including digital processing circuitry and an on-chip emulator connected to the digital processing circuitry for initiating command and control sequences for the digital processing circuitry in response to externally applied signals or in response to detected states of the digital processing circuitry.

Abstract: Disclosed is a method and apparatus for emulating a fiber channel port. A controller is provided according to the invention that includes a fabric port and a virtual N port. The controller is adapted to buffer incoming data and convert an N port address provided with the data by a host computer to an instruction to the picker to couple the disk drive corresponding to the requested N port address to the virtual N port.

Abstract: A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.

Abstract: Connectivity between an emulation controller and a plurality of target devices can be automatically detected. After the target devices (Chip1, ChipN) and the emulation controller (12) tri-state respective terminals thereof, one of the target devices drives a predetermined logic level on each of the aforementioned terminals thereof in sequence, while maintaining the remainder of the aforementioned terminals thereof tri-stated. These driving (33) and maintaining (31) operations are thereafter performed by each of the remaining target devices in sequence. During each driving step, all of the target devices and the emulation controller read logic levels at their aforementioned terminals (34, 43).

Abstract: Apparatus and method for remote administration of a PC-server and which enables remote keyboard input, even during re-boot sequence of the PC-server. The apparatus comprises an adapter emulating video of a display adapter to convert display data, including boot-level data at the console, for serial transmission to a remote user. Further, the microprocessor converts input commands from the user to a form compatible with the PC-server input interface such as scan codes for a keyboard input interface. Additionally, the method and apparatus of the present invention makes it possible to route textual data to a speech synthesizer at the boot level.

Abstract: The present invention relates to a system and method for emulating a greater range of behavior of a peripheral device connected to a host device or host computer than was available in the prior art. The emulation of a greater range of activity of the peripheral device provides an opportunity to more fully test the interaction of a host device with the emulated peripheral device. More specifically, the present invention preferably adds control data line and power data line connections to user data line connections between the host device and an intelligent emulator so that variations in control settings and power levels may be exercised in addition to manipulation of transmissions along a user data line, thereby more fully exercising host device interaction with an emulated device.

Abstract: An debug and emulation system includes a target device embodied in a single integrated circuit. The target device includes a function clock circuit and an operation circuit operating in synchronism with the function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. The trace data is sensed in synchronism with the oscillator clock. The emulator is coupled to the target device to control the clock selection.

Abstract: A system and a method for providing an emulated network including a plurality of emulated networking devices, in which a number of network node executable images are employed. Each of the network node executable images corresponds to one of the emulated networking devices. The emulated networking devices represent physical networking devices, such as optical switches. A portion of each of the network node executable images is operable to execute without modification on a physical networking device.

Abstract: A micro-controller is connected to an external circuit via an address bus and a read control signal line. The external circuit includes an enable circuit, a decoder and a register group. The enable circuit produces an enable signal from the sixteenth bit of 16-bit information on the address bus and a control signal on the read control signal line. The decoder creates an address from the ninth to fifteenth bits of the 16-bit information. When the enable signal is valid, the register group writes a signal value of the first to eighth bits of the 16-bit information into a register specified by the address. Accordingly, the micro-controller can send the read control signal, the register address and the register data to the external circuit via the address bus. It is therefore possible to write data into the external circuit without using a write control signal line.

Abstract: An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path.

Abstract: The present invention is directed to a method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation. Addresses may be provided to multiplexers through configuration pins. The input ports of the multiplexers may be connected to interface pins of the pre-diffused IP blocks, and the output ports of the multiplexers may be connected to I/O pins which provide input and output to the semiconductor device. Through controlling the signals on the configuration pins and thus the outputs of multiplexers, any single pre-diffused IP blocks or any combination of the pre-diffused IP blocks in the semiconductor device may be exposed through corresponding I/O pins for prototyping.

Abstract: Emulation communications via a test access port and boundary-scan architecture providing serial access to a serial connection of a plurality of registers disposed in a plurality of modules. One of the modules is selected for communication. Nonselected modules are made nonresponsive to data on the serial connection. The external emulation hardware supplies a serial signal having a first logic state for a number of cycles greater in number than a number of bits of the serial connection of registers to the test access port. The emulation hardware supplies a start bit having an opposite logic state. The selected module detects the start bit and stores the next predetermined number of data bits. These bits could be data bits to be stored in a program visible data register or bits interpreted as an instruction for execution by the module. The selected module may transmit return communications via the serial scan path using the same format.

Abstract: An emulator block (30) for use in the development or testing of an embedded system, the emulator block (30) being configured to model a processing block (20) that includes a bus interface (22) and processing core logic (28), said emulator block comprising: an emulator bus interface comprising bus specific logic (24) and a Register Block (26), said emulator bus interface being configured to be substantially identical to the bus interface of the processing block that the emulator block is to model; and a core block emulator (32) configured, in use, to supply and receive signals to and from the Register Block (26) which mimic signals supplied and received to and from the processing core logic (28) of the processing block that the emulator block is to model.

Abstract: A novel reconfigurable logic element (RLE) architecture for use in an integrated circuit itself used in an emulation system is disclosed. The RLE has lookup table logic circuitry for implementing a function. In addition, the RLE contains multi-stage coupling logic circuitry correspondingly coupling RLE inputs to the inputs of the lookup table logic circuitry. This allows global routing of the emulation system by circuit design mapping software to be much more flexible, as the routing may be configured independently of those four input constraints due to the ability to reassign the inputs with the swapper.

Abstract: Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis.

Abstract: A RAID storage device controller provides a host interface for interfacing the controller to a host system bus. The host interface is isolated from the attached storage devices, for example IDE disk drives, so that the actual attached drives are not limited in number or interface protocol. Various device ports can be implemented, and various RAID strategies, e.g., level 3 and level 5, can be used. In all the cases, the host interface provides a standard, uniform interface to the host, namely an ATA interface, and preferably a dual channel ATA interface. The host interface emulates the ATA single or dual channel interface and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to the controller. Thus, for example, five or seven IDE drives can be deployed in RAID level 5 protocol without changing the standard BIOS in a PCI host machine. Thus the RAID controller is transparent relative to a standard dual channel ATA controller board.

Abstract: A component, system and method for simulation of a PCI device's memory-mapped I/O register(s) are provided. The PCI simulation component has an initialization component, a configuration space simulator and a memory-mapped I/O space simulator. The initialization component can claim an amount of memory by modifying the amount of memory that an operating system has available to it. The initialization component further identifies to the operating system that at least some of the claimed memory resides on a PCI bus. The configuration space simulator causes the operating system to accept that the simulated PCI device is present in the system.

Abstract: Methods and systems for increasing the speed with which configuration data can be loaded and tested on a reconfigurable interconnect device are disclosed. A reconfigurable interconnect integrated circuit (IC), or a reconfigurable portion of an integrated circuit, is coupled to a digital storage circuit such as a shift register. A seed configuration pattern is loaded once into the digital storage circuit, which is loaded onto a first set of switches in the integrated circuit. The shift register shifts the configuration patterns by a predetermined amount, and then loads the shifted configuration pattern onto a second set of switches in the integrated circuit. Using the digital storage circuit coupled to the reconfigurable interconnect, each integrated circuit only needs to load a configuration pattern once, instead of reloading a new configuration pattern for each set of switches in the integrated circuit.

Abstract: A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.

Abstract: A system and method for predicting timing of future service events of a product. A database contains a plurality of service information and performance information for the product. A statistical analyzer analyzes the plurality of processed service information to determine a plurality of compartment failure information. A performance deterioration rate analyzer analyzes the performance deterioration rate of the product from the plurality of service information and performance information. A simulator, simulates a distribution of future service events of the product according to the plurality of compartment failure information and the performance deterioration rate analysis.

Abstract: A method of and apparatus for efficiently and effectively coupling a newly designed peripheral device to a legacy data processing system. The approach utilizes emulation of a SCSI tape device by a SCSI DVD device. Through device emulation, system-wide modifications are minimized.

Abstract: A computer system implements a standard modem without the use of a microcontroller. Instead, a digital signal processor is provided on an expansion card, but with direct links to the computer system itself. The code usually implemented in the microcontroller is instead implemented as a virtual modem controller to be called by the operating system of the computer itself. Further, this virtual modem controller includes a virtualized UART, that appears to the operating system software as a hardware UART, with entry points for calls to replace input/output instructions. In this way, standard device driver code written to execute input/output operations is easily converted to operate with the “virtualized” UART.

Abstract: A system is described including a disk-based data cartridge that contains a plurality of disk drives, and that physically conforms to industry standard dimensions for magnetic data tape cartridges. A tape drive emulator receives the disk-based data cartridge and stores data within the plurality of disk drives in accordance with a format that emulates a tape storage format. A controller within the tape drive emulator utilizes RAID techniques to store data on the plurality of disk drives, thereby achieving increased performance, fault tolerance, or combinations thereof. A host computing device communicates the data to the tape drive emulator via a tape drive communication protocol. An automation unit selectively retrieves the disk-based data cartridge from a data tape cartridge library and engages the disk-based data cartridge with the tape drive emulator.

Abstract: Where instruction data to enable a stop control is stored in an operation setting register that is provided in a peripheral module in an evaluation chip, a stop control circuit of the peripheral module stops the progress of an operation of a functional circuit until a CPU completes processing of a monitor program that is performed in response to a break interrupt request. None of the operation setting register, the stop control circuit, and an interface circuit are reset by a reset signal supplied from a circuit board as a target system. The CPU directly starts execution of a user program without starting the monitor program.

Abstract: A RAID storage device controller provides a host interface for interfacing the controller to a host system bus. The host interface is isolated from the attached storage devices, for example IDE disk drives, so that the actual attached drives are not limited in number or interface protocol. Various device ports can be implemented, and various RAID strategies, e.g. level 3 and level 5, can be used. In all the cases, the host interface provides a standard, uniform interface to the host, namely an ATA interface, and preferably a dual channel ATA interface. The host interface emulates the ATA single or dual channel interface and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to the controller. Thus, for example, five or seven IDE drives can be deployed in RAID level 5 protocol without changing the standard BIOS in a PCI host machine. Thus the RAID controller is transparent relative to a standard dual channel ATA controller board.

Abstract: A hard disk drive (HDD) emulator comprises a dynamic random access memory, a controller that refreshes content of the dynamic random access memory, and an input/output port coupled to the controller. The input/output port provides a hard disk drive interface. An operating system of a computing system in which the HDD emulator is installed uses the dynamic random access memory as a swap storage space.

Abstract: A read-write hard disk drive is emulated using a hard disk drive image file on a protected medium such as a CD-ROM, a written disk sector database, and file system filters. A file system filter intercepts file I/O requests from the operating system. Initial read requests are serviced from the hard disk drive image file. Write operations are directed to a database, such as in RAM. Subsequent read requests for previously written data are serviced from the database. Another file system filter monitors attempts to alter the file access attributes, and prevents pre-existing read-only files on the emulated drive from being written or deleted. The maximum size of the written disk sector database is the sum of sectors on the hard disk drive image file allocated to read-write files and free space. The emulated read-write hard disk drive allows for the execution of programs requiring a read-write native media.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: A method and a chipset for supporting a system management mode interrupt of a multi-processor system. While the central processing is accessing the specified input/output port defined by the chipset, the chipset detects the specified input/output port at the peripheral component interface bus and extracts the trap data to store into the chipset. Therefore, while entering the system management mode, a first central processing unit executes a proper operation according to the trap data of the chipset, and a second central processing unit stands by until the proper operation is completed by the first central processing unit. Thus, when the central processing units in a multi-processor system enters the system management mode, the first central processing unit can access the parameters from chipset even though the system management interrupt is induced by the second central processing unit and the parameters are stored in the second CPU's state dump area.

Abstract: An apparatus for connecting a computer bus to a network comprises a network interface capable of coupling to an external network and an emulator coupled to the network interface. The emulator comprises a processor control block that can emulate a host processor coupled to the computer bus and a device control block that can emulate a device coupled to the computer bus.

Abstract: A method for implementing the physical design for a dynamically reconfigurable logic circuit. The method is carried out using software that forms a physical design flow to take a design specification from a schematic or high-level description language (HDL) through to FPGA configuration bitstream files. The method involves reading a design netlist that was entered, the design netlist including a set of static macros and a set of reconfigurable macro contexts. Then, each of the reconfigurable macros are compiled and an initial device context is placed and routed. The device context is updated by arbitrarily selecting a context for each reconfigurable macro, placing and routing the updated device context and repeating the steps of updating, placing and routing until all of the reconfigurable macro contexts have been placed and routed. Then, after the compilation process is complete, full, partial, and incremental bitstream files are generated.

Abstract: An emulation system for data-driven processors which aims at shortening the emulation time by employing parallel processing techniques without increasing overhead. The emulation system emulates virtual data-driven processors by using real data-driven processors. The emulation is performed by dividing the functionality of the processor into a data path and a timing path. In the data path emulation, each virtual packet to be processed in the virtual processor is expressed as a PACKET message, and the processing operation of the virtual packet is evaluated for each functional block. In the timing path emulation, a SEND signal and an ACK signal, to be controlled by a self-timed transfer control mechanism and a gate logic, are expressed as a SEND message and an ACK message, respectively, and stage-to-stage transfer operations of the SEND signal and the ACK signal are evaluated.

Abstract: A configuration contains a test unit that, during emulation, replaces a program-controlled unit that is used in normal operation of the system containing the program-controlled unit. The test unit has a first program-controlled unit and a second program-controlled unit. The first program-controlled unit contains only some of the components of the program-controlled unit replaced by the test unit, and the second program-controlled unit contains those components of the program-controlled unit replaced by the test unit that are not contained in the first program-controlled unit. In addition, the first program-controlled unit contains a control device which monitors whether one of the components of the first program-controlled unit requests access to a component not present in the first program-controlled unit and which, if this is so, prompts appropriate access to the corresponding component in the second program-controlled unit.

Abstract: A communication system comprises a source media device, a sink media device communicatively coupled with the source media device over an out-of-band transfer protocol, a control point communicatively coupled to the source media device and the sink media device using communication control actions, and an emulator. The emulator can be contained in one or more of the source media device, the sink media device, and the control point. The emulator comprises a communication controller capable of coupling to an out-of-band communication link and an emulation controller capable of converting information between an out-of-band communication link format and a standard device internal format.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: An OS executed by a CPU employed in an information processing apparatus prepares a series of CCW commands and data to be transmitted or an area for receiving data in a main storage device, and issues a request to start an operation of an I/O function to an auxiliary-storage-device control unit. Receiving the request to start an operation of the I/O function, the auxiliary-storage-device control unit emulates each command in the series of CCWs to transmit or receive the data to or from another information processing apparatus, generating a command set to request the other information processing apparatus employing an embedded disk unit that information be read out from the disk unit.

Abstract: There is disclosed an apparatus for providing a virtual PCI device for use in a processing system comprising a data processor having an external peripheral bus coupled thereto in which peripheral devices associated with the external peripheral bus are controlled by accessing configuration circuitry associated with each of the peripheral devices. The apparatus comprises: a) an address trap circuit for detecting a configuration cycle accessing a virtual configuration address space associated with the virtual PCI device and generating an enable signal in response and b) an interrupt generation circuit associated with the address trap circuit that receives the enable signal and, in response, generates an interrupt signal that causes the data processor to execute instructions stored in system memory associated with the virtual device.

Abstract: Methods and systems for interfacing one or more Input/Output (I/O) controllers to a channel-based switched fabric. One or more channel adapters allow connection of the one or more I/O controllers to the channel-based switched fabric. The channel adapters support transferring of messages or data between the one or more I/O controllers and one or more initiating units connected to the channel-based switched fabric. An adaptable physical interface exists between the one or more I/O controllers and the adapters. A set of command primitives are used for communicating information between the one or more I/O controllers and the adapters via the physical interface.

Abstract: Clock cycle simulation involves modeling of clock cycles in a hardware module with a software model. Each simulated clock cycle involves several individual stages: Start, Execute, and End. During the start stage, output pin values for the model are calculated from an initial state of the module being simulated. Between the start stage and the execution stage, a combinatorial function of the modules outputs can be calculated. These calculated functions may be used as inputs to the modules in the execution stage. Afterwards, during the execute stage, input pin values are received by the model and the next state of the module is calculated based upon the current module state and the input pin values. Finally, during the last stage, i.e., the end stage, the internal state is updated; the internal state is defined as a set of the module's internal register and memory values.

Abstract: A method of, and apparatus for, processing the output of a design tool for an integrated circuit, the output relating to a circuit under design. A part of the circuit to be investigated is selected. Information relating to each signal in the selected part of the signal is then selected, and an output containing the selected information for the signals in the selected part of the circuit is generated.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: A multi-user simulation system is provided. The multi-user simulation system utilizes a processing unit with multiple ports, the processing system being coupled via communications lines to a central unit. The processing system is adapted to execute test software and communicate to the central unit via the multiple ports to emulate multiple users of a communications network, thus simulating real-world loading conditions of the communication network. A method for testing the central unit is also disclosed.

Abstract: An information processing system has first and second information processing apparatuses. The first information processing apparatus has an internal auxiliary storage device. The second information processing apparatus does not include an internal auxiliary storage device. Both information processing apparatuses have a main storage device, communication unit and auxiliary-storage-device control unit. The second information processing apparatus has an emulation mechanism for carrying out CKD-FBA format conversion to a series of CCW commands. Specifically, a command is set to access the internal auxiliary storage device and the emulation mechanism transmits the command set to the first information processing apparatus having the internal auxiliary storage device by way of the communication unit of the second information processing apparatus and a communication path.

Abstract: The present invention is directed to a peripheral device that integrally provides a program relating to the peripheral device, and may be connected to a computer system. The peripheral device includes a peripheral function subsystem for providing a peripheral device functionality. The peripheral device further includes a solid-state memory device storing a program relating to the peripheral device in a format used by disk drives. When the peripheral device is connected to a computer system, the program stored in the solid-state memory device is immediately available, and can be read by the computer system as though it was stored on a disk drive connected to the computer system.