Abstract: According to one embodiment, a random number generation circuit includes an oscillation circuit and a holding circuit. The oscillation circuit has an amplifier array and a high-noise circuit. Amplifiers are connected in series in the amplifier array, and the amplifier array has a terminal between neighboring amplifiers. The high-noise circuit is inserted between other neighboring amplifiers in the amplifier array, and the high-noise circuit generates noise required to generate jitter in an oscillation signal from the amplifier array. The holding circuit outputs, as a random number, the oscillation signal held according to a clock signal.

Abstract: A random number generator of a processor comprises a whitener for reducing the bias in random numbers generated by the random number generator. The whitener receives a random number of a first length read by an array of latches with inputs from an array of oscillators. The whitener dynamically creates a mask of the first length based on a parity of at least one previous random number read from the array of latches during at least one cycle prior to reading the random number. The whitener applies a compare operation between the random number and the mask to generate a whitened random number of the first length, with reduced bias, without reducing randomness.

Abstract: A random number generator of a processor comprises a whitener for reducing the bias in random numbers generated by the random number generator. The whitener receives a random number of a first length read by an array of latches with inputs from an array of oscillators. The whitener dynamically creates a mask of the first length based on a parity of at least one previous random number read from the array of latches during at least one cycle prior to reading the random number. The whitener applies a compare operation between the random number and the mask to generate a whitened random number of the first length, with reduced bias, without reducing randomness.

Abstract: A random number generator includes a first circuit producing a random sequence of values, the first circuit having an adjustable input that changes the entropy of the random sequence of numbers; a second circuit receiving the random sequence of values from the first circuit and producing an output indicative of the degree of entropy of the random sequence of values, and a third circuit that adjusts the adjustable input of the first circuit in response to the output of the second circuit.

Abstract: A random number generating device is provided. The random number generating device includes a first frequency generating circuit, a second frequency generating circuit and a flip-flop. The first frequency generating circuit generates a first frequency signal according to a signal inputted via an input end, and outputs the first frequency signal via an output end. The second frequency generation circuit generates and outputs a clock signal. The flip-flop includes a data input end, a clock input end and a data output end. The data input end and the clock input end are electrically connected to the first frequency generating circuit and the second frequency generating circuit respectively. The flip-flop outputs a random signal via the data output end according to the first frequency signal and the clock signal, and feedbacks the random signal to the first frequency generating circuit to change frequency of the first frequency signal.

Abstract: A device generates a random bit sequence with a digital ring oscillator circuit comprising logic components. The circuit has an input node and an output node, wherein the digital ring oscillator circuit is designed such that oscillation occurs during a change of state of a logic start signal coupled on the input node, said oscillation having a fixed point, and wherein on the output node a random signal can be tapped having an arbitrary level curve.

Abstract: An apparatus for generating a random number has high entropy. The apparatus includes a plurality of random number generators, each of which generates a metastability signal and generates a random number by using the generated metastability signal in a first mode, and in a second mode, the plurality of random number generators are connected to one another to operate as a ring oscillator.

Abstract: A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator.

Abstract: A method for detecting a correlation of a first ring oscillator with a second ring oscillator and a system for carrying out the method are provided. In the method, combinations of concatenations are compared to chronologically preceding concatenations.

Abstract: A random number generator includes a first oscillator configured to output a first oscillating signal having a first frequency. A second oscillator is configured to output a second oscillating signal having a second frequency different from the first frequency. A sampling unit is configured to receive the first and second oscillating signals. The sampling unit is configured to generate at least one entropy source by combining the received first and second oscillating signals. The sampling unit is configured to generate a random bit corresponding to the generated entropy source using a third oscillating signal. A third oscillator & control unit is configured to control the first and second oscillators and to generate the third oscillating signal. A frequency of the third oscillating signal is lower than the first and second frequencies.

Abstract: A random number generator includes oscillating units configured to generate entropy sources and amplify the generated entropy sources, an entropy source combination unit configured to receive the entropy sources output from the oscillating units and combine the entropy sources to increase entropy, a sampling unit configured to sample a signal output from the entropy source combination unit in response to a sampling clock, and a clock generator and control unit configured to control the oscillating units and generate the sampling clock.

Abstract: An apparatus includes a first counter for counting successive bits representative of a logic 1, and a second counter for counting successive bits representative of a logic 0, wherein a first predetermined count on the first counter or a second predetermined count on the second counter indicates a randomness failure. A method for testing randomness performed by the apparatus is also included.

Abstract: It is made possible to provide a random number generation device which generates a physical random number with as little power dissipation as possible. A random number generation device includes: a ring oscillator having at least one set, each set comprising a current noise source and a Schmitt inverter configured to receive an output of the current noise source; and a conversion circuit configured to convert output frequency fluctuation of the ring oscillator to a random number and output the random number.

Abstract: Novel random number generation methods and random number generators (RNG)s based on continuous-time chaotic oscillators are presented. Offset and frequency compensation loops are added to maximize the statistical quality of the output sequence and to be robust against parameter variations and attacks. We have verified both numerically and experimentally that, when the one-dimensional section was divided into regions according to distribution, the generated bit streams passed the tests used in both the FIPS-140-2 and the NIST 800-22 statistical test suites without post processing. Numerical and experimental results presented in this innovation not only verify the feasibility of the proposed circuits, but also encourage their use as the core of a high-performance IC RNG as well.

Abstract: According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.

Abstract: When an encryption processing circuit encrypts data, a current flows in the encryption processing circuit. A noise current generated by a noise generation circuit is superimposed on the current consumed by the encryption processing circuit. The present invention is applicable to an IC chip that encrypts plaintext data using a key, thus preventing the key from being broken by DPA attacks based on analysis of the current consumption to provide high security.

Abstract: An apparatus includes: a plurality of bit producing circuits; a controller setting a sample frequency at which bits from the bit producing circuits are sampled; and a plurality of test circuits determining if bits sampled from each of the bit producing circuits are random, wherein the controller adjusts the sample frequency if the test circuits determine that the sampled bits are not random. A method performed by the apparatus is also included.

Abstract: A random number generator includes: a variable frequency oscillator that includes: a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit including one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator.

Abstract: A method and an assemblage for generating random numbers. In the method, at a ring oscillator that comprises an odd number of inverting elements, values are picked off at at least two sampling points, an odd number of inverting elements being present in each case between at least two directly successive sampling points.

Abstract: An assemblage for monitoring an output of a random generator is provided, which assemblage compares chronologically successive sample values at a sampling point with one another in order to detect a relationship of the compared sample values with one another.

Abstract: Novel random number generation methods and novel random number generators based on continuous-time chaotic oscillators with dual oscillator architecture are presented. Numerical and experimental results not only verify the feasibility of the proposed circuits, but also encourage their use as a high-performance IC TRNG. In comparison with RNG's based on discrete-time chaotic maps, amplification of a noise source and jittered oscillator sampling, which are advantageous in the sense that true random behavior can be mathematically proven thanks to an analytical model that has been developed, it is seen that RNG's based on continuous-time' chaotic oscillators can offer much higher and constant data rated without post-processing. The proposed innovation increases the throughput, maximizes the statistical quality of the output sequence and is robust against external interference, parameter variations and attacks aimed to force throughout. The proposed circuits can be integrated on today process at GHz range.

Abstract: A random number generation method and apparatus using a low-power microprocessor is provided. In the random number generation method, a low-power microprocessor determines whether external power is supplied to a random number generator. The low-power microprocessor updates an internal state of the random number generator based on a first scheme if it is determined that the external power is supplied to the random number generator. The low-power microprocessor updates the internal state of the random number generator based on a second scheme different from the first scheme if it is determined that the external power is not supplied to the random number generator.

Abstract: Spread spectrum clock generators and electronic devices including the same are provided. An electronic device may include a memory and a first circuit block configured to output a first spread spectrum clock signal and a first address for accessing the memory. The electronic device may include a second circuit block configured to operate in response to a second spread spectrum clock signal, and configured to output a second address for accessing the memory. The electronic device may include a spread spectrum clock signal generator configured to receive the first spread spectrum clock signal to generate the second spread spectrum clock signal. The memory may be configured to compare the first and second addresses to each other to output a clock generator control signal corresponding to a difference between the first and second addresses.

Abstract: A property of a signal may be detected by sampling a signal and determining a scalar indicator of the samples. The samples can be transformed to create a transformed signal. A scalar indicator of the transformed signal may be determined and compared to the scalar indicator of the sample. If the comparison yields a number greater than a selected threshold value then the signal that was sampled may be deemed to include the property. A property indicator signal may be driven low or high to indicate that the signal has the property. The time and duration of time that the signal is deemed to include the property may be recorded. The recorded data may be reviewed and appropriate action may be taken.

Abstract: An apparatus includes an oscillator, a counter for counting pulses, and a latch for latching a count from the counter in response to changes in a logic level of an output of the oscillator. The apparatus can further include an edge detector for producing a latching signal in response to changes in the logic level of the output of the oscillator.

Abstract: A random number generation system comprising one or more ring oscillators configured to generate entropy due to accumulated phase drift. A random number generator can include a ring oscillator configured to switch between a first state in which a signal of the ring oscillator oscillates between logic levels, and a second state in which the signal at least partially settles to one of the logic levels. The random number generator can also include a counter configured to measure a count of pulses of the signal and a whitener mechanism configured to receive the signal from the ring oscillator, latch a logic level of the signal from the ring oscillator, latch the count of pulses from the counter, and generate a random number based on the logic level and the count of pulses. Corresponding methods may also be performed.

Abstract: The pseudorandom number generating system repeatedly performs simple transformation of a non-secure pseudorandom number sequence that may be generated quickly, and thus may quickly generate a highly secure pseudorandom number sequence having a long period. Furthermore, the encryption system and the decryption system do not generate a large encryption function difficult to be deciphered based on a shared key 122, but prepare multiple functions 126, which perform fast, different types of transformation, and select a combination of functions determined based on information of the shared key 122, and make the selected functions transform a text multiple times, thereby encrypt the text. Each of the functions is fast, and thus transformation by the entire combination is also fast. Furthermore, since the combination of functions and repetitive count can be changed, future improvement in specification is easy. Moreover, security is high since which functions are applied in what order is unknown.

Abstract: A device (1) for generating a random bit sequence has a digital ring oscillator circuit (2) having at least one first feedback path (R8) and one second feedback path (R14). To this end, a changeover is performed between the feedback paths (R8, R14) at times which can be predetermined, and a random signal (OS) having a random level history can be tapped at an output node (4) of the ring oscillator circuit (2).

Abstract: Random numbers are generated according to a variety of solutions. A particular solution relates to method for generating the random number. A common start signal is provided to each of a plurality of inverter components of a ring oscillator circuit. This causes the ring oscillator circuit to enter a metastable mode. At least a first bit and a second bit of a random number are both generated in parallel. The parallel generation of the bits involves the generation of the first bit from entropic properties of a signal of a first one of the plurality of inverter components and the generation of the second bit from entropic properties of a signal of a second one inverter components.

Abstract: Provided is an information security apparatus that has enhanced stability and confidentiality of a hash key. The information security apparatus includes an information generating PUF unit that has tamper resistance set, using physical characteristics, so as to output a preset hash key, a partial error-correction information storage unit that stores partial error-correction information, an error correcting PUF unit that has tamper-resistance set, using physical characteristics, so as to output error-correcting PUF information, an error-correction information generating unit that generates error-correction information using partial correction information and the error-correcting PUF information, and an error correcting unit that corrects an error for the hash key outputted from the information generating PUF unit and outputs an error-corrected hash key.

Abstract: A random number generating device includes: a microcomputer; a first oscillator circuit that has a predetermined temperature characteristic and generates a clock serving as a basis of a behavior of the microcomputer; and an electronic circuit that has a temperature characteristic being different from the predetermined temperature characteristic of the first oscillator circuit and operates in accordance with a command from the microcomputer. The microcomputer measures an operating time of the electronic circuit based upon the clock generated by the first oscillator circuit and generates a random number based upon a result of the measurement.

Abstract: A system and method of for obtaining a pseudorandom number generator are disclosed. A set of state modules, each with a limit value, may be provided. In an embodiment, each of the limit values may be relatively prime to the other limit values. In response to one or more events, the values of the state modules are incremented. At some frequency that may be statistically independent from the occurrence of the one or more events, the values of the state modules are obtained and combined to form a random number. The values may be combined as desired and, if desired, may be combined modulo 2w, where 2w represents the number of possible random values.

Abstract: A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Abstract: A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

Abstract: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.

Abstract: An apparatus for generating a random bit sequence has a ring oscillator which includes inverting digital devices and on which an oscillator signal can be tapped. An intermediate storage element monitors and stores fluctuating levels of the oscillator signal. At least two controllable switch devices for simultaneously exciting at least two harmonic wave edges of the ring oscillator are provided in a signal path of the ring oscillator. The phasing of the two harmonic wave edges and a potential convergence thereof are subject to statistical fluctuations, which are used as a basis for the random bit generation. A corresponding random number generator can be used in particular as an FPGA for security applications, such as cryptographic methods. The apparatus has substantially digital components, which are easy to produce in a standardized manner. A dedicated regulating circuit is not necessary. The apparatus is also robust toward exterior influences.

Abstract: A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.

Abstract: A method of generating a number includes asynchronously updating a plurality of linear feedback shift registers, selecting a mixing function using a balanced entropy value, and determining the number from bit values selected from the plurality of linear feedback shift registers based on the selected mixing function.

Abstract: A device includes a plurality of linear feedback shift registers, a counter having a counter value of a bit length, and a comparator to compare the counter value and an update value including bit values of bit positions of a first linear feedback shift register. The number of bit positions equal to the bit length of the counter value. A second linear feedback shift register to update based on the comparison.

Abstract: A system is described for generating random numbers. The system may include a plurality of information sources and one or more sampling devices coupled to each of the information sources. Each information source may have a characteristic which may differ from the characteristic of any other information source. The sampling devices may sample the information sources at some sampling interval. A sample value may be captured from each of the information sources by the sampling devices coupled thereto at the sampling interval. An output representative of a substantially random number may be derived from the sample values captured at the sampling interval.

Abstract: Provided is a random number generator including: a clock generator outputting first and second control signals; a ring oscillator (RO) block receiving a meta stable voltage and performing an oscillation operation using the meta stable voltage in response to the first control signal; and a sampling unit sampling an output signal according to the oscillation operation in response to the second control signal.

Abstract: The invention reduces unnecessary electromagnetic radiation noise due to an operation clock signal generated by an oscillator circuit. Random number data outputted by a random number generation circuit is stored in a frequency variable data register. The data stored in the frequency variable data register is replaced by random number data sequentially generated by the random number generation circuit. An oscillator circuit is a circuit generating a clock signal, and the clock signal is supplied as an operation clock signal to an internal circuit through an operation clock signal generation circuit. The frequency of the clock signal from the oscillator circuit is variably controlled in response to the random number data stored in the frequency variable data register. A frequency variable range control register which stores control data for controlling the range of the frequency variably controlled in response to the random number data stored in the frequency variable data register is further provided.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for generating random data at an early stage in a boot process. A system practicing the method performs, by a processor based on a first clock, a group of reads of a counter running on a second clock to yield entropy words. In order to produce words with entropy, the system introduces a progressively increasing delay between each of the group of reads of the counter. The system generates entropy words by filling the buffer with successive reads of the least significant bit of the counter and then generates random data by applying a hash algorithm to the entropy words stored in the buffer.

Abstract: An apparatus and method for generating a random number are provided, the apparatus having at least one generator circuit, each generator circuit being configured to provide a first operating mode and a second operating mode, in the first operating mode each generator circuit operating as an oscillator, and in the second operating mode each generator circuit operating as a state retention element. A control signal generator then generates a control signal for input to each generator circuit. Each generator circuit is responsive to the input control signal being at a set level to operate in the first operating mode, and is responsive to the input control signal being at a clear level to operate in the second operating mode. On a transition of the input control signal from the set level to the clear level, each generator circuit is configured to capture within the state retention element a current value of the oscillator, and to output that current value to form at least part of the random number.

Abstract: An apparatus and method for generating a random number are provided, the apparatus having at least one generator circuit, each generator circuit being configured to provide a first operating mode and a second operating mode, in the first operating mode each generator circuit operating as an oscillator, and in the second operating mode each generator circuit operating as a state retention element. A control signal generator then generates a control signal for input to each generator circuit. Each generator circuit is responsive to the input control signal being at a set level to operate in the first operating mode, and is responsive to the input control signal being at a clear level to operate in the second operating mode. On a transition of the input control signal from the set level to the clear level, each generator circuit is configured to capture within the state retention element a current value of the oscillator, and to output that current value to form at least part of the random number.

Abstract: A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data.

Abstract: A system comprising a feedback shift-register having L serially connected stages, and a non-linear feedback sub-system to receive input from stage n and 2n+1, and including a first AND gate having a first and second input operationally connected to the output of stage n and 2n+1, respectively, the sub-system having an output based on a value of an output of the first AND gate, a bit generator operative to generate bits, and an XOR gate having a first and second input, an output of the bit generator being operationally connected to the first input of the XOR gate, the output of the sub-system being operationally connected to the second input of the XOR gate, the output of the XOR gate being operationally connected to the input of the first stage of the shift-register. Related apparatus and methods are also described.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.