Abstract: According to one embodiment, a random number generation circuit includes an oscillation circuit and a holding circuit. The oscillation circuit has an amplifier array and a high-noise circuit. Amplifiers are connected in series in the amplifier array, and the amplifier array has a terminal between neighboring amplifiers. The high-noise circuit is inserted between other neighboring amplifiers in the amplifier array, and the high-noise circuit generates noise required to generate jitter in an oscillation signal from the amplifier array. The holding circuit outputs, as a random number, the oscillation signal held according to a clock signal.

Abstract: An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.

Abstract: A system and method for estimating a signal based on a stream of randomly generated samples. The method includes: (a) receiving a sample; (b) generating a sampling vector; (c) multiplying the sample and the sampling vector to obtain a current back projection; (d) computing a first intermediate vector that represents an average of the current back projection and previous back projections; (e) transforming the first intermediate vector to determine a second intermediate vector; (f) identifying locations where the second intermediate vector attains its k largest values; (g) computing an estimate for the transformation of the signal by solving a system of equations based on the identified locations, the received sample value, previously received sample values, the sampling vector and previously generated sampling vectors; (h) inverse transforming the transformation estimate to determine an estimate of the signal; and (i) storing the signal estimate.

Abstract: Method and device for generating factors of a RSA modulus N with a predetermined portion Nh, the RSA modulus comprising at least two factors. A first prime p is generated; a value Nh that forms a part of modulus N is obtained; a second prime q is generated in an interval dependent from p and Nh so that pq is a RSA modulus that shares Nh; and information enabling the calculation of the modulus/V is outputted.

Abstract: The invention concerns a random number generator comprising a n-bit LSFR at least one oscillator having at least one delay element introducing a variable delay in the counter feedback loop, and at least one sampling/holding device having at least one input coupled to an output of the oscillator, and at least one output coupled to a input of the LSFR, and a clock input receiving a sampling clock signal at a much lower frequency than the oscillator frequency. Said generator is for example configured to vary the delay introduced by the oscillator delay based on a number q of feedback bits among the n bits of the LSFR output, where q is a an integer such that 1?q?n.

Abstract: A random number generator uses the output of a true random generator to alter the behavior of a pseudo-random number generator. The alteration is performed by a mixing logic that builds a random seed for the pseudo-random number generator and includes a generator of an alteration signal, the generation of which exploits the random instant of arrival of the bits outgoing from the true random generator. The alteration signal is obtained by processing the seed by means of the pseudo-random sequence.

Abstract: A random binary sequence generator for generating a random binary sequence adapted to be used for producing random numbers, includes at least one logic circuit corresponding to an associated finite-state machine having a state-transition function including states arranged to form cycles of states, wherein the at least one logic circuit has a set of logic circuit inputs and a set of logic circuit outputs fed back to the logic circuit inputs; the associated finite-state machine is autonomous and asynchronous; the state-transition function is void of loops; and any of the cycles of states has either a minimum length equal to three states, in case the cycle is stable, or a minimum length of two states, in case the cycle is meta-stable.

Abstract: A method for random number generation includes generating random number sequences using a Random Number 5 Generator (RNG) circuit having an externally-modifiable configuration. The RNG circuit generates a first random number sequence having a first measure of randomness, and modifies the configuration of the RNG circuit, causing the RNG circuit to generate a second random number sequence having a second measure of the randomness, indicating a degree of the randomness that is no less than the first measure.

Abstract: True random number generation circuitry utilizes a pair of oscillators driving a pair of linear feedback shift registers, with their output being combined to generate random numbers. At least one of the oscillators is programmable with a variable frequency. One embodiment controls the variable frequency of oscillators with output from one or more sets of oscillators and linear feedback shift registers. In other embodiments, linear feedback shift register output is captured and used to control the frequency of oscillators.

Abstract: A random number generator generates a string of random bits from a received RF signal source. A sample-and-hold circuit is coupled to the received RF signal source. The RF signal is sampled by a jittered clock signal from a source coupled to the sample-and-hold circuit. The frequency of the jittered clock signal is less than frequency of the received RF signal. The random number appears at the output of the sample-and-hold circuit.

Abstract: An apparatus for generating a random number has high entropy. The apparatus includes a plurality of random number generators, each of which generates a metastability signal and generates a random number by using the generated metastability signal in a first mode, and in a second mode, the plurality of random number generators are connected to one another to operate as a ring oscillator.

Abstract: A random number generating circuit comprises: the seed generating circuit which generates a seed; and a pseudo random number circuit which generates pseudo random numbers based on the seed generated by the seed generating circuit. The seed generating circuit has: an oscillating circuit which oscillates continuously or intermittently, and which outputs a digital data sequence; a smoothing circuit which outputs time series data by controlling appearance frequencies of “0” and “1” in the digital data sequence outputted from the oscillating circuit; and a postprocessing circuit which generates one-bit seed by a computation using a plurality of bits included in the time series data.

Abstract: A random number generator and a random number generating method thereof are provided. The random number generator includes a signal generating unit and a sampling unit. The signal generating unit is adapted for memorizing a status of a noise generated during a transient of an output signal of an output buffer, and accordingly generating a frequency conversion signal which changes according to time and ambient factors. The sampling unit is coupled to the signal generating unit for receiving the frequency conversion signal, and sampling the frequency conversion signal according to a sampling clock pulse, so as to obtain a plurality of sets of unpredictable random number codes.

Abstract: Methods of securely communicating a message from a first terminal to a second terminal include generating a keypad including a random sequence of bits having a length L, encrypting the message at the first terminal using a bit string beginning at an offset O in the keypad, and transmitting the encrypted message and an indicator of the offset O to the second terminal. A communication terminal includes a controller, a communication module configured to establish a location-limited communication channel, and an encryption unit configured to store a keypad including a random sequence of bits having a length L, to encrypt an outgoing message using the keypad, and to decrypt an incoming message using the keypad.

Abstract: Disclosed is a method for deriving random numbers at a higher speed than ever before while maintaining desired randomness without spoiling uniformity of the occurrence frequency of each random number. One pulse included in one of two or more mutually-independent random pulse sequences and one pulse included in one of the remaining random pulse sequences are used, respectively, as a start pulse and a stop pulse. Then a time interval between the start pulse and the stop pulse is measured, and the measured value is output. The pulses temporally occur in a random manner, and therefore the obtained sequence of numerical values becomes random numbers. Specifically, in FIG. 1, time intervals t1 to t4 are measured, and these measured values (in FIG. 1, four values) are derived as random numbers.

Abstract: An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream.

Abstract: Embodiments of the present invention provide a random number generating apparatus, including a first level sampling module and a second level sampling module. The first level sampling module includes a first oscillator, a second oscillator and a first sampler capable of sampling the first oscillating signal with the second oscillating signal to generate a first output signal. The second level sampling module includes a voltage-controlled oscillator capable of generating a voltage-controlled oscillating signal by using the first output signal as a control voltage, a third oscillator capable of generating a third oscillating signal, and a second sampler, capable of sampling the third oscillating signal with the voltage-controlled oscillating signal and generating random numbers. The first level oscillator sampling provides a random control voltage for the second level oscillator sampling, therefore improving the randomicity of the second level oscillator sampling as well as the random number generating rate.

Abstract: Provided is a random number generating circuit having a simple circuit structure, for generating a physical random number based on a noise. The random number generating circuit includes a reference voltage section, an inverting amplifier section having a threshold voltage equal to a reference voltage level, and a semiconductor switch provided between an output terminal of the reference voltage section and an input terminal of the inverting amplifier section. A thermal noise produced from the reference voltage section is held by the semiconductor switch and a capacitor and amplified by the inverting amplifier section to generate the physical random number.

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract: A random number generator includes a signal generator and a sampling unit. The signal generator is configured to generate an alternating sequence of metastable seed signals and oscillating signals during respective first and second half-periods of a clock signal. The oscillating signals having respective phases determined by corresponding ones of the metastable seed signals in the alternating sequence. The sampling unit is configured to detect a logic value of each consecutive oscillating signal during a portion of a respective half-period of the clock signal. The signal generator may be responsive to the clock signal and the sampling unit may be responsive to a delayed version of the clock signal.

Abstract: Apparatus and method for generating an initial value for a pseudo-random number generator, with an oscillator configured to generate an oscillator signal; and a generator configured to generate the initial value based on the oscillator signal at least during part of a transient of the oscillator.

Abstract: Random number generating, encrypting, and decrypting apparatus, method thereof, program thereof, and recording medium thereof are provided. Random numbers for cryptographic applications are generated by a CA core. The CA core is composed of one-dimensional, two-state, and three-neighbor cell automaton. A total of three inputs for the own cell and both neighbor cells are input to each cell. Each cell performs a logical operation and outputs the result of the logical operation. Each cell contains a register. Each register captures the result of the logical operation in synchronization with a clock and stores the result. An output of a cell is fed back to the cell to perform an arithmetic calculation at the next time step. In this case, a rotation shift operation of which outputs of cells are shifted to the left and fed back to the cells is performed. To output random numbers having many bits, 40 bits of outputs of cells are selected.

Abstract: A physical random number generation device includes a physical random number generation source which generates a white noise, an AD conversion module which inputs the white noise for conversion to a physical prime random number as digital data, a physical prime random number sequence generation module which inputs two or more physical prime random numbers to generate a physical prime random number sequence, a white noise array generation module for inputting the physical prime random number sequence and for generating a white noise array, a white noise composition module for generating multiple physical random numbers from the input white noise array, and an interface for externally outputting the generated physical random numbers as physical random number data. With this arrangement, multiple physical random numbers are generated at high speeds from the physical prime random number(s) taken out of the physical random number generation source as digital data.

Abstract: In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.

Abstract: The invention relates to a circuit for generating a true, circuit-specific and time-invariant random binary number, having: a matrix of K?L delay elements that can be connected to each other by means of L?1 single or double commutation circuits into chains of delay elements of length L, a single or double demultiplexer connected before the matrix, a single or double multiplexer connection after the matrix, and a run time or number comparator, wherein the setting of the commutation circuits, the demultiplexer, and the multiplexer can be prescribed by a control signal, wherein the circuit comprises a channel code encoder whereby code words of a channel code can be generated and a transcriber, whereby code words of the channel code can be transcribed into the control signal of the L?1 single or double commutation circuits, and a method for generating a true, circuit-specific and time-invariant random number by means of a matrix of L?K delay elements, L?1 single or double commutation circuits, a single or double

Abstract: A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.

Abstract: A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Abstract: Random number generators are used for entertainment in gambling, lotteries and video gaming devices. True Random Number Generators, as are now currently defined, must be actuated by a physical noise source, typically based on the uncertainty of the phase differences of a stable and an unstable autonomous oscillator. In this invention an autonomous random frequency modulated oscillator driven by a self contained pseudo-random number generator outputs three loosely correlated random binary streams. Included in the invention is a hardware method for proving wandering phase differences and also the existence of a colored random distribution of concatenated nibbles.

Abstract: A true random number generator (TRNG) in an integrated circuit comprises a plurality of independent ring oscillators with multiple output taps combined into enhanced outputs, a plurality of delay lines, a combiner-sampler and a source of a clock signal. Some embodiments provide a TRNG that is resettable, allowing one or more independent random numbers to be generated in response to a trigger signal.

Abstract: A method for generating random numbers in which oscillating digital output signals of unequal or equal periodicity are generated by at least two ring oscillators, an external parity signal representing a logical state being generated when an odd number of the output signals take on a specified logical state, the external parity signal being fed back to an external parity input of each of the respective ring oscillators. Also, a random number generator having at least two ring oscillators made up of independently freewnning inverter chains with feedback having an odd number of series-connected inverters that generate oscillating digital output signals of unequal or equal periodicity, and having first panty signal generating mechanisms that generate an external parity signal representing a logical state when an odd number of the output signals take on a specified logical state.

Abstract: An apparatus and method for generation of a noise signal are provided. The apparatus includes a noise synthesizing module and a noise signal transfer module. The noise synthesizing module includes a voltage controlled oscillator, a phase frequency detector, a phase locked loop filter, and a reference generator which form a phase locked loop. An output signal of the reference generator is provided to a first phase-frequency input of the phase-frequency detector, and an output signal of the voltage controlled oscillator is provided to a second input of the phase-frequency detector. An output signal of the phase-frequency detector is provided to an input of the phase locked loop filter, and an output of the phase locked loop filter is provided to a frequency control input of the voltage controlled oscillator.

Abstract: A device generates a random bit sequence with a digital ring oscillator circuit comprising logic components. The circuit has an input node and an output node, wherein the digital ring oscillator circuit is designed such that oscillation occurs during a change of state of a logic start signal coupled on the input node, said oscillation having a fixed point, and wherein on the output node a random signal can be tapped having an arbitrary level curve.

Abstract: Novel random number generation methods and novel random number generators based on continuous-time chaotic oscillators with dual oscillator architecture are presented. Numerical and experimental results not only verify the feasibility of the proposed circuits, but also encourage their use as a high-performance IC TRNG. In comparison with RNG's based on discrete-time chaotic maps, amplification of a noise source and jittered oscillator sampling, which are advantageous in the sense that true random behavior can be mathematically proven thanks to an analytical model that has been developed, it is seen that RNG's based on continuous-time' chaotic oscillators can offer much higher and constant data rated without post-processing. The proposed innovation increases the throughput, maximizes the statistical quality of the output sequence and is robust against against external interference, parameter variations and attacks aimed to force throughout. The proposed circuits can be integrated on today process at GHz range.

Abstract: An apparatus includes: a plurality of bit producing circuits; a controller setting a sample frequency at which bits from the bit producing circuits are sampled; and a plurality of test circuits determining if bits sampled from each of the bit producing circuits are random, wherein the controller adjusts the sample frequency if the test circuits determine that the sampled bits are not random. A method performed by the apparatus is also included.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a random number generator (RNG) based on oscillator noise. In some embodiments, the RNG buffers effects of thermal noise from two independent oscillators impacted by effects of pseudo-stochastic processes and separates thermal noise from other effects. The RNG may then convert the thermal noise to a stochastic binary sequence based, at least in part, on a digital signal processing algorithm.

Abstract: A system comprising a feedback shift-register having L serially connected stages, and a non-linear feedback sub-system to receive input from stage n and 2n+1, and including a first AND gate having a first and second input operationally connected to the output of stage n and 2n+1, respectively, the sub-system having an output based on a value of an output of the first AND gate, a bit generator operative to generate bits, and an XOR gate having a first and second input, an output of the bit generator being operationally connected to the first input of the XOR gate, the output of the sub-system being operationally connected to the second input of the XOR gate, the output of the XOR gate being operationally connected to the input of the first stage of the shift-register. Related apparatus and methods are also described.

Abstract: Novel random number generation methods and random number generators (RNG)s based on continuous-time chaotic oscillators are presented. Offset and frequency compensation loops are added to maximize the statistical quality of the output sequence and to be robust against parameter variations and attacks. We have verified both numerically and experimentally that, when the one-dimensional section was divided into regions according to distribution, the generated bit streams passed the tests used in both the FIPS-140-2 and the NIST 800-22 statistical test suites without post processing. Numerical and experimental results presented in this innovation not only verify the feasibility of the proposed circuits, but also encourage their use as the core of a high-performance IC RNG as well.

Abstract: Presently disclosed is method and apparatus for generating a random bit stream by generating a random bit according to a polynomial expression, providing a modification function operative on the polynomial expression, and modifying the polynomial expression by modifying the modification function.

Abstract: A circuit that generates a random number includes a phase-locked loop circuit and a sampling circuit. The phase-locked loop circuit generates an internal clock signal that is synchronized with a reference signal in which the internal clock has a random noise. The sampling circuit samples the reference signal in response to the internal clock signal to generate a random data bit. The circuit of generating a random number is capable of generating a random number with high randomness and is capable of operating at a relatively low frequency.

Abstract: A method and apparatus for obtaining, while on a spacecraft, a random number and hence a secure cryptographic key. The method includes the steps of providing, on the spacecraft, a device capable of producing random information when subject to random space phenomena, obtaining the random information and producing a random number therefrom and using an algorithm to establish the secure key. The apparatus includes a random access memory which experiences bit-flips when struck by radiation such as cosmic rays. Changes in the RAM bits are propagated using a linear feedback shift register.

Abstract: An apparatus and a method are provided for generating a random number, wherein the randomness of the random number is derived from thermal noise present across a pair of resistors. Each of the pair of resistors is defined to receive a respective input voltage and add a respective noise component to the input voltage. The output from each resistor in the pair of resistors is amplified to generate a noisy analog voltage that includes a representation of the random noise components added by the pair of resistors. The randomly varying noisy analog voltage is used to control a voltage controlled oscillator (VCO). The VCO generates a random digital signal based on the randomly varying noisy analog voltage. The random digital signal generated by the VCO is used to set a number of bits for defining a random number.

Abstract: An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and second inverters is connected to the second input of the first inverter; and a third inverter connected between the output of the first and second inverters and the first input of the second inverter.

Abstract: True random number generation circuitry utilizes a pair of oscillators driving a pair of linear feedback shift registers, with their output being combined to generate random numbers. At least one of the oscillators is programmable with a variable frequency. One embodiment controls the variable frequency of oscillators with output from one or more sets of oscillators and linear feedback shift registers. In other embodiments, linear feedback shift register output is captured and used to control the frequency of oscillators.

Abstract: A method and apparatus for generating a random bit stream in true random number generator fashion are described. Two periodic signals are employed in generating the random bit stream. A first periodic signal having preferably an approximately fifty percent duty cycle and jitter induced by supply and substrate noise is sampled by a second periodic signal that is relatively jitter-free and of a lower frequency than the first periodic signal.

Abstract: A random number generator includes: a variable frequency oscillator that includes: a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit including one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator.

Abstract: A device for generating a random sequence (10) of bits is disclosed. The device comprises oscillating means (13), which will generate a random sequence of bits when biased with a noise signal. The oscillating means comprises at least one oscillator amplifier being protected from interfering signals by means of a load and a tail-current source for providing high noise-interference ratio. Further, the present invention relates to an integrated circuit and an electronic apparatus comprising the device for generating a random sequence according to the invention.

Abstract: A seedable pseudo-random number generator. A linear feedback shift register (LFSR) arrangement is used to generate a first pseudo-random number, and a cellular automata is used to generate a second pseudo-random number. The bits of the LFSR arrangement are XORed with bits of the cellular automata to generate the output pseudo-random number.

Abstract: It is made possible to provide a random number generation device which generates a physical random number with as little power dissipation as possible. A random number generation device includes: a ring oscillator having at least one set, each set comprising a current noise source and a Schmitt inverter configured to receive an output of the current noise source; and a conversion circuit configured to convert output frequency fluctuation of the ring oscillator to a random number and output the random number.

Abstract: The invention concerns a random number generator comprising a n-bit LSFR at least one oscillator having at least one delay element introducing a variable delay in the counter feedback loop, and at least one sampling/holding device having at least one input coupled to an output of the oscillator, and at least one output coupled to a input of the LSFR, and a clock input receiving a sampling clock signal at a much lower frequency than the oscillator frequency. Said generator is for example configured to vary the delay introduced by the oscillator delay based on a number q of feedback bits among the n bits of the LSFR output, where q is a an integer such that 1?q?n.

Abstract: A random number generator and a random number generating method thereof are provided. The random number generator includes a signal generating unit and a sampling unit. The signal generating unit is adapted for memorizing a status of a noise generated during a transient of an output signal of an output buffer, and accordingly generating a frequency conversion signal which changes according to time and ambient factors. The sampling unit is coupled to the signal generating unit for receiving the frequency conversion signal, and sampling the frequency conversion signal according to a sampling clock pulse, so as to obtain a plurality of sets of unpredictable random number codes.