Abstract: A method for random number generation includes generating random number sequences using a Random Number Generator (RNG) circuit having an externally-modifiable configuration. The RNG circuit generates a first random number sequence having a first measure of randomness, and modifies the configuration of the RNG circuit, causing the RNG circuit to generate a second random number sequence having a second measure of the randomness, indicating a degree of the randomness that is no less than the first measure.

Abstract: A random number generator. The random number generator includes a noise source, a circuit controlling random current consumption, and a circuit generating random bits. A noise voltage output from the noise source drives the circuit controlling random current consumption, which also generates a random control signal. The circuit generating random bits also includes a voltage-controlled oscillator, a plurality of frequency dividers, and a plurality of flip-flops. The voltage-controlled oscillator is controlled by both the noise voltage and the random control signal. The output of the voltage-controlled oscillator is input to the frequency dividers and the flip-flops to generate a random number.

Abstract: A system and method of for obtaining a pseudorandom number generator are disclosed. A set of state modules, each with a limit value, may be provided. In an embodiment, each of the limit values may be relatively prime to the other limit values. In response to one or more events, the values of the state modules are incremented. At some frequency that may be statistically independent from the occurrence of the one or more events, the values of the state modules are obtained and combined to form a random number. The values may be combined as desired and, if desired, may be combined modulo 2w, where 2w represents the number of possible random values.

Abstract: Provided is a random number generator including: a clock generator outputting first and second control signals; a ring oscillator (RO) block receiving a meta stable voltage and performing an oscillation operation using the meta stable voltage in response to the first control signal; and a sampling unit sampling an output signal according to the oscillation operation in response to the second control signal.

Abstract: A method for generating random data, the method comprising repeatedly performing a series of operations, and the series of operations comprising processing a seed value to generate a resulting value for use as the seed value in a subsequent performance of the series of operations and to generate output random data; wherein the series of operations also comprises: determining whether a predetermined amount of new truly random data is available; and if such data is available, modifying the generation of at least the resulting value in dependence on the new truly random data.

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract: A device for generating a noise signal, which may be used for generating a truly random sequence (10) of bits is disclosed. The device comprises a noise source (11), and an amplifier (12) connected to the noise source (11). The device according noise source according to the invention is protected from interfering signals to provide high noise-interference ratio. Further, the present invention relates to an integrated circuit and an electronic apparatus comprising the device for generating a noise signal according to the invention.

Abstract: An apparatus includes a first counter for counting successive bits representative of a logic 1, and a second counter for counting successive bits representative of a logic 0, wherein a first predetermined count on the first counter or a second predetermined count on the second counter indicates a randomness failure. A method for testing randomness performed by the apparatus is also included.

Abstract: An apparatus includes an oscillator, a counter for counting pulses, and a latch for latching a count from the counter in response to changes in a logic level of an output of the oscillator. The apparatus can further include an edge detector for producing a latching signal in response to changes in the logic level of the output of the oscillator.

Abstract: An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: A random number generating circuit comprises: the seed generating circuit which generates a seed; and a pseudo random number circuit which generates pseudo random numbers based on the seed generated by the seed generating circuit. The seed generating circuit has: an oscillating circuit which oscillates continuously or intermittently, and which outputs a digital data sequence; a smoothing circuit which outputs time series data by controlling appearance frequencies of “0” and “1” in the digital data sequence outputted from the oscillating circuit; and a postprocessing circuit which generates one-bit seed by a computation using a plurality of bits included in the time series data.

Abstract: A random number signal generator using pulse oscillators, the generator including: a first pulse oscillator oscillating a first pulse at high speed; a second pulse oscillator oscillating a second pulse; a sampler receiving an output pulse of the first oscillator as data, receiving an output pulse of the second pulse oscillator as a clock signal, and outputting a plurality of output signals; and a digital processor generating a random number signal with a desired size by using the output signals of the sampler.

Abstract: A random number generator includes an amplifier to amplify a difference between a noise signal and a reference signal to generate an amplified signal, a plurality of binarization circuits configured to binarize the amplified signal by using different inherent threshold values to obtain a plurality of binarized signals, and an exclusive OR circuit to perform an exclusive OR operation on the a plurality of binarized signals to generate random number sequence.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: Embodiments of the present invention provide a random number generating apparatus, including a first level sampling module and a second level sampling module. The first level sampling module includes a first oscillator, a second oscillator and a first sampler capable of sampling the first oscillating signal with the second oscillating signal to generate a first output signal. The second level sampling module includes a voltage-controlled oscillator capable of generating a voltage-controlled oscillating signal by using the first output signal as a control voltage, a third oscillator capable of generating a third oscillating signal, and a second sampler, capable of sampling the third oscillating signal with the voltage-controlled oscillating signal and generating random numbers. The first level oscillator sampling provides a random control voltage for the second level oscillator sampling, therefore improving the randomicity of the second level oscillator sampling as well as the random number generating rate.

Abstract: A random number generating circuit comprises: the seed generating circuit which generates a seed; and a pseudo random number circuit which generates pseudo random numbers based on the seed generated by the seed generating circuit. The seed generating circuit has: an oscillating circuit which oscillates continuously or intermittently, and which outputs a digital data sequence; a smoothing circuit which outputs time series data by controlling appearance frequencies of “0” and “1” in the digital data sequence outputted from the oscillating circuit; and a postprocessing circuit which generates one-bit seed by a computation using a plurality of bits included in the time series data.

Abstract: Method and apparatus for true random number generation is described. One aspect of the invention relates to a digital logic circuit that includes N logic gates, where N is an integer greater than two. For each logic gate in the N logic gates: a first input terminal thereof is coupled to an output terminal thereof; a second input terminal thereof is coupled to an output terminal of a left neighbor thereof; and a third input terminal thereof is coupled to an output terminal of a right neighbor thereof. A sampling logic circuit may be provided to sample the output of the N logic gates to produce N-bit binary numbers. The N-bit binary numbers are true random numbers produced using pure digital logic without using an external source of randomness. A linear hybrid cellular automaton (LHCA) may be provided for scrambling output data of the sampling circuit.

Abstract: A pseudo-random number generator comprises a linear feedback register for generating pseudo-random numbers; and a signal generator for generating a shift clock for operating a linear feedback register and predetermined input data. The linear feedback register has a plurality of registers connected in series, a first logical operation circuit for taking logical operation of output data from predetermined registers to deliver the result thereof, and a second logical operation circuit for taking logical operation of input data supplied from the outside and output data of the first logical operation circuit to supply the result thereof to any one of the registers.

Abstract: An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an input also for receiving the common signal from the digital signal generator. Each of the delay units is attached to the input of a respective logic gate. A frequency measurement of the occurrences of metastability, which is the speed of the random bit generation and delay tuning module 312 receives an output of one of the first NAND gates, checks the frequency of random number bit generation and updates the variable delay unit to according to predetermined criteria to tune the delay so as to maximize the speed of the random bit generation. An algorithm is used to determine whether the optimum delay is equal to, smaller or larger than the delay used to achieve the measured frequency.

Abstract: Apparatus and method for generating an initial value for a pseudo-random number generator, with an oscillator configured to generate an oscillator signal; and a generator configured to generate the initial value based on the oscillator signal at least during part of a transient of the oscillator.

Abstract: A random number generator includes a flip-flop, and a pair of independent free-running oscillators having a respective set of 4 switches controlled with a non-inverted and inverted output of the flip-flop. An output from each of the oscillators is fed back to their respective input via a delay device. The pair of oscillators each has a feedback loop switch, and a pair of cross gate switches, each of which respectively connects an input signal of one oscillator to an output of another oscillator of the pair of oscillators. When the feedback loop switches are open and the cross gate switches are closed, the pair of oscillators forming a flip-flop with positive feedback resolves to a logic state that in a metastable way, producing an unpredictable (random) logic signal.

Abstract: A cryptographic key 1 constituted to be freely attachable and detachable to/from a personal computer 2 encrypting and decrypting data by use of a cipher key includes: a pseudo random number generator 14 for generating a pseudo random number of a chaotic time series based on a data size of the data, a chaotic function and an initial value of the chaotic function; and a USB controller 12 for receiving the data size of the data from the personal computer 2 and transmitting the pseudo random number of the chaotic time series as the cipher key to the personal computer 2, the pseudo random number being generated in the pseudo random number generator 14, when the cryptographic key 1 is attached to the personal computer 2.

Abstract: A random number generator includes a flip-flop in which an output state (0 or 1) becomes definite according to a phase difference between signals inputted to two input units, a delay unit for producing the phase difference in these two input signals, and a feedback circuit for controlling the phase difference so that an occurrence ratio of 0 or 1 of an output from the flip-flop by the input signals is constant within a specified repetition cycle.

Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.

Abstract: An apparatus for providing a jittered clock signal has a reverse-biased diode. The reversed-biased diode has a leakage current which decreases a reverse voltage on the diode, time-dependent on a shot-noise of the leakage current. The apparatus for providing a jittered clock signal further has a unit for periodically increasing the reverse voltage of the diode to a value, which is above a switching value and the apparatus has a unit for comparing the reverse voltage of the diode to the switching value and for outputting a jittered clock signal dependent on the comparison.

Abstract: A generator of random numbers by a flip-flop having a data input receiving a first signal at a first frequency comprised in a predetermined range and the instantaneous value of which is conditioned by a disturbing signal, and having a clock input receiving a second signal at a second predetermined frequency, smaller than the first one, said second signal passing through a delay element giving it a delay greater than or equal to the maximum period of the first signal.

Abstract: A method of producing a uniform duty cycle output from a random bit source. The method includes testing the duty cycle of said random bit source; varying the output voltage of a voltage source if the duty cycle is not substantially fifty percent; and iteratively altering the output voltage of the voltage source until said duty cycle is substantially fifty percent.

Abstract: A white noise generator comprising a MOSFET operated in its linear region and having zero source-drain DC bias current. This is achieved by connecting the source or drain terminal of the MOSFET to a gate terminal of a MOSFET amplifier that may be implemented as a multi-stage differential amplifier. Such a noise source avoids the effect of DC current responsible for generating 1/f noise and has a small physical size that results in low parasitic capacitance of the device itself.

Abstract: A random number data generator includes a plurality of oscillation units and an AND circuit for outputting random number data produced in at least one oscillation unit when each of the entire oscillation units has oscillated a predetermined number of times, wherein high-reliability random number data can be generated efficiently.

Abstract: A device including an oscillator circuit having semiconducting logic elements and switching means for controlling warming and cooling of the circuit and, in that process, causing it to heat or cool in order to generate a random signal at the output of the logic elements. A plurality of devices are for continuously generating random signals, and control elements are for controlling in alternating manner the warming and cooling of the devices.

Abstract: A random number generator comprising an oscillator with an output signal dependant upon a random source, a sampling device to sample the output signal from the oscillator to obtain a sampled oscillator output, and a fixed frequency clock driven linear feedback shift register (LFSR) communicatively coupled to the sampling device via a digital gate to receive the sampled oscillator output, and to provide a random number at an output of the LFSR. Additionally, the random number generator may comprise an optional mixing function communicatively coupled to the LFSR to read the random number, and to insert the random number into an algorithm to obtain a robust random number.

Abstract: The invention relates to a method of generating a random-number sequence, and to a random-number generator, particularly for a chip card or a smart card.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The random number generator includes a first variable frequency oscillator, a second variable frequency oscillator, and frequency variation logic. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency. Bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The frequency variation logic is coupled to the second variable frequency oscillator. The frequency variation logic generates a noise signal that directs the second variable frequency oscillator to vary the second frequency.

Abstract: A random number generator includes a first oscillator that provides a first oscillatory signal to a processor, and a second oscillator that provides a signal to a frequency multiplier, which in turn provides a second oscillatory signal to the processor. The relative jitter between the two oscillatory signals contains a calculable amount of entropy that is extracted by the processor to produce a sequence of true random numbers.

Abstract: A digital true random number generator circuit, comprising a linear feedback shift register having an input and an output, a system clock having a system clock frequency value for driving the shift register, and a plurality of free running oscillators operatively connected to the input of the shift register. The oscillators and the system clock having different oscillation frequency values, the greatest common divisor of which having the value one, thereby avoiding locking of the oscillators and the system clock.

Abstract: According to one embodiment, a programmable random bit source is disclosed. The programmable random bit source includes a latch having a data input, a bias input and a clock input. In addition, the programmable random bit source includes a programmable voltage source coupled to the bias input of the latch and a first oscillator coupled to the data input of the latch to output a first oscillating signal. Further, the programmable random bit source includes a second oscillator coupled to the clock input of the latch circuit to output a second oscillating signal having a frequency slower than a frequency of the first oscillating signal.

Abstract: A chaos-generating loop includes a one dimensional mapping circuit (13) with non-linear input-output characteristics for generating chaos, a linear or non-linear AD converter (15) for converting an analog output of the one dimensional mapping circuit (13) to digital form, a sample-and-hold circuit (17) for holding and outputting the digitally converted value from the AD converter (15), in response to an external clock (C), and a linear or non-linear DA converter (19) for converting an output of the sample-and-hold circuit (17) to analog form and outputting this analog signal to the one dimensional mapping circuit (13), and a decoder for outputting a chaos stream in response to the output of the sample-and-hold circuit (17).

Abstract: A spreading code generator generates a spreading code specified by a matrix order and row number, which are matrix elements.

Abstract: A random number generator includes a noise signal generating device for supplying a noise signal, a sampling device connected between an output of the noise signal generating device and an output of the random number generator and sampling the noise signal in a sampling state and not sampling the noise signal in an idle state. The random number generator further includes a control oscillator for supplying a control alternating signal, the frequency of the control alternating signal of the control oscillator not being rigidly coupled to the frequency of the noise signal. The random number generator further includes an enabling device which puts the sampling device in the sampling state when the noise signal or the signal derived from the noise signal is in a first trigger state, and when, subsequently, the control alternating signal of the control oscillator is in a second trigger state.

Abstract: A random number generator on an integrated circuit has a first clock generator circuit with a first voltage supply for generating a first signal of a first frequency or of a first frequency range. A second clock generator circuit has a second voltage supply for generating a second signal of a second frequency or of a second frequency range, such that the second frequency or a mean value of the second frequency range is lower than the first frequency. A generator samples the first signal with the second signal and-generates at least one random number in dependence on the result of the sampling. The clock generator circuits are located as far away from one another as possible on the integrated circuit and/or the two voltage supplies are isolated from one another and/or at least one guard ring is placed around each of the clock generator circuits.

Abstract: A system for outputting pseudorandom noise sequences comprises a plurality of output apparatuses.

Abstract: A random number data generator includes a plurality of oscillation units and an AND circuit for outputting random number data produced in at least one oscillation unit when each of the entire oscillation units has oscillated a predetermined number of times, wherein high-reliability random number data can be generated efficiently.

Abstract: A random number generator is disclosed that uses the meta-stable behavior of flip-flops. The output of the flip-flop is compared to an input waveform to determine if the output signal does not match the input signal, indicating a meta-stable state. When a meta-stable event is detected an output bit is provided as a random bit. In one variation, an even random number distribution is obtained by “marking” half of the zeroes as “ones” and the other half of the zeroes as “zeroes” and half of the ones as “ones” and the other half of the ones as “zeroes.” In further variations, the (i) delay between the clock and the input are varied to cause the meta-stable behavior more often and (ii) multiple circuits with n different flip-flops are utilized so that at least one of the n circuits will be meta-stable at a given time.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The random number generator includes a first variable frequency oscillator, a second variable frequency oscillator, and frequency variation logic. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency. Bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The frequency variation logic is coupled to the second variable frequency oscillator. The frequency variation logic generates a noise signal that directs the second variable frequency oscillator to vary the second frequency.

Abstract: A random number generating system and its method for generating very irregular random numbers without an increase of a consumed current and an expansion of a chip in size, comprising a random number generator 202 for generating random numbers and a signal line 201 for transmitting data to functional blocks arranged outside the random number generator 202, wherein the random number generator 202 has a first shift register 203, a second shift register 204, and a logic device 205 for executing a logical operation between an output from the first shift register 203 and data transmitted through the signal line 201 and then inputting a result of the operation to the second shift register 204 and generates random numbers by using a data value transmitted to the functional block arranged outside the random number generator 202.

Abstract: A random number generator includes a first oscillator that provides a first oscillatory signal to a processor, and a second oscillator that provides a signal to a frequency multiplier, which in turn provides a second oscillatory signal to the processor. The relative jitter between the two oscillatory signals contains a calculable amount of entropy that is extracted by the processor to produce a sequence of true random numbers.

Abstract: Random pulse generators and generating systems using at least three oscillators. The output signals of at least two of the oscillators are combined to disturb the output signal of a final oscillator. For one configuration, combined output signals of at least two phase shift oscillators are used to modify the feedback signal of a final phase shift oscillator, thus disturbing the output signal of the final oscillator. For another configuration, the output signals of at least two phase shift oscillators are used to drive a subtractor whose output signal is combined with the output signal of a final phase shift oscillator to drive a subsequent subtractor, thus disturbing the output signal of the final oscillator.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The apparatus has a first variable frequency oscillator, a second variable frequency oscillator, and a variable bias generator. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The a second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency, where bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The variable bias generator is coupled to the first and second variable frequency oscillators, and generates an analog bias signal. The first and second frequencies vary according to the analog bias signal, and the analog bias signal varies based upon logic states of a plurality of bits of the random number.

Abstract: An improved random number generator for micro-controllers is provided with multiple free running oscillators. These oscillators may be ring oscillators. They run at different frequencies. A phase difference between at least two of the oscillators provides the random number. The determination of a phase difference can be done by sampling the high speed oscillator using the lower speed oscillator. This sampling of the oscillators for the determination of a phase difference can be controlled by an oscillators as well. The random number is picked up from a shift register which provides feedback to a control circuit which can alter the frequency of one or more (including all) of the oscillators so that an increased randomness can be achieved. The random number from the shift register is loaded into a linear feedback shift register (LFSR) to generate independent uniform random data.