Abstract: A transmission control protocol (TCP) session processing architecture for conducting numerous TCP sessions during testing of a network-under-test: multiple processor cores running, allocated to TCP session handling, and program instructions configured to distribute processing of each TCP session across multiple cores with a first set of cores allocated to handle TCP control, a second set of cores allocated to handle TCP packet transmission, and a third set of cores allocated to handle TCP packet receiving. The TCP session processing architecture also includes a shared memory accessible to the first, second and third sets of cores, that holds PCBs for each of numerous TCP sessions during the testing with update access controlled by an atomic spinlock processor instruction that each TCP state machine running on a core must engage to secure the update access to a respective PCB, in order to proceed with state processing of its respective TCP session.

Abstract: An embodiment may involve determining that a first logical partition of a scratchpad memory coupled to a processor core is empty and a first application is scheduled to execute; instructing a direct memory access (DMA) engine to load the first application into the first logical partition and then instructing the processor core to execute the first application from the first logical partition; while the first application is being executed from the first logical partition, determining that a second logical partition of the scratchpad memory is empty and a second application is scheduled to execute; instructing the DMA engine to load the second application into the second logical partition; determining that execution of the first application has completed; and instructing the DMA engine to unload the first application from the first logical partition and instructing the processor core to execute the second application from the second logical partition.

Abstract: In adjustment processing executed at the same period as waveform analysis processing, a CPU of a microcomputer permits an execution of the waveform analysis processing on condition that the waveform analysis processing has been completed. Thus a period of non-execution of the waveform analysis processing is ensured between a completion of preceding waveform analysis processing to an execution of next waveform analysis processing. Since low priority processing, which has been disabled to be executed, is enabled to be executed, it is possible to stop continuation of disablement of execution of the low priority processing.

Abstract: The present invention provides a scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system. The PCIe switch is utilized for handling input/output requests of a host of the electronic system. The scheduling method includes the PCIe switch determining a scheduling sequence of message signal interrupts (MSIs) and read/write requests corresponding to the input/output requests according to amount of the message signal interrupts corresponding to the input/output requests; and the PCIe switch handling the message signal interrupts and the read/write requests according to the scheduling sequence.

Abstract: Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.

Abstract: A system, method, and computer program product are provided for a memory device system. One or more memory dies and at least one logic die are disposed in a package and communicatively coupled. The logic die comprises a processing device configurable to manage virtual memory and operate in an operating mode. The operating mode is selected from a set of operating modes comprising a slave operating mode and a host operating mode.

Abstract: Techniques for behavioral pairing in a task assignment system are disclosed. In one particular embodiment, the techniques may be realized as a method for behavioral pairing in a task assignment system comprising: determining, by at least one computer processor communicatively coupled to and configured to operate in the task assignment system, a priority for each of a plurality of tasks; determining, by the at least one computer processor, an agent available for assignment to any of the plurality of tasks; and assigning, by the at least one computer processor, a first task of the plurality of tasks to the agent using a task assignment strategy, wherein the first task has a lower-priority than a second task of the plurality of tasks.

Abstract: Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading by a quality of service management (QM) circuit, respective first data rate metrics and respective latency metrics from requester circuits while the requester circuits are actively transmitting memory transactions to a memory controller. The QM circuit periodically reads a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines, while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: Provided are systems, methods, and computer-readable medium for enabling sharing of a multi-channel packet processor by multiple processes executing on a network device. The network device can include a memory management unit, configured to include an address map. The address map can include a reserved portion. The virtual machine can allocate a guest portion in the address map, where the guest portion is allocated in a part of the address map that does not include the reserved portion. A first channel from the packet processor can be assigned to the guest portion, and the virtual machine can use the first channel to receive packets. The reserved portion can be assigned to a host process executing on the network device. A second channel from the packet processor can be assigned to the reserved portion. The host process can transmit packets to the network using the second channel.

Abstract: A method for encrypting data with an encryption entity includes, in a step a), dividing a plaintext into a number of N blocks. In a step b), each of the blocks are encrypted with an encryption key resulting in a number of ciphertext blocks. In a step c), a linear All-Or-Nothing scheme is applied on the ciphertext blocks. In a step d), each of the ciphertext blocks output from step c) is transformed with a transformation procedure such that the information in different ciphertext blocks is transformed differently based on the encryption key and such that the transformation procedure is only revertable with knowledge of the encryption key. In a step e), the transformed ciphertext blocks are dispersed according to an information dispersal procedure.

Abstract: A method for wireless communication within a building automation system is disclosed. The method includes establishing a communications link between a first automation component and a second automation component, detecting a change in the communications link at the second automation component, and initiating a reset function on the second automation component in response to the detected change in the communications link. A building automation system is further disclosed. The system includes a first automation component, a second automation component in communication with the first automation component via a communication link. The second automation component further includes a reset function stored on a memory and executable by a processor in communication with the memory, such that the reset function is activated in response to a change in the communications link.

Abstract: A novel method of providing a locking mechanism which supports multiple operations rights is disclosed. The locking mechanism includes a policy aspect which defines which operations are allowed to access the common resource concurrently. The locking mechanism also includes the ability to allow predetermined number of tasks to access the common resource simultaneously. Furthermore, additional operations can be easily and quickly added to the mechanism.

Abstract: Managing execution of computer operations by determining that a computer resource targeted by a command's first operation is available, in a candidate processing record in a processing records schedule, to receive an instruction to perform the first operation, determining that a computer resource targeted by the command's second operation is available, in a processing record in the schedule at a processing offset relative to the candidate record, to receive an instruction to perform the second operation, the processing offset being an expected processing latency associated with the command, scheduling the computer resource targeted by the first operation to receive the instruction to perform the first operation when processing the candidate record in the schedule, and scheduling the computer resource targeted by the second operation to receive the instruction to perform the second operation when processing the processing record in the schedule at the processing offset relative to the candidate record.

Abstract: A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

Abstract: Apparatus and methods of reducing clock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. The clock control circuit includes a command/address domain configured to selectively provide a command/address clock signal based, at least in part, on a chip select signal. The clock control circuit further includes a command domain circuit configured to selectively provide a command clock signal based, at least in part, on the chip select signal. The clock control circuit further includes a column latency domain circuit configured to selectively provide a column latency clock signal based, at least in part, on a memory command. The clock control circuit further includes a four phase domain circuit configured to selectively provide a four phase clock signal based, at least in part on the memory command.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing tests on mobile devices. In one aspect, a power distribution system includes a set of mobile devices and a computer that manages the execution of a test using the set of mobile devices. The computer can include one or more data communication ports. The system can also include one or more Universal Serial Bus (USB) hubs connected to the mobile devices using USB cables. Each mobile device can be connected to one of the one or more USB hubs. The system can also include one or more USB charging hubs connected between each data communication port of the computer and at least one of the one or more USB hubs. The system can also include a power supply connected between a power source and each of the one or more USB hubs.

Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources.

Abstract: The present disclosure relates to systems and computer-implemented methods for implementing a resource allocation and adjusting resource usage and spending based on information received from a plurality of network-connected devices. One example method is performed by identifying a master resource allocation associated with a plurality of connected devices and monitoring, at a device hub, resource usage information associated with at least one connected device. The device hub compares the monitored resource usage information associated with the at least one connected device to the master resource allocation for the plurality of connected devices, and, in response to the comparison, calculates at least one adjustment in operation for a particular connected device from the plurality of connected devices based on the monitored resource usage information.

Abstract: A UE is configured to function as a relay on behalf of a donor access node. The donor access node can dynamically adjust scheduling of resources to the relay UE based on a size of a buffer associated with the relay UE. The donor access node monitors a size of the buffer and, if the size exceeds a threshold, assigns a greater scheduling weight to the relay UE. Similarly, when the buffer size associated with the relay UE drops below a threshold, the scheduling weight may be lowered. The buffer may include any combination of a downlink buffer stored on the donor access node or an uplink buffer stored on the relay UE.

Abstract: Managing a distributed system. Embodiments may allow for a quorum to dynamically change the quorum vote. One example is illustrated in a method. The method includes determining a change to a voter's level of participation in a cluster. A quorum of voters changes the voter's voting privileges, based on the change in the voter's level of participation.

Abstract: A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

Abstract: An onboard apparatus comprising a connection portion, a control block, and a bus switch is provided. The connection portion connects with an external device mounted to a vehicle, and includes at least a data terminal to input and output a communication data and a control terminal to output a communication availability signal that indicates communication is available or not. The control block performs data communication with the external device, which is connected to the connection portion. The bus switch, according to a permission signal, changes a non-conduction state to a conduction state of a transmission path from the control block to the data terminal. A signal level of the permission signal varies when an output of the control block is stabilized after the onboard apparatus starts.

Abstract: In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.

Abstract: A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

Abstract: According to an embodiment, a data transfer control apparatus has a band measurement unit and a request mask unit. The band measurement unit measures a band level to transfer data, and compares this measurement band level with a target band level. The request mask unit outputs a correction request signal which is obtained by correcting a timing of a request signal sent from each of a plurality of processing units, based on a request mask control signal which the band measurement unit outputs.

Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources.

Abstract: The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

Abstract: A method of handling interrupts in a data processing system includes maintaining a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR. Whether a received interrupt is associated with the first IHR or the second IHR is determined. In response to the received interrupt being associated with the first IHR, event information associated with the received interrupt is stored in the first IDB. In response to the received interrupt being associated with the second IHR, the event information associated with the received interrupt in stored in the second IDB.

Abstract: A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.

Abstract: Migrating MMIO from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, MMIO mapping information, wherein the hypervisor supports operation of a logical partition executing and the logical partition is configured for MMIO operations with the source I/O adapter through a MMU of the computing system utilizing the MMIO mapping information; placing, by the hypervisor, the destination I/O adapter in an error state; configuring, by the hypervisor, the MMU for MMIO with the logical partition utilizing the MMIO mapping information collected by the hypervisor; and enabling the destination I/O adapter to recover from the error state.

Abstract: A method and apparatus for handling in-device co-existence interference in a user equipment are provided. In an exemplary method, a Long Term Evolution (LTE) activity scheduled to be performed during an inactive time period of an LTE module in a user equipment is determined. It is determined whether the LTE module is to be allowed to perform the LTE activity during the inactive time period. If the LTE activity is to be allowed, then the LTE module is allowed to perform the LTE activity during the inactive time period. Otherwise, the LTE module is not allowed to perform the LTE activity during the inactive time period to provide interference free time for an Industrial, Scientific and Medical (ISM) module in the user equipment. Moreover, the disallowed LTE activity is scheduled to be performed during an active time period following the inactive time period.

Abstract: A half-graphical user interface (Half-GUI) order processing (HGOP) system with single sign on and its method of use is described. A set of web services may be utilized for order processing in an electronic commerce system which allows a merchant to host a product catalog and shopping cart, but post the transaction to an e-commerce system in one simple transaction. In response to a shopping cart request and utilizing single sign on technology, the HGOP system exposes a single checkout form, prepopulated with customer account information to a merchant web site. If no edits are required, the transaction posts and an order confirmation/thank you page is displayed. If edits are required or a new customer account is required, the customer's account is updated or created.

Abstract: A bus access arbiter includes an access mode judgment unit and a round robin arbitration unit. The access mode judgment unit judges, when bus access is generated from a plurality of masters M0 and M1, whether an access mode of each of the masters that are connected is a sequential access mode or a single access mode. The round robin arbitration unit dynamically switches an access arbitration method for arbitrating the bus access according to the access mode. The access mode judgment unit includes an access interval count unit, a sequential access number count unit, and an access mode state register that stores a state of the judged access mode for each of the masters, and updates the state of the access mode based on an access interval and the number of sequential access.

Abstract: An apparatus in which at least two pieces of software capable of controlling a device may be installed, each of the pieces of software capable of controlling a device, the apparatus including a setting unit provided by a first piece of software, the setting unit being capable of controlling the device, and a determining unit configured to determine whether the device is to be controlled by a second piece of software that is different from the first piece of software. In this case, if the determining unit determines that the device is to be controlled by the second piece of software, at least partial control of the device is suppressed on a setting screen of the setting unit.

Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for providing a customized representation of a business process involving one or more organizational entities that are accessible through a network. A user interface that can display a customized representation of a business process is provided. User information, including user privileges associated with the business process, is stored in a central repository that is accessible through the network. A request to view the business process is received from a first user through the user interface. The user privileges for the first user are retrieved from the central repository. A customized representation of the business process is displayed with the user interface. The customized representation is in compliance with the retrieved user privileges for the first user.

Abstract: Some of the embodiments of the present disclosure provide a system comprising: a shared memory unit and an arbiter that is configured to generate a clock signal, receive information regarding bandwidths of each of a plurality of agents, and determine a clock frequency or a sequence for selecting single agents among the plurality of agents to allow the single agents to transfer data in parallel from/to the shared memory unit in a single clock cycle of the clock signal, wherein the sequence is based, at least in part, on the bandwidths for each of a plurality of agents. The arbiter is also configured to cycle through the determined sequence for selecting the single agents among the plurality of agents to allow the single agents to transfer data from/to the shared memory unit in the single clock cycles.

Abstract: A dispatcher stack is allocated to each of a plurality of processors sharing a run queue. Each processor, in process dispatch processing, saves in a switch-source process stack the context of a switch-source process (the process being run), saves in the dispatcher stack of each of the processors a dispatcher context, inserts the switch-source process into the run queue, removes a switch-destination process from the run queue, and, in addition, restores the context of the switch-destination process from the switch-destination process stack.

Abstract: A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.

Abstract: A device, of a cloud computing environment, receives information associated with one or more computing resources of a local portion of the cloud computing environment, and receives, from a global allocator device, a request for placement of a computing resource element at a selected computing resource of the one or more computing resources. The device also determines, based on the information, whether the request can be satisfied by the selected computing resource, and places the requested computing resource element in the selected computing resource when the request can be satisfied by the selected computing resource. The device sends, to the global allocator device, a message indicating that the requested computing resource element has been successfully placed in the selected computing resource.

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources.

Abstract: Described are techniques for processing a request to update a globally shared data item. The request is received at a first processor designated as the master processor. Other processors are designated as non-master processors. The first processor sends a synchronization request message to the other processors. The first processor waits a predetermined amount of time for the other processors to signal to the first processor regarding commitment in executing the request. Responsive to the first processor receiving the signal from the other processors first processing is performed that includes the first processor notifying the other processors regarding completion of a first synchronization point, updating the globally shared data item by said first processor, and waiting, by the other processors, for notification from the first processor regarding completion of a second synchronization point thereby indicating that updating of the globally shared data item is completed.

Abstract: A method and a device are disclosed for a cache memory refill control.

Abstract: Systems and methods of protecting a shared resource in a multi-threaded execution environment in which threads are permitted to transfer control between different software components, for any of which a disclaimable lock having a plurality of orderable locks can be identified. Back out activity can be tracked among a plurality of threads with respect to the disclaimable lock and the shared resource, and reclamation activity among the plurality of threads may be ordered with respect to the disclaimable lock and the shared resource.

Abstract: Cooperative interaction of a message processor and an intermediation processor. The message processor processes messages received from a network and to be sent over a network. The intermediation processor intermediates between the message processor and the network using a shared memory that includes a memory portion that is within the address space of the message processor. The message processor writes messages into the memory portion over a physical channel and reads message from the memory portion over the physical channel. The intermediation processor provides messages received from a network into the memory portion so that the received messages can be read by the message processor over the physical channel. The intermediation processor dispatches messages written to the memory portion by the message processor over the network.

Abstract: Various embodiments for troubleshooting a network device in a computing storage environment by a processor. In response to an error in a specific port, an alternative error recovery operation is initiated on the port by performing at least one of initiating a silent recovery operation by reloading a failed instruction, taking the port offline, cleaning up any active transactions associated with the port, performing a hardware reset operation port, and bringing the port online.