Abstract: An apparatus for controlling access to a resource includes a shared pipeline configured to communicate with the resource, a plurality of command queues configured to form instructions for the shared pipeline and an arbiter coupled between the shared pipeline and the plurality of command queues configured to grant access to the shared pipeline to a one of the plurality of command queues based on a first priority scheme in a first operating mode. The apparatus also includes interface logic coupled to the arbiter and configured to determine that contention for access to the resource exists among the plurality of command queues and to cause the arbiter to grant access to the shared pipeline based on a second priority scheme in second operating mode.

Abstract: A method and system for sharing access to a storage device. Two processing devices are connected to a storage device interface. The processing devices are interconnected to allow communication with regard to access to the storage device interface. Access to the storage device interface is controlled by the first and second processing devices exchanging signals. Embodiments of the invention may be a mobile device configured to play audio files from a memory card connected to the mobile device. A communications link may be established to a remote device for the transfer of data between devices.

Abstract: Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.

Abstract: This document describes techniques (300, 600) and apparatuses (102, 106, 700, 800, 900) for peripheral authentication. These techniques (300, 600) and apparatuses (102, 106, 700, 800, 900) may configure data lines for authentication between host device (102) and peripheral (106), use these configured data lines to authenticate the peripheral (106), and then reconfigure the data lines for use. These techniques (300, 600) may also or instead transmit time stamps to a remote entity (402) for tracking peripheral use and/or present home screens (122) responsive to connection to a peripheral (106).

Abstract: An apparatus comprising a first sub-arbiter circuit and a second sub-arbiter circuit. The first sub-arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. The second sub-arbiter circuit may be configured to determine a winning channel received from the plurality of channel requests based on a second criteria. The second sub-arbiter may also be configured to optimize the order of the winning channels from the first sub-arbiter by overriding the first sub-arbiter if the second criteria creates a more efficient data transfer.

Abstract: In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed.

Abstract: A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Abstract: Arbitrating access to industrial resources as a function of controller identify is provided herein. For example, a unique identifier can be associated with a control module that can distinguish the module from other components of a system. Upon receiving a request to control a resource, the identifier of the requesting module can be associated with that resource. In a case of multiple requests, an arbitrated ID can be chosen and added to an owner queue. The chosen ID is then published and, if the published identifier matches the module identifier, the module can assume control of the resource; if not, the module's request is placed into a request queue for further arbitration. The subject innovation provides for generally applicable arbitration that can reduce redundant code crafted for each module of a system, greatly reducing overhead costs associated with such redundancy.

Abstract: Preventing time out of an IO transaction during CPU re-initialization by controlling the IO transaction so that the time when the IO transaction is continuously stopped during the CPU re-initialization process is within a predetermined time that prevents complete time out of an interrupt of an IO transaction. In a case where the IO transaction would be continuously stopped for greater than the predetermined time during a CPU re-initialization the IO transaction is stopped and restarted within the predetermined time. The status of the interrupt during such stopping and starting is stored so as not to loose the interrupt status during the interval between such stopping and starting.

Abstract: In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.

Abstract: Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A multi-core LSI with improved stability of operation. The multi-core LSI includes a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus for arbitrating access to the module(s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from a module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.

Abstract: A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a set of input ports. Responsive to the first predetermined time period expiring before the processor determines whether the random priority-based arbiter is blocking, a determination is made as to whether the random priority-based arbiter is blocking one of the set of output ports or the set of input ports within a second predetermined time period using the random seed and at least one of property strengthening or underapproximation. Responsive to the processor determining that the random priority-based arbiter satisfies a non-blocking specification such that not one of the set of output ports or the set of input ports is blocked within the second predetermined time period, the random priority-based arbiter is validated as satisfying the non-blocking specification.

Abstract: A method includes receiving a first interrupt request from a first device instance of a plurality of device instances. The first interrupt request is requesting an interrupt of a processor. The method also includes updating a bit vector based on the first interrupt request. The bit vector comprises a plurality of bits representing an accumulation of interrupt requests. The method further includes generating a gang interrupt comprising the updated bit vector. The method also includes transmitting the gang interrupt to call a first device driver associated with the first interrupt request based on the bits in the bit vector.

Abstract: A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters.

Abstract: A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.

Abstract: A multi-core processor system includes multiple cores; shared memory accessed by the cores; and an arbiter circuit that arbitrates contention of right to access the shared memory by the cores. Each of the cores is configured to acquire for the core, a measured speed of access to the shared memory; calculate for the core, a response performance based on the measured speed of access and a theoretical speed of access for the core; calculate for the cores and based on the response performance calculated for each of the cores, ratios of access rights to access the shared memory, the ratios being calculated such that a ratio of access rights for a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and notify the arbiter circuit of the calculated ratios of access rights.

Abstract: An apparatus and method implemented in hardware and embedded software that improves performance, scalability, reliability, and affordability of Storage Area Network (SAN) systems or subsystems. The apparatus contains host computers (application servers, file servers, computer cluster systems, or desktop workstations), SAN controllers connected via a bus or network interconnect, disk drive enclosures with controllers connected via network interconnect, and physical drive pool or cluster of other data storage devices that share I/O traffic, providing distributed high performance centrally managed storage solution. This approach eliminates I/O bottlenecks and improves scalability and performance over the existing SAN architectures.

Abstract: A method of operating a resource lock for controlling access to a resource by a plurality of resource requesters, the resource lock operating in a contention efficient (heavyweight) operating mode, and the method being responsive to a request from a resource requester to acquire the resource lock, the method comprising the steps of: incrementing a count of a total number of acquisitions of the resource lock in the contention efficient operating mode; in response to a determination that access to the resource is not contended by more than one resource requester, performing the steps of: a) incrementing a count of a number of uncontended acquisitions of the resource lock in the contention efficient operating mode; b) calculating a contention rate as the number of uncontended acquisitions in the contention efficient operating mode divided by the total number of acquisitions in the contention efficient operating mode; and c) in response to a determination that the contention rate meets a threshold contention rate

Abstract: A method for handling an interrupt during testing of at least one logic block of a processor includes performing a test on at least one logic block of a processor; during the performing, receiving an interrupt; determining a progress status of the test in response to receiving the interrupt; and determining when the processor responds to an interrupt, wherein the determining when the processor responds to an interrupt is based on the progress of the test.

Abstract: The disclosure recites a device, system and method for provisioning resources from a server in a network to a mobile electronic device. The method comprises at the mobile electronic device: generating and sending a network registration request to the server to allow the server to determine whether the mobile electronic device is in a device registry linking resources managed by the server; waiting for a data transmission from the server, the data transmission containing text and a link to the resource that can receive the data transmission at the mobile electronic device; incorporating text and a link from the data transmission into a graphical user interface (GUI) generated on a display of the mobile electronic device to provide an interface to activate the link from the mobile electronic device; and generating an indicator on the GUI that the resource is new, if the resource is new to the mobile electronic device.

Abstract: The invention pertains to a method for determining a sequence of access (300) to a communications network (100) by a plurality of nodes (101, 102, 103, 5 104, 107) of said communications network (100) in the context of the broadcasting of a data content by a transmitter node (101) to a set of receiver nodes (103, 107, 104, 102), at least one receiver node (102, 104) having to receive said content by means of another receiver node (103, 107), called a relay receiver node.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: Hardware resources sharing for a computer system running software tasks. A controller stores records including a mutex ID tag and a waiter flag in a cache. Lock and unlock registers are readable by the controller and loadable by the tasks with a mutex ID specifying a hardware resource. The controller monitors whether the lock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it sets the record's waiter flag. If not, it adds a record having a tag corresponding with the mutex ID. The controller also monitors whether the unlock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it determines whether that record's waiter flag is set and, if so, it clears that record from the cache.

Abstract: The present specification describes techniques and apparatus that enable synchronization using agent-based semaphores. In one or more implementations, a semaphore is used for a first agent to notify a second agent that the first agent has completed a particular task of a set of tasks and has completed using a shared resource for the particular task.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Abstract: Method and apparatus for enabling continuous validation of a data structure by acquiring a first read lock for the data structure and processing the data structure under the first read lock. When the first read lock is relinquished and subsequently reacquired, the method provides for determining if a write lock was granted prior to reacquiring the first read lock. The data structure is further processed when a write lock was not granted and is revalidated when a write lock was granted.

Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes a storage for storing a resource discovery table, and programmed I/O (PIO) configuration registers corresponding to hardware resources. A system processor may allocate the plurality of hardware resources to one or more functions, and to populate each entry of the resource discovery table for each function. The processing units may execute one or more processes. Given processing units may further execute OS instructions to allocate space for an I/O mapping of a PIO configuration space in a system memory, and to assign a function to a respective process. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

Abstract: A communication system including a resource and an arbiter. The resource is shared among a plurality of requestors such that, at any given time, only one of the plurality of requestors has access to the resource. The arbiter is configured to receive a request from each of the plurality of requestors to access the resource, in which each request has a priority level associated with the request. The arbiter is further configured to age each request at a different rate relative to that associated with another request, and grant each requestor access to the resource based on i) the priority level and/or ii) the age of the request corresponding to the requestor.

Abstract: Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.

Abstract: In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle.

Abstract: Method, apparatus and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.

Abstract: A virtual computer system has a plurality of computers for executing a program and a storage system connected to the computers via a network. A virtualization mechanism in a first computer of the plurality of computers generates at least one virtual computer on the first computer. The virtualization mechanism in the first computer executes at least one of a first judgment and a second judgment when a request for activating a first virtual computer of the at least one virtual computer is received, the first judgment being for judging whether or not the activation of the first virtual computer is prohibited based on first information stored in a memory of the virtualization mechanism, and the second judgment being for judging whether or not an identifier included in a logic I/O adapter device assigned to the first virtual computer is invalid based on second information stored in the memory of the virtualization mechanism.

Abstract: A browser-enabled device includes a browser-based user interface and control architecture, which has a browser core, a browser framework, and a user interface. The user interface is written using a markup language. In processing event registrations, the browser framework receives an event registration. The received event registration having a response unique resource identifier (URI) content and a priority field. The priority field of the received event registration is examined to determine priority of the received event registration. If the browser core is loading the response URI content of a prior event registration and if the priority of the received event registration is higher than the priority of the prior event registration, then the loading of the response URI content of the prior event registration is halted, and loading of the response URI content of the received event registration is begun.

Abstract: The disclosure recites a system and method for updating a resource to an electronic device. The system comprises: a resource providing information for the device; a server to maintain the resource; a communication link providing the device with access to the resource; a data transmission module for extracting and transmitting access information about the resource to the device; and a data processing module for processing the received information at the device. In the device, a GUI provides information on a topic retrieved from local storage on the device and additional information about the resource is incorporated into the GUI for that topic.

Abstract: An apparatus for performing arbitration increases the fairness of arbitrations, decreases system latency, increases system throughput, and is suitable for use in more complex systems. According to an exemplary embodiment, the apparatus includes a generator for generating a plurality of arbitration numbers corresponding to a plurality of agents, and circuitry for selecting one of the agents to access a resource shared by the agents based on the arbitration numbers. At least one of the arbitration numbers includes a plurality of fields corresponding to a plurality of parameters.

Abstract: A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the data processing system. The utilization slack value is determined using one or more active core count values and one or more slack core count values. The control system computes a new utilization metric to be a difference between a full utilization value and the utilization slack value. The control system determines whether the new utilization metric is below a predetermined utilization threshold. Responsive to the new utilization metric being below the predetermined utilization threshold, the control system decreases a frequency of the plurality of processors.

Abstract: A data storage device may include multiple memory chips and a controller that is operably coupled to the memory chips and that is arranged and configured to receive a group of commands from a host, where each of the commands in the group includes a same group number to identify the commands as part of the group, process the group of the commands using the memory chips and generate and send a single interrupt to the host when the group of the commands completes processing.

Abstract: A method for efficiently handling interrupts in a virtual technology environment with integrity services is provided. The method comprises assigning an interrupt to a virtual machine that is running a software agent; suspending the software agent; invoking a protected interrupt handler; copying the interrupt's memory content to a protected location, in response to successfully verifying the integrity of the content; replacing the interrupt's return address with a return address for a protected function; switching from the software agent's protected context to its active context; executing the original interrupt handler; returning control to the protected function to ensure that execution of the software agent resumes safely; switching back to the software agent's protected context, in response to successfully verifying the integrity of the content; and passing control back to the software agent to resume execution.

Abstract: A wireless network device including an antenna, a first communication module, and a second communication module. The first communication module is configured to transmit or receive packets of data in accordance with a first communication standard, and the second communication module is configured to transmit or receive packets of data in accordance with a second communication standard. The wireless network device further includes an arbitration module configured to grant access of each of the first communication module and the second communication module to the antenna so that the first communication module and the second communication module can respectively transmit or receive data packets in accordance with the first communication protocol and the second communication protocol.

Abstract: Methods, apparatus, and computer-readable media for management and arbitration of dedicated mobile communication resources for mobile applications are provided. Mobile applications can be given a priority level that establishes an importance with respect to one or more other mobile applications and at least one mobile resource. If competing applications attempt to access the mobile resource concurrently, access can be provided to an application having higher priority level. Furthermore, control of a resource can be taken away from an application having lower priority in order to affect control of such resource for a higher priority application. In one aspect, a privilege code of an application can be verified prior to establishing control of the resource for the application, to mitigate a likelihood of inappropriate transfer of resources.

Abstract: Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.

Abstract: A method for managing states by a Media Access Control (MAC) layer in a wireless network is disclosed. The method includes determining next occurable physical interrupts for each of the states; configuring a link of the states according to the determination result; transitioning to a state to be linked next if a physical interrupt occurs in each state; and transitioning to an initial state if an timer interrupt occurs in each state. The MAC layer transitions to the initial state if a physical interrupt occurs in a last state among the linked states. The physical interrupt occurs in association with a physical event, and the timer interrupt occurs in association with a timer event.

Abstract: Embodiments operating shared peripherals in a hybrid computing system are described. Embodiments control a shared wireless antenna variously between a primary system and a secondary system, where the secondary system is detachable from the primary system and operates as an independent computing device in the disconnected state, while operating as a display device in the connected state.

Abstract: The disclosure provides a system and method of provisioning a resource to an electronic device. The method comprises: after a triggering event, receiving from a network a data transmission at the device, the data transmission containing access information relating to a resource in a library that is in a remote server from the device, the resource relating to an application operating on the device; extracting the access information from the data transmission at the device; presenting the access information for the resource in a graphical user interface (GUI) on a display of the device; and after a selection event is initiated on the device for the resource, initiating a second data transmission containing a copy of the resource to the device and integrating the resource into the application as an output generated by the application.

Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.

Abstract: A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.

Abstract: State of the art processor systems, esp. in embedded systems, are not able to process data under real-time conditions especially with throughput rates near 10 Gbps. So, when using interfaces like PCI Express (PCIe) or Infiniband or 10 G-Ethernet for 10 Gbps data throughput, special data-paths have to process the high throughput rate data. But tasks like connection management or time uncritical control messaging are better manageable by a processor. According to the invention it is proposed a kind of multiplexer architecture that is needed to split between control and data-path access for a PCI Express based architecture.

Abstract: A multiprocessor server system executes a plurality of multiprocessor or single-processor operating systems each using a plurality of storage adapters and a plurality of network adapters. Each operating system maintains load information about all its processors and shares the information with other operating systems. Upon changes in the processor load of the operating systems, processors are dynamically reassigned among operating systems to improve performance if the maximum load of the storage adapters and network adapters of the reassignment target operating system is not already reached. Processor reassignment includes shutting down and restarting dynamically operating systems to allow the reassignment of the processors used by single-processor operating systems. Furthermore, the process scheduler of multi-processor operating systems keeps some processors idle under light processor load conditions in order to allow the immediate reassignment of processors to heavily loaded operating systems.