Access Arbitrating Patents (Class 710/240)
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Patent number: 9430808Abstract: Techniques for synchronization points for state information are described. In at least some embodiments, synchronization points are employed to propagate state information among different processing threads. A synchronization point, for example, can be employed to propagate state information among different independently-executing threads. Accordingly, in at least some embodiments, synchronization points serve as inter-thread communications among different independently-executing threads.Type: GrantFiled: June 19, 2013Date of Patent: August 30, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Christian Fortini, Brian E. Manthos, Grant A. Watters, Li-Hsin Huang, Richard K. James, Samuel R. Fortiner, R. Scott Briggs, Sergey Z. Malkin, Yuanzhe Wang, Rico Mariani, Justin E. Rogers, Anjali S. Parikh, Praveen Kumar Muralidhar Rao, Matthew P. Kotsenas, Jason J. Weber, Nirankush Panchbhai, Rossen Atanassov, Peter Salas
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Patent number: 9411753Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.Type: GrantFiled: September 22, 2015Date of Patent: August 9, 2016Assignee: MARVELL WORLD TRADE LTD.Inventors: Jun Zhu, Joseph Jun Cao, Tsung-Ju Yang, Ruoyang Lu
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Patent number: 9412455Abstract: According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.Type: GrantFiled: February 10, 2014Date of Patent: August 9, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Makiko Numata, Mitsunori Tadokoro, Norikazu Yoshida, Kohei Oikawa
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Patent number: 9390039Abstract: In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed.Type: GrantFiled: January 31, 2014Date of Patent: July 12, 2016Assignee: Intel CorporationInventor: Siaw Kang Lai
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Patent number: 9383396Abstract: A method for detecting a signal activity on a bus comprises measuring a current on the bus, and determining a signal activity based on the measured current.Type: GrantFiled: October 16, 2013Date of Patent: July 5, 2016Assignee: Sony CorporationInventors: Ben Eitel, Heimo Guth
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Patent number: 9355048Abstract: Apparatuses, systems, and methods are directed to securely store, transfer, and/or process data especially sensitive data sent from input devices to processors. In one embodiment, sensitive data may be packaged with at least one interrupt vector to provide a single posted write transaction initiated by an input device. The single posted write transaction may then be directly sent to a predetermined memory block allocated from a processor. In response to the single posted write transaction, a memory decoder associated with the processor may generate an emulated message signaled interrupt (MSI) signal to invoke an interrupt handler or an interrupt service routine (ISR) to service the emulated MSI using interrupt data, including the sensitive data, retrieved from the predetermined memory block. Once the sensitive data are processed by the processor, they may be removed from the processor before the processor exits the interrupt handler.Type: GrantFiled: March 28, 2012Date of Patent: May 31, 2016Assignee: INTEL CORPORATIONInventor: Yen Hsiang Chew
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Patent number: 9304924Abstract: Disclosed herein is a processing network element (NE) comprising at least one receiver configured to receive a plurality of memory request messages from a plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, and a plurality of response messages to the memory requests from the plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, at least one transmitter configured to transmit the memory requests and memory responses to the plurality of memory nodes, and a controller coupled to the receiver and the transmitter and configured to enforce ordering such that memory requests and memory responses designating the same memory location and the same source node/destination node pair are transmitted by the transmitter in the same order received by the receiver.Type: GrantFiled: August 2, 2013Date of Patent: April 5, 2016Assignee: Futurewei Technologies, Inc.Inventors: Iulin Lih, Chenghong He, Hongbo Shi, Naxin Zhang
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Patent number: 9298505Abstract: A time and space-deterministic task scheduling apparatus and method using a multi-dimensional scheme are disclosed. The time and space-deterministic task scheduling apparatus includes a preparation list generation unit and a task insertion unit. The preparation list generation unit generates a preparation list, including a preparation table having an array structure configured to have each bit formed of a binary number indicative of a priority of a task, and also including a preparation group cluster configured to include a plurality of preparation groups, each including bits corresponding to the respective binary numbers of the preparation table, and to have an upper and lower dimension relationship between the plurality of preparation groups. The task insertion unit performs bit masking on the preparation group cluster and the preparation table corresponding to a task P having a specific priority and thus inserts the task into the preparation group cluster and the preparation table.Type: GrantFiled: August 26, 2014Date of Patent: March 29, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Moon Haeng Cho, JongJin Won, CheolOh Kang, JeongSeok Lim
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Patent number: 9285801Abstract: A method for automatically creating a customized motion controller based on user input specifying desired characteristics of the motion controller. The method may compile the program into executable code and download the executable code to a target platform, thus enabling the target platform to function as the specified customized motion controller. User input may specify characteristics of the motion controller system such as: the target platform; the configuration of motors, sensors and I/O devices to be used; the supervisory control functions to be implemented; and the target language for the motion control program.Type: GrantFiled: September 14, 2005Date of Patent: March 15, 2016Assignee: National Instruments CorporationInventor: Sundeep Chandhoke
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Patent number: 9251022Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.Type: GrantFiled: March 1, 2013Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Ali Y. Duale, Dennis W. Wittig
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Patent number: 9229646Abstract: A environment and method are provided for increasing the storage capacity of a data storage environment. Additional storage clusters may be added to the storage environment without affecting the performance of each individual storage cluster. When data is written to the storage environment, a selection may be made as to which storage cluster is to store the data. When data is read from the storage environment, it may be determined which storage cluster stores the data and the data may be retrieved from that storage cluster.Type: GrantFiled: February 26, 2004Date of Patent: January 5, 2016Assignee: EMC CorporationInventors: Stephen Todd, Michael Kilian, Tom Teugels, Jan Van Riel, Carl D′Halluin, Christophe Bouhon
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Patent number: 9223581Abstract: A method for operating a system on chip includes receiving an acceleration request signal generated upon execution of an application program, in response to receipt of the acceleration request signal, comparing a current usage of a central processing unit (CPU) with a threshold value to generate a comparison signal, and performing switching between heterogeneous accelerators to accelerate a function executed by the application program in response to the comparison signal.Type: GrantFiled: August 30, 2012Date of Patent: December 29, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Boo-Jin Kim, Je Myoung Ko, Taek Kyun Shin
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Patent number: 9215087Abstract: Techniques for transmitting a packet from a source switch module to a destination switch module. Embodiments receive, at a first port of a first switch module, a packet that includes (i) path information specifying a route to the destination switch module, (ii) a set of load/store operations to be executed by the destination switch module and (iii) return path information specifying a route from the destination switch module to the source switch module. Upon determining that the first switch module is the destination switch module, the set of load/store operations are copied from the received packet into an execution buffer for automatic execution. Once the set of load/store operations are executed, embodiments transmit the packet to a second switch module using the first port on which the packet was received.Type: GrantFiled: March 15, 2013Date of Patent: December 15, 2015Assignee: International Business Machines CorporationInventors: William T. Flynn, Joseph A. Kirscht, Bruce M. Walk
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Patent number: 9189435Abstract: A method and apparatus for arbitration. In one embodiment, a point in a network includes first and second arbiters. Arbitration of transactions associated with an address within a first range are conducted in the first arbiter, while arbitration of transactions associated with an address within a second range are conducted in the second arbiter. Each transaction is one of a number of different transaction types having a respective priority level. A measurement circuit is coupled to receive information from the first and second arbiters each cycle indicating the type of transactions that won their respective arbitrations. The measurement circuit may update a number of credits associated with the types of winning transactions. The updated number of credits may be provided to both the first and second arbiters, and may be used as a basis for arbitration in the next cycle.Type: GrantFiled: April 23, 2013Date of Patent: November 17, 2015Assignee: Apple Inc.Inventors: Benjamin K. Dodge, Deniz Balkan, Gurjeet S. Saund, Munetoshi Fukami
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Patent number: 9189296Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.Type: GrantFiled: December 27, 2013Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Bahaa Fahim, Jeffrey Chamberlain, Yen-Cheng Liu
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Patent number: 9170903Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.Type: GrantFiled: September 30, 2014Date of Patent: October 27, 2015Assignee: International Business Machines CorporationInventors: Ali Y. Duale, Dennis W. Wittig
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Patent number: 9158547Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.Type: GrantFiled: April 29, 2014Date of Patent: October 13, 2015Assignee: Altera CorporationInventors: Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek, Larry D. Larsen
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Patent number: 9141429Abstract: A multicore processor system includes a core configured to detect a change in a state of assignment of a multicore processor; obtain, upon detecting the change in the state of assignment, number of accesses of a common resource shared by the multicore processor by each of process that are assigned to cores of the multicore processor; calculate an access ratio based on the obtained number of accesses; and notify an arbitration circuit of the calculated access ratio, the arbitration circuit arbitrating accesses of the common resource by the multicore processor.Type: GrantFiled: September 21, 2012Date of Patent: September 22, 2015Assignee: FUJITSU LIMITEDInventors: Hiromasa Yamauchi, Koichiro Yamashita, Kiyoshi Miyazaki, Hitoshi Ikeda
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Patent number: 9128891Abstract: The invention discloses a method of sharing a storage device and a mobile terminal. The mobile terminal comprises a first processor, a second processor and a readable and writable nonvolatile storage device. A processing capacity of the first processor is different from that of the second processor. A state in which the first processor is operating and using the storage device is a second state. A state in which the second processor is operating and using the storage device is a third state. The method comprising: the first processor receiving a switch instruction; the first processor controlling the storage device to enter the second state or the third state according to the switch instruction.Type: GrantFiled: March 10, 2010Date of Patent: September 8, 2015Assignee: LENOVO (BEIJING) CO., LTD.Inventors: Fuliang Zhang, Wenying Shan, Chunhui Sun, Jinmei Yang
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Patent number: 9104470Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.Type: GrantFiled: April 2, 2014Date of Patent: August 11, 2015Assignee: Renesas Electronics CorporationInventor: Naotaka Maruyama
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Patent number: 9092273Abstract: A multicore processor system includes a processor configured to detect any among a switching process and an assignment process of applications in a multicore processor; acquire upon detecting any among the switching process and the assignment process, a priority level concerning execution of each application assigned to each core of the multicore processor and number of accesses of a shared resource shared by the multicore processor; determine an access ratio of an application whose priority level is highest to each of application remaining after excluding the application whose priority level is highest, among the assigned applications, by comparing the number of accesses by each remaining application and the number of accesses by the application whose priority level is highest; notify an arbiter circuit of the determined access ratios; and arbitrate using the arbiter circuit, the access of the shared resource by the multicore processor, based on the access ratios.Type: GrantFiled: September 13, 2012Date of Patent: July 28, 2015Assignee: FUJITSU LIMITEDInventors: Koji Kurihara, Koichiro Yamashita, Kiyoshi Miyazaki, Hitoshi Ikeda
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Patent number: 9081630Abstract: A method includes receiving a request to access a resource; determining a presence of a memory buffer in a hardware-assisted memory pool; and determining a response to the request to access the resource based on the presence of the memory buffer. A system includes a plurality of processors, a resource, and a hardware-assisted memory pool including a memory buffer; one of the plurality of processors receives a request to access the resource, determines a presence of the memory buffer, and determines a response to the request to access the resource based on the presence of the memory buffer.Type: GrantFiled: December 12, 2012Date of Patent: July 14, 2015Assignee: WIND RIVER SYSTEMS, INC.Inventors: Markus Carlstedt, Kenneth Jonsson, Rikard Mendel
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Patent number: 9069614Abstract: A method is provided for using a temporary object handle. The method performed at a resource manager includes: receiving an open temporary handle request from an application for a resource object, wherein a temporary handle can by asynchronously invalidated by the resource manager at any time; and creating a handle control block at the resource manager for the object, including an indication that the handle is a temporary handle. The method then includes: responsive to receiving a request from an application to use a handle, which has been invalidated by the resource manager, sending a response to the application that the handle is invalidated.Type: GrantFiled: September 15, 2012Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Paul Cullen, Andrew Hickson, Gary Longerstaey, Stuart Reece
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Patent number: 9053521Abstract: An image processing apparatus is provided. The image processing apparatus for image signal processor (ISP) realization may include a Static Random Access Memory (SRAM) for each function module. A unified SRAM to store at least one line data of an input image for each of a plurality of functions modules within the image processing apparatus is further provided.Type: GrantFiled: December 22, 2010Date of Patent: June 9, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Sun Jeon, Ho Jin Lee, Joon Hyuk Cha, Shi Hwa Lee, Young Su Moon, Hyun Sang Park
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Patent number: 9037767Abstract: An arbiter configured to selectively grant access to a shared bus to a plurality of requestors. The arbiter includes a plurality of request shapers each configured to receive a request signal corresponding to a request, from a respective one of the plurality of requestors, to access the shared bus, a base priority signal indicating a base priority level of the respective one of the plurality of requestors, and a delta period signal indicating a counter value threshold. The counter value threshold corresponds to a threshold amount of time, and the counter value threshold is different for each of the plurality of requestors. Each of the plurality of request shapes is configured to separately output the request signal and a priority signal indicating a priority level of the request based on the base priority level, the counter value threshold, and a counter value.Type: GrantFiled: November 5, 2012Date of Patent: May 19, 2015Assignee: MARVELL INTERNATIONAL LTD.Inventor: Bhaskar Chowdhuri
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Patent number: 9015516Abstract: Example embodiments disclosed herein relate to storing event data and a time value in memory with an event logging module. Example embodiments of the event logging module include event command storage, clock command storage, and memory command storage.Type: GrantFiled: February 29, 2012Date of Patent: April 21, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventor: Ted A Hadley
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Patent number: 9003092Abstract: A bus system of a system on chip (SoC) includes a first and a second masters, a first slave, and a first and a second control modules. The control modules generates a first and a second access control state signals in response to a first locking access preparation request signal from a corresponding master. The access control signals are broadcasted between the first and the second control modules through a communication channel. A method of operating a bus system in a locked access mode includes allowing one of masters to access one of slaves through a control module and restricting other masters from accessing the one of slaves through other control modules connecting the other masters and the one of slaves in accordance with a control state signal.Type: GrantFiled: February 23, 2012Date of Patent: April 7, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-min Hong, Jae-geun Yun
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Patent number: 8990466Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.Type: GrantFiled: May 29, 2012Date of Patent: March 24, 2015Assignee: Infineon Technologies Austria AGInventor: Tommaso Bacigalupo
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Patent number: 8984194Abstract: The present invention discloses an arbitration mechanism for controlling access of a plurality of nodes external to a shared resource, to which accesses by the number of nodes must be restricted, is applicable to any shared source in a computer or computer-controlled system. The present design delivers the following advantageous features. It provides localized arbitration to obtain resource access and localized self-management of resource mastery; eliminates resource seizure locally; it allows equal access to the share resource, encapsulate all four above features with the same circuit/protocol.Type: GrantFiled: December 15, 2011Date of Patent: March 17, 2015Assignee: Numia Medical Technology LLCInventors: Duane E. Allen, James Jay Allen
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Patent number: 8977795Abstract: Systems, methods, and other embodiments associated with managing access to critical sections in a multithread processor are described. According to one embodiment, an apparatus includes a register configured to store i) respective resource identifiers that identify respective resources and ii) respective priorities for respective resource identifiers. The apparatus includes a managing module logic configured to receive a blocking instruction for a first resource having a first resource identifier that is associated with a first task, access the register to determine a priority associated with the first resource identifier, select one or more dependent resources based, at least in part on the priority associated with first resource identifier, and block the first resource and the dependent resources. In this manner the first task is granted access to the first resource and the dependent resources while other tasks are prevented from accessing the first resource and the dependent resources.Type: GrantFiled: October 23, 2012Date of Patent: March 10, 2015Assignee: Marvell International Ltd.Inventors: Olaf Mater, Sascha Schmeckenbecher
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Patent number: 8972989Abstract: A virtualization mechanism in a first computer of the plurality of computers generates at least one virtual computer on the first computer. The virtualization mechanism in the first computer executes at least one of a first judgment and a second judgment when a request for activating a first virtual computer of the at least one virtual computer is received, the first judgment being for judging whether or not the activation of the first virtual computer is prohibited based on first information stored in a memory of the virtualization mechanism, and the second judgment being for judging whether or not an identifier included in a logic I/O adapter device assigned to the first virtual computer is invalid based on second information stored in the memory of the virtualization mechanism. The activation of the first virtual computer is permitted or prohibited based on the executed judgment.Type: GrantFiled: August 8, 2012Date of Patent: March 3, 2015Assignee: Hitachi, Ltd.Inventors: Naoko Ikegaya, Tomoki Sekiguchi
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Patent number: 8959269Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: GrantFiled: February 18, 2014Date of Patent: February 17, 2015Assignee: Synopsys, Inc.Inventor: David Latta
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Patent number: 8954642Abstract: A signal transfer circuit comprising a control signal transfer unit configured to output an access request output signal and a memory address output signal to the arbiter after timings of the access request input signal of the access request and the memory address input signal input from the bus master have been adjusted, and output an access permission output signal, and a data signal transfer unit configured to output each data output signal to the corresponding bus master or the arbiter after a timing of each data input signal of the access request input from the arbiter or the bus master is adjusted, and output a data validity period output signal to the bus master after a timing of a data validity period input signal indicating a period in which each data is valid in the access request input from the arbiter is adjusted.Type: GrantFiled: November 12, 2012Date of Patent: February 10, 2015Assignee: Olympus CorporationInventors: Keisuke Nakazono, Masami Shimamura, Yoshinobu Tanaka, Akira Ueno
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Patent number: 8930603Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.Type: GrantFiled: November 8, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Charles W. Gainey, Jr., Klaus Meissner, Damian L. Osisek, Klaus Werner
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Patent number: 8930601Abstract: A transaction routing device (e.g. an interconnect) for routing transactions in an integrated circuit includes arbitration circuitry for performing arbitration between a plurality of candidate transactions using attribute values associated with the candidate transactions. Candidate transactions are selected for routing to a destination device in dependence on the arbitration. In a cycle in which a new candidate transaction is received, the arbitration is performed using a default attribute value as the attribute value for the new transaction. Meanwhile, the actual attribute value is stored to an attribute storage unit. In a following processing cycle, if the new candidate transaction has not yet been selected for muting, then the arbitration is performed using the actual attribute value stored in the storage unit.Type: GrantFiled: February 27, 2012Date of Patent: January 6, 2015Assignee: ARM LimitedInventor: Arthur Laughton
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Patent number: 8930602Abstract: In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.Type: GrantFiled: August 31, 2011Date of Patent: January 6, 2015Assignee: Intel CorporationInventors: Kie Woon Lim, E-Liang Chew, Khee Wooi Lee, Darren L. Abramson
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Patent number: 8924751Abstract: A method is provided for a SAS (Serial Attached SCSI (Small Computer System Interface)) expander to manage power consumption of a wide port that includes multiple expander phys each operable in at least three power conditions. The method includes monitoring number of AIP primitives for the wide port over time, changing at least one expander phy to a lower power condition when the number of AIP primitives total less than a first threshold over a first period of time, and changing at least one expander phy to a higher power condition when the number of AIP primitives total more than a second threshold over a second period of time.Type: GrantFiled: July 31, 2012Date of Patent: December 30, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael G. Myrah, Balaji Natrajan, Pruthviraj Herur Puttaiah
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Patent number: 8924613Abstract: A data processing device includes a master arbitrating unit assigning information to a command sent from a selected bus master, a data buffer, a write command buffer, a read command buffer, a write data reception completion notification control unit issuing a signal indicating that storing of write data is complete, and a command order determining unit selecting whichever of a first command and a second command coming earlier in an order identified with the information, the first information being information for which the completion is indicated by the signal and a second command being a read command.Type: GrantFiled: January 17, 2014Date of Patent: December 30, 2014Assignee: Panasonic CorporationInventor: Takashi Yamamoto
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Patent number: 8918786Abstract: A multiprocessing system executes a plurality of processes concurrently. A process execution circuit (10) issues requests to access a shared resource (16) from the processes. A shared access circuit (14) sequences conflicting ones of the requests. A simulating access circuit (12) generates signals to stall at least one of the processes at simulated stall time points selected as a predetermined function of requests from only the at least one of the processes and/or the timing of the requests from only the at least one of the processes, irrespective of whether said stalling is made necessary by sequencing of conflicting ones of the requests. Thus, part from predetermined maximum response times, predetermined average timing can be guaranteed, independent of the combination of processes that is executed.Type: GrantFiled: March 26, 2008Date of Patent: December 23, 2014Assignee: NXP, B.V.Inventors: Marco J. G. Bekooij, Jan W. Van Den Brand
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Patent number: 8856415Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.Type: GrantFiled: February 1, 2012Date of Patent: October 7, 2014Assignee: National Instruments CorporationInventor: Sundeep Chandhoke
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Patent number: 8843682Abstract: Described embodiments provide arbitration for a cache of a network processor. Processing modules of the network processor generate memory access requests including a requested address and an ID value corresponding to the requesting processing module. Each request is either a locked request or a simple request. An arbiter determines whether the received requests are locked requests. For each locked request, the arbiter determines whether two or more of the requests are conflicted based on the requested address of each received memory requests. If one or more of the requests are non-conflicted, the arbiter determines, for each non-conflicted request, whether the requested addresses are locked out by prior memory requests based on a lock table. If one or more of the non-conflicted memory requests are locked-out by prior memory requests, the arbiter queues the locked-out memory requests. The arbiter grants any non-conflicted memory access requests that are not locked-out.Type: GrantFiled: September 30, 2011Date of Patent: September 23, 2014Assignee: LSI CorporationInventor: Shashank Nemawarkar
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Publication number: 20140281086Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.Type: ApplicationFiled: May 30, 2014Publication date: September 18, 2014Inventors: Tommaso Bacigalupo, Torsten Hinz
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Patent number: 8838863Abstract: The present application relates to a method for resource controlling comprising controlling the processing of requests of a first category having a first priority. The method comprises controlling the processing of requests of a second category having a second priority, wherein the first priority is set such that processing the requests of the first category has priority over processing the requests of the second category. The method comprises blocking requests of the first category by a mechanism that detects when a predefined condition regarding the service provided to the second category is met.Type: GrantFiled: November 9, 2009Date of Patent: September 16, 2014Assignee: Synopsys, Inc.Inventors: Tomas Henriksson, Elisabeth Francisca Maria Steffens
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Patent number: 8818276Abstract: Example method, apparatus, and computer program product embodiments are disclosed to enable granting access rights to guest devices. Example embodiments include a method comprising receiving, by a first device, an input from a user of the first device to grant access rights to a wireless short-range communication network to a user of a second device when the first device is present within coverage of the wireless short-range communication network; and transmitting, by the first device, an access grant message to a control node managing the wireless short-range communication network, wherein the access grant message comprises one or more rules indicating that access rights for a second device are to be granted only when the first device is present within coverage of the wireless short-range communication network.Type: GrantFiled: May 16, 2012Date of Patent: August 26, 2014Assignee: Nokia CorporationInventors: Niko Kiukkonen, Janne Marin, Jukka Reunamaki, Sverre Slotte
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Patent number: 8769176Abstract: A system including a first communication module to transmit or receive data via an antenna in accordance with a first communication standard; a second communication module to transmit or receive data via the antenna in accordance with a second communication standard; and an arbitration module. The arbitration module outputs a first mutual grant where both the first communication module and the second communication module are able to simultaneously transmit data via the antenna; a second mutual grant where both the first communication module and the second communication module are able to simultaneously receive data via the antenna; a third mutual grant where the first communication module and the second communication module are able to simultaneously transmit and receive data, respectively, via the antenna; and a fourth mutual grant where the first communication module and the second communication module are able to simultaneously receive and transmit data, respectively, via the antenna.Type: GrantFiled: August 14, 2012Date of Patent: July 1, 2014Assignee: Marvell International Ltd.Inventors: Gladys Yuen Yan Wong, Timothy J. Donovan, Timothy Li, Ken Yeung
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Patent number: 8769546Abstract: Method to selectively assign a reduced busy-wait time to threads is described. The method comprises determining whether at least one thread is spinning on a mutex lock associated with a condition variable and assigning, when the at least one thread is spinning on the mutex lock, a predetermined reduced busy-wait time for a subsequent thread spinning on the mutex lock.Type: GrantFiled: January 7, 2010Date of Patent: July 1, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Rakesh Sasidharan Nair, Sherin Thyil George, Aswin Chandramouleeswaran
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Publication number: 20140181343Abstract: Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.Type: ApplicationFiled: March 3, 2014Publication date: June 26, 2014Applicant: Synopsys, Inc.Inventors: Roberto Attias, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Akash Renukadas Deshpande, Navendu Sinha, Vineet Gupta, Shobhit Sonakiya
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Patent number: 8756608Abstract: A method, a system, an apparatus, and a computer program product for allocating resources of one or more shared devices to one or more partitions of a virtualization environment within a data processing system. At least one user defined resource assignment is received for one or more devices associated with the data processing system. One or more registers, associated with the one or more partitions are dynamically set to execute the at least one resource assignment, whereby the at least one resource assignment enables a user defined quantitative measure (number and/or percentage) of devices to operate when the one or more transactions are executed via the partition. The system enables the one or more devices to execute one or more transactions at a bandwidth/capacity that is less than or equal to the user defined resource assignment and minimizes performance interference among partitions.Type: GrantFiled: July 1, 2009Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Elmootazbellah N. Elnozahy, Ramakrishnan Rajamony, William E. Speight, Lixin Zhang
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Patent number: 8751715Abstract: A system, computer-implemented method, and a computer program product for regulating control of a slave device on a communications bus includes monitoring for a request for control of the slave device by a master device. Control of the slave device is granted to the master device. Control of the slave device is relinquished by the master device after the occurrence of a relinquishment event.Type: GrantFiled: March 31, 2010Date of Patent: June 10, 2014Assignee: ENC CorporationInventor: Paul Anton Shubel
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Patent number: 8745335Abstract: Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.Type: GrantFiled: June 29, 2011Date of Patent: June 3, 2014Assignee: Synopsys, Inc.Inventors: Pieter Van Der Wolf, Marc Jeroen Geuzebroek, Johannes Boonstra