Abstract: In general, embodiments of the present invention provide a Semiconductor Storage Device (SSD) memory disk unit having multiple host interface units. Specifically, in a typical embodiment, the SSD memory disk unit comprises a plurality of host interface units for coupling the SSD memory disk unit to at least one host; a host interface controller unit coupled to each of the plurality of host interface units; a DMA controller coupled to the host interface controller unit; an ECC controller coupled to the DMA controller; a memory controller coupled to the ECC controller; and a memory array coupled to the memory controller, the memory array comprising at least one SSD memory block.

Abstract: Provided is a storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type, which provides data storage/reading services through a PCI-Express interface. The PCI-Express type storage device includes: a memory disk unit which includes a plurality of memory disks provided with a plurality of volatile semiconductor memories; a PCI-Express host interface unit which interfaces between the memory disk unit and a host; and a controller unit which adjusts synchronization of a data signal transmitted/received between the PCI-Express host interface unit and the memory disk unit to control a data transmission/reception speed between the PCI-Express host interface unit and the memory disk unit.

Abstract: A removable electronic circuit card having both a memory module with a non-volatile mass storage memory and a separate input-output module so that data transfers may be made through the input-output module directly to and from the mass storage memory in a direct memory access (DMA) type transfer when the card is inserted into the host system but without having to pass the data through the host system. Once the host gives a DMA command, the data transfer is accomplished independently of the host system, except for the host supplying power and possibly a clock signal and other like support, during such a data transfer directly with card. The data for the transfer can be communicated between the input-output module and the exterior device through either wireless or an electrical connection means.

Abstract: A data storage system includes an input/output server and a storage unit. The input/output server includes a processor, memory, and a host channel adapter. The storage unit includes a processor, memory, and a storage module. The storage module includes a storage controller, and an interface block for connecting the storage module to a corresponding memory-mapped interface. The storage unit further includes a host channel adaptor. The storage unit host channel adapter is connected to a corresponding memory-mapped interface. The storage unit host channel adapter is capable of remote direct memory access to the input/output server. Protocol translation logic is configured to intercept a memory access request from the storage controller, and initiate a corresponding remote direct memory access to the input/output server through the storage unit host channel adapter and the input/output server host channel adapter.

Abstract: There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

Abstract: A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.

Abstract: A system balances bandwidth used by a data stream. The system receives data in the data stream and partitions the data into bursts. The system then identifies whether a size of a current one of the bursts is less than a size of a maximum burst associated with the data stream and schedules an additional burst in the data stream when the current burst size is less than the maximum burst size. The system transmits the current burst and the additional burst to balance bandwidth used by the data stream.

Abstract: A network switch, based on the PCI Express protocol, is disclosed. The switch includes a processor, local memory and a plurality of non-transparent bridges. By configuring the non-transparent bridges appropriately, the network switch can facilitate a number of different communication mechanisms, including TCP/IP communication between servers, server clusters, and virtualized I/O device utilization. For example, the network switch may configure the non-transparent bridges so as to have access to the physical memory of every server attached to it. It can then move data from the memory of any server to the memory of any other server. In another embodiment, the network switch is connected to an I/O device, and multiple servers are given access to that I/O device via virtualized connections.

Abstract: A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.

Abstract: A network control apparatus and network control method is provided. The network control apparatus including: a content addressable memory receiving to store a plurality of addresses which are generated by at least one master intellectual property, determining whether data corresponding to each of the plurality of stored addresses is received, and generating a determination signal; and a packet decoder transmitting each of the plurality of stored addresses and the data corresponding to each of the plurality of stored addresses to a slave intellectual property according to the determination signal. Accordingly, a multiple address issue function can be supported.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is distributed to buffer ingress managers. Within a set of ingress managers serving one buffer, each manager corresponds to one function of the buffer's corresponding host, and is programmed with criteria for identifying packets desired by that function. One copy of the packet is stored in a buffer if at least one of the buffer's ingress managers accepts it, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.

Abstract: By writing a command for transferring data from a first cluster to a second cluster and the second cluster writing data that was requested from the first cluster based on the command into the first cluster, data can be transferred in real time from the second cluster to the first cluster without having to issue a read request from the first cluster to the second cluster.

Abstract: A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues.

Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Abstract: Accessing memory on a first device from a second device is supported by reversible host/client interfacing between the devices. The reversible interfacing permits the first and second devices to be configured respectively as host and client, or respectively as client and host.

Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

Abstract: An integrated circuit (IC) card may include non-volatile memory portions, where external data files are storable, and including volatile memory portions and a microprocessor. The IC card further may include a serial interface that stores the external data file as received into the volatile memory portions, and at least an internal register that is programmable through the serial interface. The internal register manages according to the programming a serial storing into the non-volatile portions of the external data file already stored into the volatile memory portions. The serial interface and the internal register may manage the respective programming in a parallel manner.

Abstract: Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media.

Abstract: A networking packet is to be sent from a first virtual machine of a computing device to a second virtual machine of the computing device. A hardware network interface controller (NIC) of the computing device is to determine whether the networking packet is to be routed from the first virtual machine to the second virtual machine in accordance with a first approach or a second approach, based upon one or more considerations regarding a state of the computing device. The hardware NIC is then to control routing of the networking packet in accordance with the first approach or the second approach.

Abstract: A data transmission method for a universal serial bus (USB) host controller is provided. First, input data is received. A cyclic redundancy check (CRC) result of the input data is calculated, and, simultaneously, the input data is transmitted to a system memory of a host. Then, it is determined whether the input data is the last input data of a data packet. When it is determined that the input data is the last input data of the data packet, the CRC result of the last input data of the data packet is calculated. Thus, the CRC result of the data packet is accumulated. The accumulated CRC result is combined with the last input data, and transmitted the combination to the system memory of the host.

Abstract: Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.

Abstract: Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using input/output (I/O) buses such as PCI Express buses. The I/O buses are extended to allow interconnection between computer systems without having to introduce network infrastructure. A transfer controller supporting Direct Memory Access (DMA) is provided to allow even more efficient communication between computer systems.

Abstract: To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data processing device is configured so that a USB host module to be coupled to a plurality of central processing units has a plurality of pipes to communicate with an arbitrary end point of a USB device coupled from the outside of the data processing device, the data processing device also includes an access control register to specify which central processing unit should have a right to control the pipe and specify to which extent a range of the content of setting of a function for the pipe should be allowed, and a USB host interface is controlled in accordance with the content of setting of the access control register.

Abstract: Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If the invalidate queue detects an invalidation of a memory page associated with that entry, then it is marked invalid. If the entry is marked invalid during the DMA transfer, then that DMA transfer is aborted. This enables, among other things, DMA transfers to unpinned virtual memory.

Abstract: A motherboard system is provided. The motherboard system includes a central processing unit (CPU), a control unit and an interface connector. The control unit is electrically connected to the CPU. The interface connector is electrically connected to the control unit and has a boot loader interface unit and a peripheral storage device interface unit, wherein the boot loader interface unit is electrically connected to the control unit and is configured for electrically connecting a system read only memory. When the power of the motherboard system is turned on, the CPU sends a read only memory fetch cycle to the control unit and fetches a booting program from the system read only memory configured in an external device via the boot loader interface unit. Accordingly, the system read only memory can be conveniently updated and maintained.

Abstract: A memory controller, such as a SDRAM controller, controls the way in which data is retrieved, in order to make more efficient use of the bandwidth of the memory data bus. More specifically, when a memory access request requires multiple data bursts on the memory bus, the SDRAM controller stores the data from the multiple data bursts in respective buffers. Data is then retrieved from the buffers such that data is read from a part of the first buffer, then from the other buffers, and finally from the remaining part of the first buffer. Storing the required data in the remaining part of the first buffer avoids the need to occupy the memory bus with a new data burst.

Abstract: A computer and a method for accessing data in the computer are provided. The computer comprises a mainboard chipset, a conventional hard disk, a flash memory and a controller. The controller is connected with the flash memory and selectively stores data to the hard disk or the flash memory according to the command from the mainboard chipset. The mainboard chipset is the south bridge chipset. The controller comprises a data interface unit in communication with the south bridge chipset, a controlling unit configured to receive the command through the data interface unit, and a flash memory accessing unit connected with the flash memory. The controlling unit controls the flash memory accessing unit to exchange the data with the south bridge chipset through the data interface unit according to the received command.

Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.

Abstract: This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

Abstract: Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user.

Abstract: A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.

Abstract: A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues.

Abstract: A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.

Abstract: Two logical partitions within a single computer communicate with each other internally. The protocol stack of a first logical partition generates a frame in a memory space provided in a driver and referred to by the first logical partition. The driver transfers the frame generated in the memory space of the first logical partition to a communication port of a Layer 2 switch using DMA. The communication port of the Layer 2 switch loops back the frame input from the driver. An interrupt is signaled to the driver and the frame is transferred from communication port of the Layer 2 switch to the driver using DMA. The frame is received in a memory space referred to by a second logical partition.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: A bridge circuit includes a bus, a memory interface module, a memory control module, and an external storage control module. The memory interface module receives a memory address from a processor via a memory interface and outputs the memory address to the bus. The memory address corresponds to one of a plurality of address regions of an address space of the processor. The memory control module receives the memory address via the bus and communicates with a memory when the memory address corresponds to a first one of the plurality of address regions. The external storage control module receives the memory address via the bus and communicates with an external storage device when the memory address corresponds to a second one of the plurality of address regions.

Abstract: The present invention provides a USB host controller and control method thereof. The USB host controller comprises a first controller, a second controller and a first memory. The first controller controls first transfer between a host and a USB device. The second controller controls second transfer between the host and the USB device. The first memory is coupled to the first controller and the second controller and is configured to temporarily store data transferred between the host and the USB device. The first controller accesses the first memory during the first transfer, and the second controller accesses the first memory during the second transfer.

Abstract: A device information management system for managing device information of various peripheral devices is disclosed. The system includes a central processing unit, a logic controller connected with the central processing unit, a first device connected with the logic controller, wherein the first device has a device information stored in a memory unit for identifying the first device, and a second device connected with the first device, wherein the first device outputs an access command to the second device and the second device accesses the memory unit to retrieve the device information of the first device according to the access command.

Abstract: An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

Abstract: A method of communicating data between an external storage device and a USB host via a USB device is disclosed. The method includes receiving data from the USB host; and either (1) directly communicating the received data to the external storage device via an exclusive bus, or (2) indirectly communicating the received data to the external storage device via a USB bus, separate from the exclusive bus.

Abstract: Example embodiments of the invention are disclosed for an adaptive computing platform wherein a reader/writer device uses distributed, external memory resources as non-volatile memory blocks to provide distributed execution-in-place capability for the reader/writer device, such as a mobile phone, to enhance the processing power of the device. The execution architecture of the reader/writer device is scalable and adaptive to accommodate variations in the speed, size, and other characteristics of different external memory blocks it uses as it moves from one external memory block to another.

Abstract: Disclosed is a method that simultaneously transfers DMA data from a peripheral device to a hardware assist function and processor memory. A first DMA transfer is configured to transfer data from the peripheral to a peripheral DMA engine. While receiving the data, the DMA engine simultaneously transfers this data to processor memory. The DMA engine also transfers a copy of the data to a hardware assist function. The DMA engine may also simultaneously transfer data from processor memory to a peripheral device while transferring a copy to a hardware assist function.

Abstract: Flow control mechanisms avoid or eliminate retries of transactions in a coherency interconnect. A class of transaction (CoT) framework is defined whereby individual transactions are associated with CoT labels consistent with chains of dependencies that exist between transactions initiated by any of the cooperating devices that participate in a given operation. In general, coherency protocols create dependencies that, when mapped to physical resources, can result in cycles in a graph of dependencies and deadlock. To support architectural mechanisms for deadlock avoidance, CoT labels are applied to individual transactions consistent with a precedence order of those transactions both (i) with respect to the operations of which such transactions are constituent parts and (ii) as amongst the set of such operations supported in the coherency interconnect.

Abstract: A method and apparatus are provided that include creating an image of a page descriptor at a universal serial bus (USB) device, transferring the image of the page descriptor to a main memory, modifying a schedule list in a main memory based on the transferred image, identifying an active transaction in the modified schedule list, and providing code data to the USB device from the main memory based on the identified active transaction.

Abstract: A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: An interface arrangement (24) is disclosed that provides an interface between a signal line (5) for connecting external peripheral devices and a microcontroller bus (3). Data input and output interfaces (1, 2; 4) are provided for connecting corresponding register units (6, 7) to the bus systems (3, 5) and are connected through a buffer memory (8). This is, moreover, coupled with a direct memory access (DMA) controller (9). A control signal generator is also provided for the flexible generation of control signals (10). The proposed arrangement thus permits a high data transfer rate when operating peripheral devices with a system-on-chip, without demanding computing time from the microcontroller.